Digi ana total 2012

Courses In
Electrical
Engineering

Volume II

ELECTRICAL, DIGITAL AND INDUSTRIAL CIRCUITS

EXAM QUESTIONS WITH SOLUTIONS
(2012 academic year)

By

Jean-Paul NGOUNE

DIPET I (Electrotechnics), DIPET II (Electrotechnics)
M.Sc. (Electrical Engineering)
Teacher in the Electrical Department, GTHS KUMBO, Cameroon.

Exam questions with solutions_2012_Jean-Paul NGOUNE 1

Foreword

This is a compilation of some exam questions that I gave to my students during this
academic year. They are accompanied by solutions proposed by me. I will be delight
if this book can be of any use for you. I will also be very happy to receive any critic or
suggestion from you. I dedicate this book to my students of Class 6, Electrical
Technology, GTHS Kumbo, 2012 batch. They are a bit stubborn, but I like to teach
them. May you be blessed as you are using this book.

NGOUNE Jean-Paul.
17 May 2012.


Acknowledgement

Most of the questions treated in this book are “Probatoire Technique” past questions
proposed by the Cameroon General Certificate of Education Board (GCEB) and the
“Office du Baccalaureat du Cameroun” (OBC).


Contents

Item Page

Foreword 2

Acknowledgment 3

Contents 4

First sequence exam with solution 5

Second sequence exam with solution 13

Third sequence exam with solution 30

About the author 46


Courses In
Electrical
Engineering

Volume II

DIGITAL ELECTRONICS

FIRST SEQUENCE EXAM WITH SOLUTION

By

Jean-Paul NGOUNE



REPUBLIC OF CAMEROON FIRST SEQUENCE EXAM
Peace – Work – Fatherland
Class: F36
……………
GTHS KUMBO/ ELECT DPT Option: Electrotechnology
Duration: 2H30
Coefficient: 4
DIGITAL CIRCUITS
No document is allowed except the one given to
the candidates by the examiners

I TECHNOLOGY
1.1 Give the meaning of the following abbreviations: TTL, CMOS, SSI, LSI,VLSI.
1.2 Give the rated voltage used to supply TTL integrated circuits.
1.3 Give the rated voltage used to supply CMOS integrated circuits.
1.4 Give the difference between digital representation and analogue representation.
1.5 Give two examples of digital apparatus and two examples of analogue apparatus.
1.6 Define the following notions used in the field of integrated circuits:
a. Noise immunity;
b. Celerity;
c. Integration scale.

II DIGITAL CIRCUITS

Exercise 1: Numeration systems and codes.
The information stored in a register of a ROM is given as follows: X = F8DA.
1. What is the meaning of ROM?
2. What is the numeration system used to codify that information?
3. Convert X into binary.
4. Convert X into octal.
5. Convert X into decimal.
6. X is made up of how many bits?
7. Knowing that one byte = 8 bits, Give the length of the memory word X in terms
of bytes.


Exercise 2: Logic gates.
The following figure is a digital circuit having four inputs A, B, C, D and one output X.

A

X

B
C
D
1. Determine the expression of the output X.
2. Draw the truth table of the digital circuit.
3. Draw the logic circuit above using exclusively 2 input AND gates, 2 input OR
gates and 2 input NAND gates.
4. Knowing that the IC 4081 is a quad 2-input AND gate, the IC 4011 is a quad 2-
input NAND gate and the IC 4071 is a quad 2-input OR gate, determine the
number of IC 4081,IC 4011 and IC 4071 that should be used to realise the
digital circuit above.

Exercise 3: Realisation of gate circuits.
Realise the logic circuit corresponding to each of the following expressions:
X A.B(C D)

Y A B CD E BC D

Z A B PQ CD

Proposed by Mr. NGOUNE Jean-Paul,
PLET Electrotechnics, GTHS KUMBO.


PROPOSITION OF SOLUTION

I TECHNOLOGY
1.1 Meaning of the abbreviations:
TTL: Transistor Transistor Logic.
CMOS: Complementary Metal Oxide Semiconductor.
SSI: Small Scale Integration.
LSI: Large Scale Integration.
VLSI: Very Large Scale Integration.
MSI: Medium Scale Integration.

1.2 Rated voltage for the supply of TTL integrated circuit: 5V+/-0.25V.
1.3 Rated voltage used for the supply of CMOS IC: 5V, 15V, 18V.
1.4 Difference between analogue representation and digital representation:
Analogue representation Digital representation
Infinitely divisible Discrete (Step by step)
Prone to errors of precision Absolute precision

1.5 Examples of digital apparatus: electronic watch, computer, mobile phone, digital
camera…
Examples of analogue apparatus: radio, oscilloscope, some model of TV,
analogue multimeter.
1.6 Definitions:
Noise immunity: It is the ability of an integrated circuit not to be disturbed in his
functioning by an external signal (electromagnetic signal). A noise can be defined as
a signal that disturbs the useful signal of being well treated by an electronic device.

Celerity: It is the speed at which electrical information are being treated by an
integrated circuit.
Integration scale: it is a range that informs on the amount of transistors used in the
manufacture of an integrated circuit. There are many integration scales (SSI, MSI,
LSI, VLSI, ULSI).


II DIGITAL CIRCUITS

Exercise 1: Numeration systems and codes.
The information stored in a ROM is given as follows: X = F8DA.
1. ROM stands for Read Only Memory. It is a type of memory in which data,
once they are written, can only be read.
2. The numeration system used to codify that information is the hexadecimal
numeration system.
3. Conversion of X into binary: X = 1111100011011010 2.
4. Conversion of X into octal: X = 1743328.
5. Conversion of X into decimal: X = 6370610.
6. X is made up of 16 bits.
7. X = 2Bytes.

Exercise 2: Logic gates.
Let us consider the following digital circuit:
A

X

B
C
D
1. Expression of the output X:
X AC AC B B C D

2. Truth table of the digital circuit:


A B C D X
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

3. Let us draw the circuit using exclusively: 2 input AND gates, 2 input OR gates
and 2 input NAND gates:
Using gate universality principle, we can convert the logic gates used in the designing
of the logic circuit into those required.
A /A = A /A

A
A
B = B
C A+B+C
C

A
A
B = B
C ABC
C


Then the logic circuit can be redrawn as follows:

A

X

B

C

D

4. Number of integrated circuit of each type to be used:
 Number of AND gates in the circuit: 3; therefore 1 IC 4081is sufficient (one IC
contains 4 gates).
 Number of NAND gates in the circuit: 2; therefore 1 IC 4011 is sufficient (one
IC contains 4 gates).
 Number of OR gates in the circuit: 4; therefore 1 IC 4071 is sufficient (one IC
contains 4 gates).
So, with 1 IC 4081, 1 IC 4011 and 1 IC 4070 the logic circuit can be designed.

Exercise 3: Realisation of gate circuits:
Let us realise the logic circuits corresponding to each of the following equations:
X A.B(C D)
Y A B CD E BC D

Z A B PQ CD


A B C D

X

A B C D E

Y

A B C D P Q

Z


Courses In
Electrical
Engineering

Volume II


SECOND SEQUENCE EXAM WITH SOLUTION

By

Jean-Paul NGOUNE



REPUBLIC OF CAMEROON SECOND SEQUENCE EXAM
Class: F36
……………
Duration: 04H
Coefficient: 4
Written paper


the candidates by the examiners.

SECTION ONE : TECHNOLOGY
1.1 Give the value of a resistance having the following colour code: red-orange-
yellow-gold.
1.2 Give the meaning of the following abbreviations: TTL, CMOS, JFET, LSI, USB,
and EPROM.
1.3 Give two protective means against overheat of semiconductors.
1.4 Name the parameters that characterize the operating point of a bipolar transistor.
1.5 Give two parameters that determine the choice of a Zener diode.
1.6 Define the following terms used in the field of integrated circuits: a) Noise
immunity, b) Celerity, c) Integration scale.
1.7 Give the difference between a diode and a thyristor.
1.8 Give the symbol and one application area of each of the following electronic
components: a) Transistor, b) Junction diode, c) Zener diode.
1.9 Describe the functioning principle of a thyristor.

SECTION TWO: ANALOG CIRCUITS
Exercise 1: Alternating current (1).
The circuit of figure 1 bellow is supplied by an ac voltage u.
i R1

R1 = 220Ω ; R2 = 1kΩ ; C = 4.5µF ; f = 50Hz
u(t) u'(t) u (t ) 120 2 sin 100 t .
R2
C
1. Determine the total impedance of the circuit.

Figure1


2. Show that the expression of the current i flowing in the circuit is given by
i I 2 sin 100 and determine the value of I and .
3. Show that the expression of the voltage u’(t) is given by
u ' (t ) U ' 2 sin 100 t and determine the value of U’.
Exercise 2: Alternating current (2)
The circuit of figure 2 bellow is connected to a voltage v(t ) 220 2 sin 100 t volts.

i1 R1 L

i
i2 C R2

Figure2
Given thatR1 = 100Ω; R2 = 150Ω; L = 0.24 H and C = 16µF.
1. Determine the following complex impedances:
a. Z1 for the branch (R1 + L)
b. Z2 for the branch (C + R2)
2. Calculate the complex values of i1, i2 and i.
3. Draw the phasor diagram of the currenti1, i2 and i.
Exercise 3: DC circuit
Consider the following circuit in figure 3.
A K

E1 = 12V, E2 = 6V, Ro= 20Ω, R1 = 10Ω, R2 = 4Ω
and R = 5Ω.
1. Determine the characteristics of the Norton
R1 E2 equivalent generator seen from terminals A
RO R
and B when K is opened.
R2
E1 2. Deduce the corresponding Thevenin,s
equivalent model.
3. Calculate the value of current I in the load R
and the voltage drop across it when K is
B
closed.
Figure3


Exercise 4: Bipolar transistor
The two transistors of figure 4 bellow are in silicon such that V BE1 = VBE2 = 0.7V,
β1=100, β2=200. The operating point is such that UEM = 5V for UAM = 20V.R1=1kΩ,
R2=1kΩ, R3=10kΩ
A
1. Calculate the current i1 flowing
through the resistance R1.

R3
2. Determine the voltage across the
10k
UAM
T1 resistance R3 and the current I3
B1 flowing through this resistance.
3. Neglecting IB2 with respect to I1,
calculate the base current IB1of the
R B2 T2

E transistor T1.
UEM
4. Calculate IC2, hence, deduce IB2
R1
1k
R2 and verify that IB2 is negligible with
1k

respect to I1
5. Calculate the voltage across R and
M the current crossing it. Hence,
Figure4
determine the resistance R.

SECTION THREE: DIGITAL CIRCUITS
Exercise 5: Multiplicator circuit.

The figure 5 below shows the block diagram of an electronic circuit which accepts
two binary numbers of two bits X1X0 and Y1Y0, and gives at the output the binary
number Z3Z2Z1Z0 which is equal to the arithmetic product of the two input numbers.
For the inputs, X0 and Y0 are the least significant bits (LSB) while for the outputs, Z3
is the most significant bit (MSB).

X1 Z3

X0 Multiplicator Z2
circuit
Z1
Y1
Z0
Y0 Figure5


1. What do you understand by the statements “Least significant bit” and “Most
significant bit”?
2. Establish the truth table of the system.
3. Write the expression of each output Z3, Z2, Z1 and Z0 as function of X1, X0
Y1 andY0.
4. With the aid of Karnaugh map, simplify the output equations obtained above.
5. Draw the logic diagram of the electronic multiplicator circuit using the simplified
output equations.

Exercise 6: Parity detector
We desire to realize a 3-bit parity detector of bits B1, B2 and B3. The operation is as
follows:
- If 0 or 2 bits are at high logic level, the output is at the high level.
- If 1 or 3 bits are at high logic, the output is at the low level.
1. Draw the corresponding truth table.
2. Give the expression of the output S in terms of B1, B2 and B3.
3. Write the expression of S using the operator exclusive OR only.
4. Draw the logic diagram of S.

Exercise 7: Numeration system
Let us consider the following numbers:
A = 1101011012 B=6248 C=1A716
1. Convert A into octal and hexadecimal.
2. Convert B and C into binary.
3. Calculate:
X(2)=A(2)+ B(2); Y(16)=A(16)+ C(16) W(8)=A(8 ) – B(8)

SUBJECT MASTER: NGOUNE Jean-Paul,


PROPOSITION OF SOLUTION

SECTION ONE: TECHNOLOGY
1.1 Value of a resistor having the following colour code: Red – Orange – Yellow –
Gold. R = 23 x 104Ω+/- 5% = 230kΩ
1.2 Meaning of the abbreviations:
 TTL = Transistor Transistor Logic;
 CMOS = Complementary Metal Oxide Semiconductor;
 JFET = Junction Field Effect Transistor;
 LSI = Large Scale Integration;
 USB = Universal Serial Bus;
 EPROM = Erasable Programmable Read Only Memory.
1.3 Two protective means against overheat of semiconductors:
 Use of heat sink (radiator)
 Use of fan (ventilation)
1.4 Parameters characterising the operating point of a bipolar junction transistor:
 IBQ = Base current at the quiescent point;
 VBEQ = VBE at the quiescent point;
 ICQ = Collector current at the quiescent point;
 VCEQ = VCE at the quiescent point.
1.5 Parameters of choice of a Zener diode:
 Zener voltage;
 Reverse current;
VZ
 Coefficient .
IZ
1.6 Definition of terms:
 Noise immunity: Degree of protection of an IC against noise. A noise is an
undesirable signal that disturbs the functioning of an IC.
 Celerity: Speed of propagation of signal through a circuit. Speed at which an
electronic circuit treats information.
 Integration scale: Number of components (transistors) integrated per surface
unit of a chip. There are many integration scales: SSI, MSI, LSI, VLSI, VLSI.


1.7 Difference between diode an thyristor: A diode is a non controlled unidirectional
rectifier component, a thyristor is a controlled unidirectional rectifier component.
1.8 Symbol an application of electronic components:
Component Symbol Application area
Bipolar Amplifier, Chopper
transistor

Junction Rectification
diode (Non controlled)

Zener
diode Stabilisation

1.9 Functioning principle of a thyristor: When a positive voltage is applied across a
thyristor (VAK > 0), a sufficient gate current (IG > Igm) permits to trigger it on. The
current keeps on passing through it even if the gate current is removed
(hysteresis effect). To trigger off a thyristor, a negative voltage should be applied
across it.

SECTION TWO: ANALOGUE CIRCUITS

Let us consider the following circuit:
i R1

u(t) u'(t) R1 = 220Ω ; R2 = 1kΩ ; C = 4.5µF
R2
C f = 50Hz
u (t ) 120 2 sin 100 t

1. Total impedance of the circuit:
ZT R1 R2 Z C ;

1 1
With Z C j j j 707.714 .
C 2 f 4.5 10 6 314
Hence,


R2 Z C 1000 j 707.714 707714 90
ZT R1 220 220
R2 Z C 1000 j 707.714 1225.095 35.28
ZT 220 577.68 54.72 553.65 j 471.58
ZT 727.26 40.42
2. Let us show that the expression of the current i flowing in the circuit is given
by: i (t ) I 2 sin 100 t .
U 120 0
I 0.165 40.42 0.165 2 sin 100 t 40.42
ZT 727.26 40.42
With I = 0.165 A and 40.42 .

3. Let us show that the voltage u’(t) is given by u ' (t ) U ' 2 sin 100 t .
The circuit can be redrawn as follows:
R1

u(t) u'(t)
Z0

With Z 0 R2 Z C 577.68 54.72

U
U' Z 0 (Voltage divider).
ZT
120 0
U' 577.68 54.72 95.318 14.30
727.26 40.42
u ' (t ) 95.318 2 sin 100 t 14.30
Where U’ = 95.318V and 14.30 .

Let us consider the following circuit:

i1 R1 L

i
i2 C R2


v(t ) 220 2 sin 100 t ; R1 = 100Ω; R2 = 150Ω; L = 0.24 H, C = 16µF
1. Determination of impedances:
 Branch (R1 + L)
Z1 R1 jL 2 f 100 j 75.36 1.757 37
 Branch (C+R2)
1 1
Z2 R2 j 150 j 150 j199.044 0.8827 52.99
C 16 10 6 314
2. Complex values of the currents i1, i2 and i.
V 220 0
I1 1.757 37 1.403 j1.057 A
Z1 125.21 37
V 220 0
I2 0.8827 52.99 0.531 j 0.704 A
Z2 249.235 52.99
I I1 I2 1.403 j1.057 0.531 j 0.704 1.934 j 0.353 1.965 10.34 A
4. Phasor diagram.
We have already the modulus and the argument of each current:
I1 1.757 37 A
I2 0.8827 52.99 A Hence, we obtain the following phasor diagram:
I 1.965 10.343 A

I2
Ref = U
O
I

I1
We notice that graphically, I1 + I2 = I.

Exercise 3: DC circuits.
Let us consider the following figure:
E1 = 12V; E2 = 6V; Ro = 20Ω; R1 = 10Ω; R2 = 4Ω


A K

R1 E2
RO R

R2
E1

B
1. Norton equivalent generator seen from terminals A and B when K is open:
The circuit obtained when K is open can be redrawn as follows:
A

R1
E2
R0

R2
E1

B

RN R0 R1 R2
1 1 1 1 1 1 1 8
RN R1 R2 R0 10 4 20 20
20
RN 2 .5
8
E1 E2 12 6
IN 2 .7 A
R1 R2 10 4
2. Thevenin’s equivalent model:
RTH
A A

RN
In Eth

B B


ETH RN I N 2.5 2.7 6.75V
RN RTH 2.5
3. Value of the current flowing in the resistor R when K is closed:
Using the Thevenin’s model obtained above, we have:

R TH A

R
E th

B
ETH 6.75
I 0 .9 A
RTH R 2 .5 5
VR R I 5 0 .9 4.5V

Exercise 4: Bipolar transistor.
Let us consider the following figure:
A

R3 UAM
10k
T1

B1

R B2 T2

E
UEM
R1
1k
R2
1k

M

VBE1 = VBE2 = 0.7V; β1 = 100; β2 = 200. At the operating point, UEM = 5V; UAM = 20V.
R1 = 1kΩ; R2 = 1kΩ; R3 = 10kΩ.
1. Current I1 flowing in R1.
U EM 5
I1 5mA
R1 1000


2. Voltage across R3 and current through it.
U EM VBE1 R3 I 3 U AM 0
R3 I 3 U AM U EM VBE1 20 5 0.7 14.3V
14.3 14.3
I3 1.43mA
R3 10000

3. IB2<< I1; calculation of IB1.
I1 I E1 1 1 I B1
IB2<< I1 I1 5 10 3
I B1 49.504 A
1 1 101

4. Determination of IC2.
6 6
IC 2 I3 I B1 1.43 10 49.504 10 1.3804mA
3
IC 2 1.3804 10
I B2 6.902 A
2 200

I1 5 10 3
6
724.42 , so IB2 is negligible with respect to I1.
I B2 6.902 10

5. Voltage across R and value of R.
U EM VR VBE 2 R2 I E 2 ; But I E 2 IC 2
3
VR U EM VBE 2 R2 I E 2 5 0.7 1000 1.3804 10 2.9196V
VR 2.9196
R 6
0.403M
I B2 6.902 10

Exercise 5: Multiplicator circuit.
1.
 The least significant bit (LSB) of a binary number is the less weighted bit of
that number (situated at the extreme right of the number).
 The most significant bit of a binary number is the most weighted bit of that
binary number (situated at the extreme left of the number).

2. Truth table of the system.


X1 X0 Y1 Y0 Z3 Z2 Z1 Z0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 0 1 0
0 1 1 1 0 0 1 1
1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 0 1 1 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 1 1 0
1 1 1 1 1 0 0 1

3. Expression of each output in function of X1, X0, Y1, Y0.
Z3 X 1 X 0Y1Y0
Z2 X 1 X 0Y Y0 X 1 X 0Y1Y0 X 1 X 0Y1Y0
Z1 X 1 X 0Y1Y0 X 1 X 0Y1Y0 X 1 X 0 Y1Y0 X 1 X 0Y1Y0 X 1 X 0 Y1Y0 X 1 X 0Y1Y0
Z0 X 1 X 0 Y1Y0 X 1 X 0Y1Y0 X 1 X 0 Y1Y0 X 1 X 0Y1Y0
4. Simplification of equations using K-maps.
Z3 is unchanged:
Z3 X 1 X 0Y1Y0


Z2
Y1Y0
X1X0 00 01 11 10
00
01
11 1
10 1 1

Z2 X 1Y1Y0 X 1 X 0Y1

Z1
Y1Y0
X1X0 00 01 11 10
00
01 1 1
11 1 1
10 1 1

Z1 X 1Y1Y0 X 1 X 0Y0 X 1 X 0Y1 X 0Y1Y0

Z0
Y1Y0
X1X0 00 01 11 10
00
01 1 1
11 1 1
10

Z0 X 0Y0

6. Logic diagram of the multiplicator circuit:


X1 X0 Y1 Y0

Z3

Z2

Z0

X1 X0 Y1 Y0

Z1

Exercise 6: Parity detector.
1. Truth table of the parity detector. Following the description of the functioning of
the circuit, the following truth table can be drawn:


B1 B2 B3 S
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

2. Expression of the output S in terms of B1, B2 and B3:
S B1.B2 .B3 B1B2 B3 B1 B2 B3 B1B2 B3

3. Expression of S using the operator Exclusive OR only.
From the expression above, we have:
S B1 B2 .B3 B2 B3 B1 B2 .B3 B2 B3
S B1 B2 B3 B1 B2 B3
S B1 B2 B3

4. Logic diagram of S.

B1 B2 B3

1
3
2 S


Exercise 7: Numeration system:

A = 1101011012 B=6248 C=1A716
1. Conversion of A into octal and hexadecimal.
A = 655(8); A = 1AD(16).
2. Conversion of B and C into binary.
B = 110010100(2); C = 110100111(2).
3. Calculations.
X(2) = 1101000001(2); Y(16) = 354(16) ; W (8) = 31(8).

END

ACKNOWLEDGEMENT

All the exercises solved in this document are past “Probatoire Technique”
examination questions proposed by the Cameroon General Certificate of Education
Board (CGCEB).


Courses In
Electrical
Engineering

Volume II


THIRD SEQUENCE EXAM WITH SOLUTION

By

Jean-Paul NGOUNE

M.sc. (Electrical Engineering)


REPUBLIC OF CAMEROON THIRD SEQUENCE EXAM
Class: F36
……………
Duration: 04H
Coefficient: 4
Written paper


the candidates by the examiners.

SECTION ONE : TECHNOLOGY

1.1 Define: Combinatory logic circuit; sequential logic circuit, decoder, multiplexer,
flip-flop.
1.2 Give the meaning of the following abbreviation: PMOS, ECL, USB, ALU, TTL.
1.3 What are the properties of a linear operational amplifier?
1.4 What are the modes of functioning of an OPMP?
1.5 The following symbol is that of the LM741 which is one of the most commonly
used OPAMP. Give the name of terminals 1, 2, 3,4,5,6 and 7.
7
1

3
6
2
4
5

1.6 Consider the following table. Indicate by putting a cross in the appropriate cell,
the nature of the each component (Active or passive component).
Resistor Transistor Inductor Capacitor Diode
Active
component
Passive
component

1.7 What is the difference between a multiplexer and a demultiplexer?
1.8 Give two protective means against overheat of semiconductors.


SECTION TWO: ANALOGUE CIRCUITS
Exercise 1: Alternating current.
Consider the circuit of figure 1 bellow.
A
e1 = 220V, e2 = j110V, ZL = j103Ω, ZC = -j500Ω,
L Z = 103Ω.
C
1. Determine the characteristics of the Norton’s
Z
equivalent generator seen from terminals A
and B.
e1 e2
2. Determine characteristics of the Thevenin’s
B equivalent generator seen from terminals A
Figure 1. and B.
3. Using Norton’s equivalent generator, determine the complex value of the
current i flowing in the load Z. Deduce its effective value.
4. Using Thevenin’s equivalent generator, determine the complex value of the
current i flowing in the load Z. Deduce its complex value.

Exercise 2: DC current.
The circuit of the figure 2 bellow is a voltage stabilizer. The voltage U1 varies

I2 from 10V to 16 V.
The Zener diode is ideal
U1 U2
IB with PZmax = 15mW;
RP
R
Iz Uz = 12V. For the bipolar

Uz transistor, take β = 100,
VBE = 0.7V. Let
R = 300Ω
Figure 2.
1. Determine the maximal current IZmax of the Zener diode.
2. For U1 = 16V, determine the values of U2 and RP so that the current in the
diode must be maximal.
3. Using the value of RP obtained in question 2 above, determine the maximal
value of U1 for which the Zener diode is blocked (Iz = 0).
4. Using the value of RP obtained above, determine the current I2 and the
voltage U2 in the following cases: a) U1 = 10V; b) U1 = 14V.


Exercise 3: Bipolar transistor amplifier.
Consider the transistor amplifier circuit presented on the figure 3 below.

For the transistor:
R2 RC
= 99; r = 2kΩ ,
C2
ICQ = 4.95mA, VBEQ = 0.7V.
C1
v2 Take: Vcc = 12V,
VCC
RG
RU
R1 = 2kΩ, RC = 2kΩ,
v1
R1 RU = 2kΩ,
RE
CE
e RE = 180Ω

M

A. Static study: Figure 3.
Determine:
1. The currents flowing through the base (IB) and the emitter (IE) of the transistor.
2. The voltage VBM between the base and the ground M.
3. The current IP flowing in the resistor R1.
4. The value of the resistance R2.
B. Dynamic study:
1. Give the name and the role of capacitors C1, C2 and C3.
2. Draw a.c. equivalent circuit of the amplifier.
3. Determine the input resistance and the output resistance of the amplifier.
4. Calculate the voltage amplification factor.

Exercise 4: Operational amplifier.
The OPAMPs of figure 4 bellow are ideal.
We have R = 10Ω, R1 = 4Ω,
R +Vcc
R2 = 20Ω, E =100mV and
Ve 1 V Vcc = 12V
2
R2 -Vcc Vs
1. Give the operating
R1 E
modes of the
OPAMPs 1 and 2.

Figure 4.
2. The voltage Ve is a sinusoidal expressed as: Ve 20 cos100 t (mV).


a. Determine the expression of the of the output voltage V of the
OPAMP1.
b. Represent in terms of time the voltages Ve and V.
3. Draw the waveform of the voltage Vs at the output of OPAMP2 knowing that E is a
DC source.

SECTION THREE: DIGITAL CIRCUITS.
1. Solve the following operations using 2’s complement:
a) 11100002 – 1101112; b) 1001111012 – 110111102; c) 100000002 – 11111112.
2. The figure 5 bellow represents the circuit of a full adder, where A1 and B1 are
the in put variables. R1 is the carry while So and Ro are the sum and the
reminder respectively.
2.1 Complete the truth table bellow.
A1 B1 R1 So Ro
0 0 0
0 0 1
0 1 0 A1
So
0 1 1 B1 Full Adder
Ro
1 0 0
R1
1 0 1
1 1 0 Figure 5.

1 1 1

2.2 Simplify the expressions of So and Ro using Boolean algebra method.
2.3 Draw the logigram of this full adder using logic gates.
3. At the input of a decoder, one can place 64 different combinations. Determine:
a) The number of ways at the input of this decoder,
b) The number of ways at the output of this decoder.

SUBJECT MASTER: NGOUNE Jean-Paul,


ACKNOWLEDGEMENT

All the exercises solved in this document are past “Probatoire Technique”
examination questions proposed by the Cameroon General Certificate of Education
Board (CGCEB) and the “Office du Baccalaureat du Cameroun” (OBC).

SECTION ONE: TECHNOLOGY
1.1 Definition of terms:
 Combinatory logic circuit: It is a logic circuit whose outputs depend only on the
combination of its inputs logic states.
 Sequential logic circuit: It is a logic circuit whose outputs depend on previous
inputs as well as present ones. Thus a sequential logic circuit has a memory.
 Decoder: It is a combinatory circuit which functions in such a way that for a
given input address, only one of its outputs is activated.
 Multiplexer: It is a combinatory logic circuit which permits to direct towards
single output information coming from many inputs.
 Flip-flop: It is a sequential logic circuit which is able to memorise one bit of
information (elementary memory).
1.2 Meaning of abbreviations:
 PMOS: P-type channel metal oxide semiconductor.
 ECL: Emitter coupled logic.
 USB: Universal serial bus.
 ALU: Arithmetic logic unit.
 TTL: Transistor transistor logic.
1.3 Properties of a linear operational amplifier:
 Infinite voltage gain.
 Infinite input impedance.
 Zero output resistance.
 Zero offsets (voltage and current).
 Zero bias current.
 Infinite common mode rejection ratio (CMRR).
1.4 The modes of functioning of an OPAMP are :
 Linear mode,


 Saturation mode.
1.5 Names of the terminals of the OPAMP LM741.

1. Offset null
7
1
2. Inverting input
3
6 3. Non-inverting input
2 4. Negative supply
5. Offset null
4
5

6. Output
7. Positive supply.

1.6 Nature of the components
Resistor Transistor Inductor Capacitor Diode
Active
component
Passive
component

1.7 Difference between multiplexer and demultiplexer.
A multiplexer directs towards one output information coming from many inputs
meanwhile a demultiplexer directs towards many outputs (one amongst those
outputs) information coming from one input. Thus, the demultiplexer is the reverse or
dual circuit of the multiplexer.
1.8 Two protective means against overheat of semiconductors:
 Use of fan
 Use of radiator or heat sink

SECTION TWO: ANALOGUE CIRCUITS.
Exercise 1: Alternating current.
Let us consider the following network.
A

L
C
e1 = 220V, e2 = j110V, ZL = j103Ω, ZC = -j500Ω,
Z
Z = 103Ω.

e1 e2

B


1. Norton equivalent generator seen from terminals A and B.
The circuit above can be transformed as follows:
A
A

I1 ZL Z I2 ZC Ieq ZEQ

B
B
e1 220
I1 j 0.22 A
ZL j1000
e2 j110
I2 0.22 A
With ZC j 500
I eq I1 I2 0.22 1 j A IN
Z L ZC j1000 j 500
Z eq Z L ZC j1000 ZN
Z L ZC j1000 j 500

Hence the Norton generator can be represented as follows
A

IN ZN

B
2. Thevenin’s equivalent generator seen from terminals A and B.
The circuit can be redrawn as follows:
A

Eth
L
C

e1 e2

B

e1.Z C e2.Z L 220 j 500 j110 j1000 j 500 220 j 220
ET 220 j 220V
Zc Z L j 500 j1000 j 500
ZT ZN j1000


Hence the Thevenin’s equivalent generator can be drawn as follows.
A

Z th

E th

B
3. Determination of the current flowing in the impedance Z, using Norton’s
equivalent generator.
IN A

I

IN ZN
Z

B

Using current divider theorem, we can write:
I N .Z N 0.22 1 j j1000 j1000 0.22 1 j j 1
I 0.22 0.22 A 0.22 180
ZN Z j1000 1000 1000 1 j 1 j

The effective value of the current can therefore be deduced: I = 0.22A.
4. Determination of the current flowing in the load Z using Thevenin’s equivalent
generator.
A

I
Z th

Z

E th

B

ET 220 j 220 220 1 j
I 0.22 A 0.22 180 A
ZT Z j1000 1000 1000 1 j
The effective value of the current can therefore be deduced: I = 0.22A.


Exercise 2: DC current.
Let us consider the following circuit.
I2

U1 U2
RP IB
R
Iz
Uz

1. Maximal current IZmax of the Zener diode.
3
PZ max 15 10
PZùax I Z max U Z I Z max 0.00125 A 1.25mA .
U Z max 12
2. U1=16V. Let us determine U2 and RP so that the diode current will be
maximal.
U2 UZ VBE 12 0.7 11.3V
U1 U Z
RP
I RP

But I RP IB I Z max . On the other hand we have:

I2 U2
I2 IE 1 IB IB . By replacing in the initial equation, we
1 R 1
have:
U1 U Z U1 U Z 16 12
RP 2460
U2 U2 3 11.3
I Z max I Z max 1.5 10
R 1 R 300 100
3. Maximal value of U1 for which IZ = 0.( Then IRP =IB)
U2 11.3
U1 RP I B U Z RP UZ 2460 12 12.92V
R 100 300
4. For U1 = 10V, we have U1<Uz, then IRP = 0, and UZ = 10. Hence,
U2 10 0.7 9.3V
U2 9 .3
The I 2 0.031 31mA
R 300
For U1 = 14V. Then; Uz = 12V and U2=11.3V
U2 11.3
I2 37.7 mA
R 300


Exercise 3: Bipolar transistor amplifier.
Let us consider the following transistor amplifier circuit.

For the transistor:
R2 RC
= 99; r = 2kΩ ,
C2
ICQ = 4.95mA, VBEQ = 0.7V.
C1
v2 Take: Vcc = 12V,
VCC
RG
RU
R1 = 2kΩ, RC = 2kΩ,
v1
R1 RU = 2kΩ,
RE
CE
e RE = 180Ω

M

A. Static study.
1. Determination of base and emitter current.
I CQ 4.95 10 3
IB 5 10 5 50 A
99
IE I CQ I B 50 A 4.95mA 5mA

2. Voltage VBM between the base and the ground.
3
VBM VBE RE I E 0.7 180 5 10 1.6V .
3. Determination of the current flowing in the resistor R1.
VBM 1 .6
IP 0.8mA
R1 2000
4. Determination of the value of the resistance R2.
VCC VBE RE I E
VCC R2 I B IP VBE RE I E R2
IB IP
3
12 0.7 180 5 10 12 1.6
12.235k
5 10 5 0.8 10 3 0.85 10 3

B. Dynamic study.
1. Name of the capacitors C1, C2 and C3.
 C1 and C2 are coupling capacitors.
 CE is a bypass capacitor.


2. ac equivalent circuit of the amplifier.
i1 ib iC i2
B C

v2
RG v1
RC RU
R1 R2 r BiB

e

E

3. Input and output resistances
v1
v1 R1 // R2 // r i1 R1 // R2 // r Ri 0.924k
i1
For the output resistance, the input source e should be rendered inactive (replaced
by a short circuit). Then we have,
Rout RC 2k

4. Voltage amplification factor.
v2 RC // Ru iB RC // Ru
By definition, Av
v1 riB r
The negative sign shows that the input and the output voltages are in opposition of
phase.

Exercise 4: Operational amplifier.
The OPAMPs of figure 4 bellow are ideal.
R +Vcc

Ve 1 V We have R = 10Ω, R1 = 4Ω,
2
R2 -Vcc Vs
R2 = 20Ω, E =100mV and
R1 E
Vcc = 12V

1. The OPAMP1 operates in linear mode (because of its negative feedback); The
OPAMP2 operates as a comparator (Saturation mode).


2.
a. Expression of the output voltage V.
Using the voltage divider theorem, we can write (The voltage Ve is directly applied
across R1since there is no drop across R).
V R1 R2 R2
Ve R1 V Ve 1 Ve
R1 R2 R1 R1

b. Representation of Ve and V in terms of time.
4 20
V Ve 6Ve 6 20 cos100 t 120 cos100 t
4
V
Ve
120

100

80

60

40

20

0
t
T/4 T/2 3T/4 T 5T/4 6T/4 7T/4 2T 9T/4

-120

3. Waveform of the voltage Vs.
The OPAMP2 functions as a comparator. So we have:
If V<E then Vs = -Vcc
If V>E then Vs = +Vcc, with E = 100mV.


12V
Vs
V(mV)
Ve(mV)
120

100

80

60

40

20

0
t
T/4 T/2 3T/4 T 5T/4 6T/4 7T/4 2T 9T/4

-120

-12V

1. Let us solve the following operations using 2’s complement.
a) 11100002 - 1101112
11100002 - 1101112 = 11100002 +2’s compl(1101112)
1’scompl(0110111) = 1001000 ( an implied zero has been added in front of the
number so that the two numbers should have the same number of digits)
2’s compl(110111) = 1001000 + 1 = 1001001
Hence,
11100002 - 1101112 = 1110000 + 1001001 = 10111001
The first 1 is rejected. Hence the result of the operation is 111001.

Using the same principle, we obtain the following results for the other operations.
b) 1001111012 - 110111102 = 10111112
c) 100000002 -11111112 = 12


2. Full adder.
2.1 Truth table.

A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

2.2 Simplification of So and Ro using Boolean algebra method.
S A.BCi ABCi AB.Ci ABCi

A BCi BCi A B.Ci BCi
AB Cin AB Ci

Let X = B Ci

S AX AX
A X
A B Ci

S A B Ci

Co A.BCi ABCi ABCi ABCi
The expression will not change if one of the elements of the sum of products is
duplicated (After the Boolean additive identity according to which A + A = A, A being
a Boolean variable). So we will duplicate the product ABCi three times in order to
simplify the expression easily.
Co A.BCi ABCi ABCi ABCi ABCi ABCi

BCi A A ACi B B AB Ci Ci
BCi ACi AB
Co BCi ACi AB


2.3 Logigram of the full adder using logic gates.

A B Ci
Ri

S

Ro

3. At the input of a decoder, we can place 64 different combinations
a) Number of ways at the input of the decoder.
We know that, with n ways or inputs, we can have up to 2n different input
combinations.
64 2n n 6
b) Number of ways at the output of the decoder.
The number of outputs is equal to the number of inputs combinations, since each
input combination should permit to select only one output. Hence the number of ways
at the output of the decoder is 64.


ABOUT THE AUTHOR

NGOUNE Jean-Paul was born in Foreké-Dschang,
Republic of Cameroon in 1984. He is a holder of a
Master Degree in electrical engineering, obtained in
2010 in the Doctorate School of the University of Douala
(UFD-PSI). He is also a holder of a DIPET II and a
DIPET I respectively obtained in 2009 and 2007 in the
Advanced Teacher Training College for Technical
Education (ENSET de Douala).
He is currently a permanent teacher of Electrical
Engineering at the Government Technical High School
of Kumbo, North-West region, Cameroon. His domain of
research concerns the improvement of energy
conversion techniques for an efficient generation of
electrical energy from renewable sources (especially
wind and solar energy, small and medium scale
hydropower) and digital designing using FPDs.
The author is looking for a Ph.D program in his domain
of research (he has not yet found it). Any suggestion for
this issue will be warmly welcome.

NGOUNE Jean-Paul, M.Sc., PLET.
P.O. Box: 102 NSO, Kumbo, Cameroon.
Phone: (+237) 7506 2458.
Email : jngoune@yahoo.fr
Web site: www.scribd.com/jngoune


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