Asynchronous technology

Asynchronous Technology

INVESTOR PRESENTATION

MAKING CLOCK-LESS ASYNCHRONOUS DESIGN POSSIBLE IN
MAINSTREAM BY USING EXISTING INFRASTRUCTURE

Copyright © Abstracte Technologies, India

A tech start-up with six international patents in asynchronous digital
design

We have developed a disruptive VLSI asynchronous logic design method. Design flow used
is as close to traditional one for synchronous designs as possible

A basic microprocessor was designed using the developed methodology. Following
advantages were evident during the exercise:
 Logic design was more intuitive
 Timing management was similar to synchronous
 Routing congestion problem was not encountered
 A truly modular structure was achieved (Plug and synthesize model)

The company is through with initial R&D, design and implementation and is now looking
forward for angel investment to set up a shop in US for advanced R&D and product
development


Existing technology is not the ideal choice

 Traditionally, most digital circuits are built as synchronous or clocked logic
 Clock is preferred for its simplicity in design process
 Although synchronous is the obvious choice, it is not the ideal one
 Power wastage in undue clocking
 Worst case design
 Silicon area overhead
 Inter-module dependencies


Yet! The ideal one is not the right choice

Even though asynchronous solutions have:
 No clock issues
 Lower power dissipation
 Faster speed performance (Average case design)
 Partial or complete PVT variation immunity
 Inherent modularity and concurrency

THEY ARE NOT USED, BECAUSE

 Design process is complex
 Inefficient implementation techniques requiring larger number of transistors and hence
increased power
 Lack of EDA tools
 Verification and debugging difficult
 Reimplementation effort greater


We bridged the GAP

To make asynchronous attractive, we developed a methodology where:

 We used standard EDA tools available in market
 We kept the design flow as close to synchronous as possible
 We designed timing constraints similar to synchronous setup-hold
 Made sure standard debugging and test infrastructure is compatible
 Made sure to allow maximum possible re-use of existing designs


We introduced some changes in the design flow


Our ‘Proof of Concept’

Module level example implementation (FIFO)
 180nm TSMC node
 35% of power saving as compared to synchronous counterpart
 Area overhead expected to be compensated at system level

Asynchronous microprocessor implementation
 Logic design more intuitive
 Timing management similar to synchronous
 Routing congestion problem not encountered, which is normally expected for asynchronous
 A true “plug and synthesize” architecture achieved


We are targeting the key levers of the industry

Main target will be
 Semiconductor Intellectual Property (SIP) companies such as ARM, MIPS and Authentec
 Integrated Device Manufacturers (IDM) like Intel, Atmel and Broadcom

Across applications
 Microprocessors, Microcontrollers
 Arithmetic, cryptographic cores
 Encoders/Decoders (Like JPEG)
 DSPs

The technology can also be used to design more efficient
 Multi-Clock domain synchronization
 GALS/GSLA interfaces
 Clock-less – Clocked circuits interfaces

Which allows us to target already implemented designs like modems, DSPs, SoCs
and high end microprocessors


The Industry has huge potential and demands on-going efficiency

Embedded intelligent systems
 Growth from 19% to 33% of total electronic shipments for intelligent systems
 Intelligent systems market to grow from 1.8 billion units to 4 billion units in 2015
 Embedded semiconductor market will grow at 20% CAGR from 2010 to 2015

Embedded Semiconductor
 Microcontrollers with $15 billion revenues in 2010
 Embedded MPUs and SoCs with $3.65 billion in 2010, 20% CAGR for 2010-2015

Microprocessors and Microcontrollers
 7.2 billion cores consumed in 2010, CAGR of 15% from 2010-2015, 14.4 billion cores in 2015

Wireless
 The wireless semiconductor market totaled $70 billion in 2011 and will have a compound
annual growth rate of 12 percent through 2016


Our revenue streams

Direct Sales
 We will license the technology as design library
 A standard IP licensing model of license upfront + Royalty on revenues will be followed
 We will provide support service as part of the package, necessary because of the novel nature of
technology

Consultancy and Design Services
 Consultancy will be an additional form of support mechanism to help design asynchronous
logic and improve R&D margins
 In further stages of operations, we will explore design services to optimize our revenues

Possible sales channels
 Agreements with design services companies
 On/Off site consultancy services
 Knowledge and training services
 Foundry agreements


Questions?


Asynchronous technology

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