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Computer Evolution
Lecture 2
ENIAC - background
• Electronic Numerical Integrator And
Computer
• Eckert and Mauchly
• University of Pennsylvania
• Trajectory tables for weapons
• Started 1943
• Finished 1946
—Too late for war effort
• Used until 1955
ENIAC - details
• Decimal (not binary)
• 20 accumulators of 10 digits
• Programmed manually by switches
• 18,000 vacuum tubes
• 30 tons
• 15,000 square feet
• 140 kW power consumption
• 5,000 additions per second
von Neumann/Turing
• Stored Program concept
• Main memory storing programs and data
• ALU operating on binary data
• Control unit interpreting instructions from
memory and executing
• Input and output equipment operated by
control unit
• Princeton Institute for Advanced Studies
—IAS
• Completed 1952
Structure of von Neumann machine
IAS - details
• 1000 x 40 bit words
—Binary number
—2 x 20 bit instructions
• Set of registers (storage in CPU)
—Memory Buffer Register
—Memory Address Register
—Instruction Register
—Instruction Buffer Register
—Program Counter
—Accumulator
—Multiplier Quotient
IAS Memory Format
The memory of the IAS consists of 1000 storage locations, called
words, of 40 binary digits (bits) each. Both data and instructions are
stored there. Numbers are represented in binary form, and each
instruction is a binary code. Figure 2.2 illustrates these formats. Each
number is represented by a sign bit and a 39-bit value.
A word may also contain two 20-bit instructions, with each instruction
consisting of an 8-bit operation code (opcode) specifying the operation
to be performed and a 12-bit address designating one of the words in
memory (numbered from 0 to 999).
IAS Memory Format
Structure of IAS –
detail
Registers
• Memory buffer register (MBR): Contains a word to be stored in
memory or sent to the I/O unit, or is used to receive a word from
memory or from the I/O unit.
• Memory address register (MAR): Specifies the address in memory
of the word to be written from or read into the MBR.
• Instruction register (IR): Contains the 8-bit opcode instruction being
executed.
• Instruction buffer register (IBR): Employed to hold temporarily the
right-hand instruction from a word in memory.
Registers
• Program counter (PC): Contains the address of the next instruction
pair to be fetched from memory.
• Accumulator (AC) and multiplier quotient (MQ): Employed to
hold tem-porarily operands and results of ALU operations. For example,
the result of multiplying two 40-bit numbers is an 80-bit number; the
most significant 40 bits are stored in the AC and the least significant in
the MQ.
Transistors
• Replaced vacuum tubes
• Smaller
• Cheaper
• Less heat dissipation
• Solid State device
• Made from Silicon (Sand)
• Invented 1947 at Bell Labs
• William Shockley et al.
Generations of Computer
• Vacuum tube - 1946-1957
• Transistor - 1958-1964
• Small scale integration - 1965 on
—Up to 100 devices on a chip
• Medium scale integration - to 1971
—100-3,000 devices on a chip
• Large scale integration - 1971-1977
—3,000 - 100,000 devices on a chip
• Very large scale integration - 1978 -1991
—100,000 - 100,000,000 devices on a chip
• Ultra large scale integration – 1991 -
—Over 100,000,000 devices on a chip

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Computer Evolution

  • 2. ENIAC - background • Electronic Numerical Integrator And Computer • Eckert and Mauchly • University of Pennsylvania • Trajectory tables for weapons • Started 1943 • Finished 1946 —Too late for war effort • Used until 1955
  • 3. ENIAC - details • Decimal (not binary) • 20 accumulators of 10 digits • Programmed manually by switches • 18,000 vacuum tubes • 30 tons • 15,000 square feet • 140 kW power consumption • 5,000 additions per second
  • 4. von Neumann/Turing • Stored Program concept • Main memory storing programs and data • ALU operating on binary data • Control unit interpreting instructions from memory and executing • Input and output equipment operated by control unit • Princeton Institute for Advanced Studies —IAS • Completed 1952
  • 5. Structure of von Neumann machine
  • 6. IAS - details • 1000 x 40 bit words —Binary number —2 x 20 bit instructions • Set of registers (storage in CPU) —Memory Buffer Register —Memory Address Register —Instruction Register —Instruction Buffer Register —Program Counter —Accumulator —Multiplier Quotient
  • 7. IAS Memory Format The memory of the IAS consists of 1000 storage locations, called words, of 40 binary digits (bits) each. Both data and instructions are stored there. Numbers are represented in binary form, and each instruction is a binary code. Figure 2.2 illustrates these formats. Each number is represented by a sign bit and a 39-bit value. A word may also contain two 20-bit instructions, with each instruction consisting of an 8-bit operation code (opcode) specifying the operation to be performed and a 12-bit address designating one of the words in memory (numbered from 0 to 999).
  • 9. Structure of IAS – detail
  • 10. Registers • Memory buffer register (MBR): Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit. • Memory address register (MAR): Specifies the address in memory of the word to be written from or read into the MBR. • Instruction register (IR): Contains the 8-bit opcode instruction being executed. • Instruction buffer register (IBR): Employed to hold temporarily the right-hand instruction from a word in memory.
  • 11. Registers • Program counter (PC): Contains the address of the next instruction pair to be fetched from memory. • Accumulator (AC) and multiplier quotient (MQ): Employed to hold tem-porarily operands and results of ALU operations. For example, the result of multiplying two 40-bit numbers is an 80-bit number; the most significant 40 bits are stored in the AC and the least significant in the MQ.
  • 12. Transistors • Replaced vacuum tubes • Smaller • Cheaper • Less heat dissipation • Solid State device • Made from Silicon (Sand) • Invented 1947 at Bell Labs • William Shockley et al.
  • 13. Generations of Computer • Vacuum tube - 1946-1957 • Transistor - 1958-1964 • Small scale integration - 1965 on —Up to 100 devices on a chip • Medium scale integration - to 1971 —100-3,000 devices on a chip • Large scale integration - 1971-1977 —3,000 - 100,000 devices on a chip • Very large scale integration - 1978 -1991 —100,000 - 100,000,000 devices on a chip • Ultra large scale integration – 1991 - —Over 100,000,000 devices on a chip