12. History of PLD: Altera
CMOS PLD
$B
3.0
Simple Control Logic Complex System SOPC
Logic Logic
2.5
CPLD
SPLD
2.0
1.5
1.0
MAX+PLUS II
MAX 7000
7032V
AHDL MAX 9000
0.5 ALTR
TTL LIB FLEX 8000 FLEX 10K FLEX 10KA APEX Mercury Stratix
IPO
EP1200 ACCESS EDA IP Library FLEX10KE ARM Transceivers
First
EPB1400 MAX 7000A Nios Cyclone
PLD
83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03
13. Application :
World of Digital and Ana-
log Computation,
control,
communication
Analog:
●
continuous time
temperature, pres-
sure
Why Digital?
Digital:
●
discrete time
ex,
18. What kinds of problem
Digital Only: two Value, Binary, 1/0
●
●
Control
●
Communication
●
Computation
●
●
19. Example: Detector and
control
Event:
True (T) ON
False(F) OFF
Voltage:
High (H) 1
Low(L) 0
Sensor Input:
T, Pressure
If (A OR B OR C) then If (T > 80) then
ALARM ALARM
else else
20. Example: Sequence
Starting up your Car
Motor control
Washing Machine
Off
Menu of Cellar Phone
Off
Off Start
Start
Running
24. How we design
Structural
module, symbol
Schematic: lines, name
Functional
module
Physical
name
Block Cell
Language: HDL
Wire
Level of Abstraction
Behavior, system
30. 2's Complement(1)
10's complement of 95 = 10^2 – 95 =5
●
9's complement of 95 = 99 – 95 =
●
4
● CM(10's) = CM(9's) + 1
● 2's complement 0001 = 2^4 – 0001 =
1111
● 1's complement 0001 = 2^4 – 1 – 0001
An N-bit 1110
= two's-complement numeral system
can represent every integer in the range
−2^(N-1) to +2^(N-1)-1.
4bit: -2^(3)= -8 to +2^3-1 = +7
8bit: -128 to +127
In this way, we only need ADDER
But how it works??
31. 2's Complement(2)
A - B = A + (not B + 1) // ( ) :2's comple-
●
ment
33. What is Logic: Boolean al-
gebra
a logical calculus of truth values,
●
developed by George Boole(1815~1864,
English).
● Algebra of two values. These are usu-
ally taken to be 0 and 1, false
and true, low and high
NOT: ¬A, ~A, !A
If A = 0 then !A = 1 and if A = 1 then !A= 0
AND: A ︿ B, A*B, AB
A product term is 1 only when all terms are a 1
OR: A ﹀ B, A+B
A product term is 1 only when any terms is a 1
35. Bolean Algebra: basic rules
10. A + A*B = A
1. A + 0 = A
= A*(1 + B) where (1+B) according to Rule 2 is equal to 1
2. A + 1 = 1
=A
3. A*0 = 0
11. A*(A+B) = A
4. A*1 = A
5. A + A = A =A*A + A*B Distributive Law
6. A + !A = 1 =A+A*B Rule 7
=A Rule 10
7. A*A = A
12. A + !A*B = A + B
8. A*(!A)= 0
= A*(B+1) + !A*B according to Rule 2 (B+1) = 1
9. !(!A)= A
= A*B +A + !A*B
= B*(A + !A ) + A according to Rule 6 A + ~A = 1
=B+A
13. (A+B)*(A+C) = A+B*C
= A*A+A*C+A*B+B*C applying the Distributive Law
= A*(1+C+B) +B*C according to Rule 2 (1+B+C) = 1
= A+B*C
42. NAND: an fan failure de-
tector
0: Fail
1: Ok ALARM
Positive Logic
Negative Logic
43. NOR: an detecor in Wash-
ing Machine
1: Lid open
Normal
1: < min water level OFF
1: > max weight
44. SOP(sum of product)
POS(product of sum)
SOP
To derive the Sum of Products
form from a truth table, OR
together all of the minterms
which give a value of 1.
POS
To derive the Product of Sums
form from a truth table, AND
together all of the maxterms
which give a value of 0.
Any boolean expression may be expressed in terms of
either minterms or maxterms.
45. Will we start design now ?
With knowledge up to now, we can start to design
●
『 combinational 』 logic circuit such as Decoder,
Adder,,,, etc, whenever we have a 『 spec 』 or
『 truth table 』 derived from the problem re-
quirement.
Traditionally, Karnaugh Map & Boolean Expres-
●
sion Simplification technics will be introduced for
design optimization.
But.....we will skip this portion since we are using
●
HDL and FPGA/CPLD other than TTL or ASIC.
Let's see “why” later.
●
65. FPGA CPLD Comparison
FGPA CPLD
Fine-Grain, Coarse-Grain,
Arch PAL
Gate-array
Like like
LAB
LE, LUT
Layout
LAB around Global Connect
Grid Array
Interconn
LAB Local and Global
LAB Local and row/col
Conf (E)EPROM-based
SRAM-based
instant-on
require programming
Scale Medium to small
Very Large design
timing Fast, predictable
dependent
memory No memory
large memory
Power Less power
High power
misc NA
DSP, TRCVR
72. Introduction
What is Verilog HDL,
take a tour of 1 st tutorial example
logic simulation
73. What is HDL
A Hardware Description Language (HDL) is a high-level
programming language that offers special constructs
with which you can model microelectronic circuits.
These special language constructs permit you to:
Describe the operation of a circuit at various levels of
abstraction, behavior, function, structure, timing of a
circuit.
Language for the concurrency of hardware, not a
software language
timing
Synthesis: mapping to physical
74. Why HDL
Top-down design methodology using synthes-
●
is
Implementation/technology highly independ-
●
ent
Quickly/easily explore design alternatives
●
Architectural problems
●
Re-use
●
Design productivity
●
Take advantage of mature software design
●
practices
75. Verilog History
1980’s Gateway Design Automation developed Veri-
●
log
1990 Cadence acquired Gateway
●
1991 Cadence released Verilog to the public do-
●
main.
1995 IEEE ratified the Verilog LRM
●
We will use
(IEEE Std. 1364-1995)
2001 IEEE updated the Verilog LRM
●
System Verilog
●
76. Verilog Usage
System architects:
●
system level Simulations
ASIC and FPGA designers:
●
RTL code for synthesis
Verification engineers:
●
tests for all level of simulation
Model developers:
●
component behavior, ex
DRAM
SystemVerilog
90. Behavior Modeling
Describes a system by the flow of data between its
functional blocks, or algorithm
Defines signal values when they change
a=b*c
wait a;
91. RTL Modeling
Describes a system by the flow of data and control
signals between and within its functional blocks
Defines signal values with respect to a clock
92. Structure Modeling
Describes a system by connecting predefined components
Uses technology-specific, low-level components when
mapping from an RTL description to a gate-level netlist,
such as during synthesis
94. Why we skip Logic Optim-
ization
HDL
●
FPGA/CPLD vs TTL, ASIC Cell
●
●
●
Let Machine do what it excels
●
You give direction.
●
You have to know what you really want.
Speed, Area, Power
●
Design Scale Dependent.
●
95. Summary
Brief History
●
Review of Number system and Boolean Al-
●
gebra
● Basic concept of CPLD/FPGA
● HDL Tour:
● modules; ports, instances
● Test Bench
● Stimulus
● Response