The document discusses flash memory technology. It begins with an introduction to flash memory and its advantages over other memory technologies. It then describes two main flash memory technologies: floating gate technology and charge trap memory technology. The document concludes by discussing scaling limitations of flash memory and potential next generation technologies.
2. Outline
Part 1 : Introduction to Flash Memory
Part 2 : Flash memory technology
Floating gate technology
Charge trap memory technology
Part 3 : Scaling limitation and Next generation Flash
| Memory
Technology |
| Flash Device
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3. Part 1:
Introduction to Flash
Memory
[Note]
• DRAM : Dynamic Random Access Memory
• SRAM : Static Random Access Memory
• ROM : Read Only Memory
• EPROM : (UV) Erasable Programmable ROM
• EEPROM : Electrically Erasable Programmable ROM
• FLASH : Flash Erase EEPROM
• FeRAM : Ferroelectric Memory
4. Inside iPhone4
Antenna & Speaker
Battery Front Panel (LCD)
Main Frame (Antenna)
Main Board (Front)
Main Board (Back)
Camera module
Microphone
| Memory
NAND
Technology | Flash
| Flash Device
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5. NAND & NOR application
NAND NOR
Mass Storage Code Memory
Mobile Phone (Storage) BIOS/Networking
Tablet PC Telecommunications
Solid-State Disk Mobile Phone (Code)
Memory Cards POS / PDA / PCA
•
| MemoryLow Cost and High Density • Fast Random Access
• Page Mode Program • Fast Read Speed
Technology |
| Flash Device
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6. Semiconductor memories
MOS Memory
Volatile Non-volatile
Random Access Read Only Memory
Memory ( RAM ) ( ROM )
Dynamic Static Programmable
Mask ROM
RAM (DRAM) RAM (SRAM) ROM (PROM)
1970 intel 1970 intel 1970 intel
EPROM EEPROM
1971 intel
Byte-alterable Flash
| Memory
Technology | 1979 intel 1984 Toshiba
| Flash Device
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7. Bi-stable status in memories
Memory DRAM SRAM Flash MRAM FeRAM
V/2
Data “1” 0
“High”
V
0
Data “0” V
“Low”
V/2
Dielectric
Dielectric Vcc or Vss 공급
Vcc or Vss 공급 Transistor 를
Transistor 를
Capacitor
Capacitor Transistor
Transistor Turn-On
Turn-On Resistor 의
Resistor 의 Capacitor 의
Capacitor 의
Bi-Stable
Bi-Stable 양단의
양단의 Gate 전압이
Gate 전압이 시키기 위한
시키기 위한 Resistance 가
Resistance 가 Capacitance 가
Capacitance 가
Status
Status 상대 전압이
상대 전압이 High (On)
High (On) 문턱전압 (VT) 이
문턱전압 (VT) 이 작은 상태
작은 상태 큰 상태
큰 상태
Description
Description Positive
Positive 또는
또는 높은 상태
높은 상태 또는
또는 또는
또는
또는
또는 Low (Off)
Low (Off) 또는
또는 큰 상태
큰 상태 작은 상태
작은 상태
| Memory Negative
Negative [latch type]
[latch type] 낮은 상태
낮은 상태
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| Flash Device
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8. Memory performance
Flash EEPROM FeRAM Slow SRAM DRAM
Nonvolatile Yes Yes Yes No No
Power
Medium Medium Medium Medium Large
Consumption
Write Speed >10us <10ms <150ns <120ns <60ns
Write Voltage 10~20V 8~12V 2~5V 2~5V 2~5V
Write Endurance 105 cycles 105 cycles 1012 cycles 1015 cycles 1015 cycles
| Memory
Technology |
| Flash Device
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9. Drain Contact
Bit Line
DSL
DSL WL31 WL30
| Memory
WELL -C
C-WELL
WL2
Technology |
Technology |
| Flash Device
SSL
WL1 WL0
SSL
Source Line
Bit line
Contact
DSL
(Drain Sel. Line)
WL
Inside NAND Flash
(Control Gate)
Floating Gate
SSL
(Source Sel. Line)
CSL
(Cell Source Line)
Block 0 1
Memory Array
Word
Line
Bit Line
Row Decoder
Row Decoder
Page 9
Block 1 2N
1 2M
BLe
BLo
BLs S/A
Block N- 1
Column Decoder
Column Decoder
14. Coupling Ratio of Flash cell
ONO Coupling Ratio means Gate Controllability
From Gauss' Law
CONO
Q = 0 = C ONO (V FG − VCG ) + CTox (VFG − VB )
+ C D (VFG − V D ) + C S (V FG − VS )
CTox
VFG = α ONOVCG + α ToxVB + α DVDS + α SVS
where CT = CONO + CTox + C D + CS
| Memory α J = C J / CT
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15. F-N tunneling
J = AE² × Exp(-B/E)
야 ! 거기 둘
Oxide 모서리
잡아 당겨
Potential diagram of Potential diagram of
|
Memory
Si/SiO2 interface Si/SiO2 interface
with No Electric Field with Strong Electric Field
Technology |
| Flash Device
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25. Charge Trap Devices
| Memory
Technology | White, "Characterization and modeling of scaled MANOS NVSM devices", IMEC lecture
M.
| Flash Device
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26. TANOS Stack
Metal Gate High Work function Metal Gate
(TaN) To prevent electron back-tunneling (barrier height)
High-K High-K dielectric material
(Al2O3) To prevent electron back-tunneling (electric field)
High CBO* necessary for retention
Charge Trapping Material
Nitride (Stoichiometric: deep trap, Si-rich: shallow trap)
(Si3N4)
Oxide Tunnel Oxide
(SiO2) Thin to enable FN tunneling (PGM & Erase)
Thick to prevent direct tunneling (Retention)
Si-sub
(P-type Si)
| Memory
Technology | * CBO (Conduction Band Offset)
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27. TANOS Energy Band Diagram
Vacuum Level (Evac)
0.9eV
Oxide electron affinity
2.8eV 3.2eV
Al2O3 CBO Oxide CBO 4.1eV
5.2eV 2.0eV
Metal Gate Work function 1.1~1.8eV Si electron affinity
Nitride CBO
Nitride active trap energy
-- - - - - -
-
EC
EF EF
EB
2.7eV 1.1eV
4.8eV Silicon band-gap
Nitride VBO
Al2O3 VBO
4.7eV
Oxide VBO
CBO: Conduction band offset (from Si CB edge)
| Memory 8.7eV 5.8eV 9.0eV VBO: Valence band offset (from Si VB edge)
Technology | Al2O3 band-gap Nitride band-gap Oxide band-gap
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28. Why TANOS?
1. Erase Saturation (back-tunneling)
0.5
I2 Tunnel 0
Gate
Oxide
-0.5
work
Vt shift (V)
-1 function
Blocking
Oxide -1.5
-2
-2.5
Erase @-18V from fresh
Trapping I1 Substrate -3
Layer 10-6 10-5 10-4 10-3 10-2 10-1 100
Time (s)
2. In order to suppress electron back-tunneling
- Barrier height Metal Gate, P+ poly-Si gate
| Memory
- Electric field reduction High-K blocking oxide
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30. TANOS Key Issue: Erase/Retention trade-off
Deep trap Nitride Shallow trap Nitride
(Slow Erase & Good Retention) (Fast Erase & Poor Retention)
Block Oxide Less Charge Loss
Gate
Charge Trap Nitride
e e e Tunnel Oxide
Back- Tunneling
e
Trap e e
e
Faster Erase
h h h
H ole Tunneling
G. van den Bosch et al, "Nitride engineering for improved
| Memory erase performance and retention of TANOS NAND Flash
memory", NVSMW 2008
Technology |
| Flash Device
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33. In order to attain more bits in a wafer...
Increasing wafer size Shrinking cell size
4x
㎚
3x
㎚
2x
㎚
2.25 times larger every 10years 1x
㎚
MLC (Multi-Level Cell) 3D Flash Bit Line (BL)
Upper Selection Gate
(USG)
Control Gate (CG)
Lower Selection Gate
(LSG)
Source Line (SL)
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35. Scaling Limitation of Floating Gate
Floating Gate Limitation ~ 1xnm
▶ No further space for IPD to wrap-around P1
▶ Low cell current since active size becomes smaller
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37. Scaling Limitation of Floating Gate
Floating Gate Limitation ~ 1xnm
▶ Interference and RTN Increase Cell distribution wider
▶ Fewer electrons are stored in FG Reliability concerns
Interference
Random Telegraph Noise
F1x
F2x
F3x
F4y
F5x
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38. Next candidates to Floating Gate
Vertical NAND is the best in cost-effectiveness
Simple Stacking Cross-point Memory Vertical NAND
| Memory beneficial for bit-cost reduction
Less Cost effective
(Critical Mask step keeps
Technology | Mask step increases as stacking)
(Critical
constant as stacking)
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39. Vertical NAND Structures
No decisive winner as of today
BiCS P-BiCS TCAT DC-SF
Cleared ONO / WL Beneficial for Device
Simple Process Best Performance
delay Operation
Complicated
ONO / WL delay Complicated Process Larger Cell Size
Process
BiCS : Bit-Cost Scalable
| Memory P-BiCS : Pipe-shaped Bit-Cost Scalable
TCAT : Tera-bit Cell Array Transistor
Technology |
DC-SF : Dual Control-gate with Surrounding Floating gate
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40. Vertical NAND Flash using FG
Best 3D cell performance ever using FG instead
of SONOS
Programmed
cell
| Memory
Technology |
| Flash Device
Technology | Fig. 9 The program characteristics of the DC-SF Fig. 10 The erase characteristics of the DC-SF
Page 40
41. Concept of Vertical String 3D NAND
3D is simple rotation of 2D (Schematically the same)
2D NAND Flash
BL
=
CHANNEL
3D Vertical String NAND Flash Rotation
=
BL
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42. 3D Device Key Features
2D cell 3D cell (Vertical String)
CG
ONO
FG
channel S CG D
S D
channel
Well
Single crystal Si channel Poly-Si channel
Floating Gate (or TANOS) SONOS
1-side gate All-around gate
Channel-first process Channel-last process
| Memory
Technology | litho (ISO/Gate)
2 step 1 step litho (hole)
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43. Gate-All-Around effect (GAA)
1 0.0
Band Diagram
Smaller hole size (or more curvature) 9.0
p lan e
h ole 1 0 00 nm
h ole 2 5 0n m
Higher Field at Tunnel Oxide (Inner) 8.0 h ole 1 2 0n m
h ole 9 0 nm
h ole 7 0 nm
Lower Field at Blocking Oxide (Outer) 7.0
Tunnel h ole 6 0 nm
Blocking
6.0 Oxide Oxide
5.0
4.0
CT Nitride
D ONO 3.0
2.0
Channel
Electric Field
1 0.0
p lan e
h o le 1 0 00 nm
Control h o le 2 5 0n m
8.0
h o le 1 2 0n m
Gate h o le 9 0 nm
Blocking
h o le 7 0 nm
h o le 6 0 nm
Oxide
6.0
Tunnel
| Memory S 4.0
Oxide
CT Nitride
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| Flash Device 2.0
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45. P-BiCS Process Sequence
(2) Channel hole etching
(1) Process Sequence : Cell size highly depends on the slope
: full dip-out of sacrificial layer
& filling ONO and channel poly
(3) Slimming for WL pick-up
: Thick PR and LER control
| Memory
Technology | et al, "Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation
R. Katsumata
| Flash Ultra High Density Storage Devices", SOVT 2009
for Device
Technology | Page 45
46. TCAT Process Sequence
(1) Gate Replacement
silicon silicon silicon silicon
Slit Patterning Nitride Pull-back ONO/MG Dep Gate Separation
(2) Slimming
| Memory
Technology |
| Flash Device J. Jang, "Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High
Density NAND Flash Memory", SOVT 2009
Technology | Page 46
47. What is a next paradigm shift?
| Memory T. Higashiki, 5th Annual SEMATECH/ISMI Symposium Japan
Technology |
| Flash Device
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48. Summary
Part 1:
Among the various proposed memory concepts, only a few survived.
Flash is nonvolatile memory and the process is compatible to well
established conventional Si-process.
Part 2:
Flash cell status ("0" or "1") is defined by the net charge captured inside
trapping layer (poly-Si or nitride).
NAND flash programs and erases using FN-tunneling.
Part 3:
NAND scaling has been achieved down to 2xnm technology. However, we are
| Memory limitation for further scaling at 1xnm.
facing
3D flash |is the most promising candidate to extend NAND bit growth.
Technology
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49. Thank you for attention and ...
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50. Homework#1
아래와 같이 주어진 Floating Gate Cell 에서 (a) ONO coupling ratio 와
(b) Floating Gate Potential (Vfg) 를 계산하라 .
20V
60pF
10pF 20pF
CTox 10pF
0V 0V 0V
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51. Homework#2
TANOS stack 은 왼쪽 그림과 같이 Serial Capacitor 로 도식화할 수 있다 .
Nitride 내부에는 전하 Q 가 균일하게 분포하고 있다고 가정하고 , Gauss' Law 를
이용하여 Block Oxide, Nitride, Tunnel Oxide 에 걸리는 Electric Field 를 유도하
라 . (ε1, ε2, ε3 은 각 Layer 의 유전율이며 , d1, d2, d3 는 각 Layer 의 두께이다 .)
Vg
Block Oxide E3 ε3, d3
Nitride E2 + + + ε2, d2
Q + + x
Tunnel Oxide E1 ε1, d1
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