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Eye Know How


  Signal Integrity Consulting

   Services and KnowHow
Company Facts

 Founder:
  Dipl. Ing. (FH) Hermann Ruckerbauer
 Founded:
  March 2009
 Location:
  Office in Moos (Bavaria), Germany
  Network partners in:
     Munich (Design, Layout, CAD)
     Straubing (EMV)
     Deggendorf (Lab)
     China (Shandong und Shaanxi): Oulong Consulting



                                         EKH - EyeKnowHow   11/11/10   2
Hermann Ruckerbauer
Background

Study of Micro System Technology at University of Applied
Sciences in Regensburg
   Dipl. Ing. (FH) Micro System Technology
15 Years experience in Memory Development and High
Speed Signaling
   Siemens: Bench and Production test
   Infineon / Qimonda:
      High Speed Signaling
      Application test
      Interface standard definition
 Holder of many patents
 EEE Publication:
   Cascading Techniques for a High-Speed Memory Interface

                                             EKH - EyeKnowHow   11/11/10   3
EKH - Services


 Consulting for High Speed Signaling
 Consulting for memory implementation
 High speed simulation and measurement
 Power delivery simulation
 Model generation
 Logic Analyzer measurements
 Failure analysis (esp. on memory interfaces)
 PCB Design and Layout

                              EKH - EyeKnowHow   11/11/10   4
EKH - Cooperation partners

 DKH – DesignKnowHow: Dr. Abdallah Bacha
   PCB Design and Layout
   RF Topics
 ESFODA: Michael Vogl (www.esfoda.de)
   CAD customization and automation
 SinePulse: Md Sayfullah (www.sinepulse.com)
   IT services (India)
   Hardware development (e. g. FPGA)
 FH Deggendorf (www.fh-deggendorf.de)
   Measurement Lab
   PCB X-section


                                       EKH - EyeKnowHow   11/11/10   5
EKH - Cooperation partners

 EMV – Testhaus (www.emv-testhaus.de)
   EMI / EMC compliance test
 PCB Manufacturing
   Enzmann (www.enzmann.de)
   Ilfa (www.ilfa.de)
 Assembly
   Mair Electronics (www.mair-elektronik.de)
 China Business (Peter Poechmueller)
   Oulong Consulting (www.oulongconsulting.com)




                                         EKH - EyeKnowHow   11/11/10   6
EKH - Customer examples

 Happy Customers
  TQ – Systems
  Kontron
  Congatec
  Numonyx
  3D-Plus




                          EKH - EyeKnowHow   11/11/10   7
Software Tools


 Agilent ADS
   Time and Frequency domain simulation
   Analog and Digital Simulation
   2.5D and 3D field solver
   Data evaluation (measurement and simulation)
 Power Delivery
   Sigrity Power SI
 Design and Layout
   Cadence Allegro
   Mentor Hyperlinx/Pads

                                  EKH - EyeKnowHow   11/11/10   8
Services from
        EyeKnowHow

   1) Memory System Know How

   2) DRAM device Know How
   3) Analog Simulation
   4) Power Delivery Simulation
   5) 2.5D Modeling: PCB Layout

   6) 3D Modeling: Package and Connectors
   7) Measurement Based Modeling
   8) Signal Integrity Correlation Measurement
   9) Logic Analyzer Memory Command Trace Evaluation
   10) Failure Analysis
   11) Design and Layout Services
   12) EMC / EMI Measurement and Consulting



                                                  EKH - EyeKnowHow   11/11/10   9
1) Memory System
             Know How
Worked in the development of DDR1 / DDR2 / DDR3 / DDR4
   Data and Command/Address bus architecture development
   Memory Device Specification
Consumer, Mobile, Desktop and Server system understanding
   Differences in requirements and boundary conditions
System requirements
   Cache line size limitations
   Turnaround times, Bandwidth and latency
   Power limitations
Clocking
   SSC, Random and Deterministic Jitter
Controller functionality
   Controller PCI register features (e. g. Delay shift, Driver strength,
   digital timings)
                                                EKH - EyeKnowHow   11/11/10   10
1) Memory System
             Know How
 DDR1 Motherboard example
                       DRAM
                                                 DIMM


                                             Bus End
                                             Termination
Controller


                                                 Register/PLL
Memory
BUS                                               2 Slot/
                                                  1 Connector

                                                 System
                                                 CLK buffer


                              EKH - EyeKnowHow    11/11/10   11
1) Memory System
             Know How
                          DDR1 MBT
DDR2 Testboard Example




  DIMMs




                          DDR2 ODT
 Controller
 Emulator


  Clock
  Buffer




                         EKH - EyeKnowHow   11/11/10   12
1) Memory System
             Know How
DDR3 System example
                                                      T
               D
               D   D
                   D   D
                       D   D
                           D         D
                                     D   D
                                         D    D
                                              D   D
                                                  D




                                                                    D
                                                                    D
                                                                    D D D
                                                                    D D D
                                                                    D D D D
                                                                    D D D D
                               CPU




                                                                          T
                                             EKH - EyeKnowHow   11/11/10      13
1) Memory System
             Know How

Close interaction between system Architecture and DRAM features
   IO specification (e. g. Input capacitance, driver and termination linearity)
   DLL functionality
   Memory Device Specification
DRAM Core / architecture / process limitation
   Source for Latency
   ODOC package and impact on Architecture
   DRAM process and impact on speed and parasitics
DRAM packaging
   Planar and stacked DRAM parasitics
                                                         Single Die DRAM package
   Wirebond and FCIP packaging




                                                     EKH - EyeKnowHow   11/11/10   14
3) Analog Simulation

 Time Domain simulation
    Spice models (Lumped elements and BSIM Transistor based)
    S-Parameter
    IBIS
 Frequency Domain simulation
    S-Parameter model generation
    Model comparison
 Statistical Data evaluation
    Adding Random and deterministic Jitter
    Channel characterization by Step Response
 Data Eye evaluation
    Setup/Hold                                   Data eye generated out of
    Timing budget calculation                    Channel Step response


                                                EKH - EyeKnowHow   11/11/10   15
3) Analog Simulation

   Schematic example: 10 coupled lines on a Desktop PC Motherboard

                                       DIMM socket



                                                  DIMM



Controller Package

 Controller
 Driver                            T-Branch on
                                   Motherboard

                                 10 Coupled Via

                           Motherboard Lead In


                                                  EKH - EyeKnowHow   11/11/10   16
3) Analog Simulation

 Simulation schematic example: 10 Coupled lines


                                             DRAM load
                                   Package




        Stub
        Resistor




                   DIMM Lead In



                                                  EKH - EyeKnowHow   11/11/10   17
4) Power Delivery Simulation

 PowerSI Simulation: PDN impedance over frequency




                                 EKH - EyeKnowHow   11/11/10   18
5) 2.5D Modeling
          PCB Layout
                                                                    Large Logic
Cadence and Mentor to ADS Layout transfer                                  package
Simulation in Momentum
  Result: S-Parameter Model
  Co-Simulation with ADS time/frequency domain simulation
  Signals and Power Supply Integrity
  Layout accurate simulation
     X-talk (intera- and inter layer)
     Reflections
     Losses


             3 coupled lines of a CA bus on a DIMM




                                                 EKH - EyeKnowHow    11/11/10   19
6) 3D Modeling:
    Package / Connector
Package and Connector Modeling
ADS 3D Fieldsolver EMDS
  Substrate routing
  Bondwires
  FBGA Package balls
  Signal traces
  Power planes




                          16 Coupled Bondwires: Signal and Power


                                        EKH - EyeKnowHow   11/11/10   20
7) Measurement based
Modeling
Characterization of existing boards
   Measurement with VNA
   TDR/TDT Characterization up to 20 GHz BW
                                              TDR of Memory Riser Card




                                         EKH - EyeKnowHow   11/11/10   21
7) Measurement based
 Modeling
   Definition, Design and Layout of Characterization boards
       Lumped model fitting                            Insertion Loss
                                                                        Blue: Model
                                                                        Red: Measurement
Testboard for S-Parameter Measurements




                                                       FEXT



           ADS model fitted to measurement results

                                                       NEXT




                                                     EKH - EyeKnowHow   11/11/10   22
7) Measurement based
Modeling
   Physical X-sections
        Measure what the manufacturer delivers
        Create model based on real Hardware




Dielectric
 (FR4)




                   Traces                  Cross section of PCB with blind and micro vias
             (transmission line)   Vias

                                               EKH - EyeKnowHow          11/11/10       23
8) Correlation
 Measurements
     Dataeye @ 5.3Gb Measured vs. Simulated / Ball vs. Pad
2x65 Ohm (initial Setting)
    Measurement @ ball            Simulated @ ball              Simulated @ pad




2x45 Ohm (matched to the differential PCB Channel impedance)
      Measurement @ ball           Simulated @ ball             Simulated @ pad




                                                      EKH - EyeKnowHow   11/11/10   24
9) Logic Analyzer
Command Trace evaluation
 Digital timing Trace evaluation
    Spec compliant timings / Finding timing violations
    Digital Timing Settings / MRS setting




                                                    EKH - EyeKnowHow   11/11/10   25
9) Logic Analyzer
        Command Trace evaluation
          Statistical Command sequence evaluation
                                                                                Timings:
                    Statistical Access evaluation                               AL=3     BL=4 RL=4 TCCD=2 TCK=3750 TFAW=14 TPDN=0 TRAS=12 TRC=16 TRCD=4 TRFC=54
                                                                                TRP=4 TRRD=3 TRTP=2 TRTW=2 TWR=4 TWTR=2 VDD=1800 WIDTH=64 WL=3 XT=1
                    Performance/Power Optimization                              Command Bank_00 Bank_01 Bank_02 Bank_03 Bank_04 Bank_05 Bank_06 Bank_07 Banks_All TOTAL

                                                                                RD         1289     402    1180    3884       0       0       0        7        0    6762
                                                                                WR         1107     402       0       7       0       0       0        4        0    1520
                                                                                ACT          45      31      31      30       0       0       0        1        0     138
Observed timings                                                                RD_AP
                                                                                WR_AP
                                                                                              0
                                                                                              0
                                                                                                      0
                                                                                                      0
                                                                                                              0
                                                                                                              0
                                                                                                                      0
                                                                                                                      0
                                                                                                                              0
                                                                                                                              0
                                                                                                                                      0
                                                                                                                                      0
                                                                                                                                              0
                                                                                                                                              0
                                                                                                                                                       0
                                                                                                                                                       0
                                                                                                                                                                0
                                                                                                                                                                0
                                                                                                                                                                        0
                                                                                                                                                                        0
Name          Min           Max          Name         Min          Max
                                                                                PRE          16       2       2       1       0       0       0        1        0      22
tRAS_bank_0            12         2025   tRC_bank_0           16         2150
                                                                                PRE_A         0       0       0       0       0       0       0        0       30      30
tRAS_bank_1           259         2025   tRC_bank_1          761         2158   des           0       0       0       0       0       0       0        0    55843   55843
tRAS_bank_2           450         2020   tRC_bank_2          718         2182   nop           0       0       0       0       0       0       0        0        0       0
tRAS_bank_3          1874         2030   tRC_bank_3         2032         2122   MRS           0       0       0       0       0       0       0        0        0       0
tRAS_bank_4   -             -            tRC_bank_4   -            -            REF           0       0       0       0       0       0       0        0       31      31
tRAS_bank_5   -             -            tRC_bank_5   -            -            SRE           0       0       0       0       0       0       0        0        0       0
                                                                                SRX           0       0       0       0       0       0       0        0        0       0
tRAS_bank_6   -             -            tRC_bank_6   -            -
                                                                                PDE           0       0       0       0       0       0       0        0        0       0
tRAS_bank_7          573           573   tRC_bank_7   -            -
                                                                                PDX           0       0       0       0       0       0       0        0        0       0
tRAS_rank             12          2030   tRC_rank            16          2182   PRE_I         0       0       0       0       0       0       0        0        0       0
                                                                                PDCONT        0       0       0       0       0       0       0        0        0       0
tRCD_bank_0            1            5    tRP_bank_0*          4           124   BST           0       0       0       0       0       0       0        0        0       0
tRCD_bank_1            1           11    tRP_bank_1*          5          1763   DPD           0       0       0       0       0       0       0        0        0       0
tRCD_bank_2            1            6    tRP_bank_2*          5           268
tRCD_bank_3            1           10    tRP_bank_3*          5           142
tRCD_bank_4   -             -            tRP_bank_4* -             -
tRCD_bank_5   -             -            tRP_bank_5* -             -
tRCD_bank_6   -             -            tRP_bank_6* -             -
tRCD_bank_7            5            5    tRP_bank_7*        1089         1089
tRCD_rank              1           11    tRP_rank              4         1763

tRFC                   55           55
tREFI                2072         2091
tRRD                    3         2070
tCCD                    2           77
                                                                                                          EKH - EyeKnowHow                  11/11/10          26
10) Failure analysis

 Memory test failure Analyis
     Evaluate log files from Software Memory tests
     Narrow down failure reason
         DQ vs. CA related fail
         Single DQ vs. DQS fail
         Read vs. Write fail
         Device vs. Signal integrity related fail
 Vref Margin test implementation
      Adjust VREF until fail and evaluate fail behavior
 Timing Margin test implementation
     Change Controller delays (DQS and CLK) until fail and evaluate fail behavior

                                                                                           12742808                                                12742822
                                                                                                      FAILURE: possible bad address line at offset
                                     FAILURE: possible bad address line at offset 0x00000000 =
                                                                                                      0x018A5141 = address 0x062D4504
                                     address 0x099C0038
                                                                                                      Expected value F9D2BAFB, Read value 8002BAFB
                                     Expected value F663FFC7, Read value 099C0038
                                                                                                      Re-Read:
                                     Re-Read:
                                                                                                      Expected value F9D2BAFB, Read value 8002BAFB
                                     Expected value F663FFC7, Read value 099C0038
                                                                                                      Expected value F9D2BAFB, Read value 8002BAFB
                                     Expected value F663FFC7, Read value 099C0038
                                                                                                      Expected value F9D2BAFB, Read value 8002BAFB
                                     Expected value F663FFC7, Read value 099C0038
                                                                                                      Expected value F9D2BAFB, Read value 8002BAFB
                                     Expected value F663FFC7, Read value 099C0038
                                                                                                      Skipping to next test...



                                                                                        EKH - EyeKnowHow                       11/11/10             27
11) Design / Layout
4GB DDR2 Registered
 DDR2 RDIMM 4GB




                      EKH - EyeKnowHow   11/11/10   28
11) Design / Layout
  DDR3 Unbuffered VLP

     DDR3 UBU VLP 1Rx8/2Rx8 ECC/non ECC: DIMM view
              Top view         ECC                                     Termination




                               CA BUS      RANK 0

Termination
                 Bottom view         ECC




                           CA BUS       RANK 1

                                                    EKH - EyeKnowHow   11/11/10      29
11) Design / Layout
DDR3 Unbuffered VLP : Timing budget

 Setup/Hold: 558ps/336ps   Setup/Hold: 532ps/368ps   Setup/Hold: 511ps/336ps


                                                                                      WEAK CASE
                                                                                     39 ohm Termination

         D0                         D1                        D2
Setup/Hold: 481ps /334ps   Setup/Hold: 423ps/406ps   Setup/Hold: 341ps/478ps




        D3                      D8-ECC                         D4

Setup/Hold: 298ps/513ps    Setup/Hold: 273ps/512ps   Setup/Hold: 226ps/524ps




            D5                        D6                          D7

                                                                           EKH - EyeKnowHow   11/11/10    30
12) EMC / EMI Investigations
   Spec. Limits & Measurements


system specification
limits (e.g. for PC, Server)




 measurement results
    DDR2 P-/R-DIMM
    on SUN Fire T2000
        "Ontario"




                                  EKH - EyeKnowHow   11/11/10   31

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EKH Company Presentation 2010 11

  • 1. Eye Know How Signal Integrity Consulting Services and KnowHow
  • 2. Company Facts Founder: Dipl. Ing. (FH) Hermann Ruckerbauer Founded: March 2009 Location: Office in Moos (Bavaria), Germany Network partners in: Munich (Design, Layout, CAD) Straubing (EMV) Deggendorf (Lab) China (Shandong und Shaanxi): Oulong Consulting EKH - EyeKnowHow 11/11/10 2
  • 3. Hermann Ruckerbauer Background Study of Micro System Technology at University of Applied Sciences in Regensburg Dipl. Ing. (FH) Micro System Technology 15 Years experience in Memory Development and High Speed Signaling Siemens: Bench and Production test Infineon / Qimonda: High Speed Signaling Application test Interface standard definition Holder of many patents EEE Publication: Cascading Techniques for a High-Speed Memory Interface EKH - EyeKnowHow 11/11/10 3
  • 4. EKH - Services Consulting for High Speed Signaling Consulting for memory implementation High speed simulation and measurement Power delivery simulation Model generation Logic Analyzer measurements Failure analysis (esp. on memory interfaces) PCB Design and Layout EKH - EyeKnowHow 11/11/10 4
  • 5. EKH - Cooperation partners DKH – DesignKnowHow: Dr. Abdallah Bacha PCB Design and Layout RF Topics ESFODA: Michael Vogl (www.esfoda.de) CAD customization and automation SinePulse: Md Sayfullah (www.sinepulse.com) IT services (India) Hardware development (e. g. FPGA) FH Deggendorf (www.fh-deggendorf.de) Measurement Lab PCB X-section EKH - EyeKnowHow 11/11/10 5
  • 6. EKH - Cooperation partners EMV – Testhaus (www.emv-testhaus.de) EMI / EMC compliance test PCB Manufacturing Enzmann (www.enzmann.de) Ilfa (www.ilfa.de) Assembly Mair Electronics (www.mair-elektronik.de) China Business (Peter Poechmueller) Oulong Consulting (www.oulongconsulting.com) EKH - EyeKnowHow 11/11/10 6
  • 7. EKH - Customer examples Happy Customers TQ – Systems Kontron Congatec Numonyx 3D-Plus EKH - EyeKnowHow 11/11/10 7
  • 8. Software Tools Agilent ADS Time and Frequency domain simulation Analog and Digital Simulation 2.5D and 3D field solver Data evaluation (measurement and simulation) Power Delivery Sigrity Power SI Design and Layout Cadence Allegro Mentor Hyperlinx/Pads EKH - EyeKnowHow 11/11/10 8
  • 9. Services from EyeKnowHow 1) Memory System Know How 2) DRAM device Know How 3) Analog Simulation 4) Power Delivery Simulation 5) 2.5D Modeling: PCB Layout 6) 3D Modeling: Package and Connectors 7) Measurement Based Modeling 8) Signal Integrity Correlation Measurement 9) Logic Analyzer Memory Command Trace Evaluation 10) Failure Analysis 11) Design and Layout Services 12) EMC / EMI Measurement and Consulting EKH - EyeKnowHow 11/11/10 9
  • 10. 1) Memory System Know How Worked in the development of DDR1 / DDR2 / DDR3 / DDR4 Data and Command/Address bus architecture development Memory Device Specification Consumer, Mobile, Desktop and Server system understanding Differences in requirements and boundary conditions System requirements Cache line size limitations Turnaround times, Bandwidth and latency Power limitations Clocking SSC, Random and Deterministic Jitter Controller functionality Controller PCI register features (e. g. Delay shift, Driver strength, digital timings) EKH - EyeKnowHow 11/11/10 10
  • 11. 1) Memory System Know How DDR1 Motherboard example DRAM DIMM Bus End Termination Controller Register/PLL Memory BUS 2 Slot/ 1 Connector System CLK buffer EKH - EyeKnowHow 11/11/10 11
  • 12. 1) Memory System Know How DDR1 MBT DDR2 Testboard Example DIMMs DDR2 ODT Controller Emulator Clock Buffer EKH - EyeKnowHow 11/11/10 12
  • 13. 1) Memory System Know How DDR3 System example T D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D CPU T EKH - EyeKnowHow 11/11/10 13
  • 14. 1) Memory System Know How Close interaction between system Architecture and DRAM features IO specification (e. g. Input capacitance, driver and termination linearity) DLL functionality Memory Device Specification DRAM Core / architecture / process limitation Source for Latency ODOC package and impact on Architecture DRAM process and impact on speed and parasitics DRAM packaging Planar and stacked DRAM parasitics Single Die DRAM package Wirebond and FCIP packaging EKH - EyeKnowHow 11/11/10 14
  • 15. 3) Analog Simulation Time Domain simulation Spice models (Lumped elements and BSIM Transistor based) S-Parameter IBIS Frequency Domain simulation S-Parameter model generation Model comparison Statistical Data evaluation Adding Random and deterministic Jitter Channel characterization by Step Response Data Eye evaluation Setup/Hold Data eye generated out of Timing budget calculation Channel Step response EKH - EyeKnowHow 11/11/10 15
  • 16. 3) Analog Simulation Schematic example: 10 coupled lines on a Desktop PC Motherboard DIMM socket DIMM Controller Package Controller Driver T-Branch on Motherboard 10 Coupled Via Motherboard Lead In EKH - EyeKnowHow 11/11/10 16
  • 17. 3) Analog Simulation Simulation schematic example: 10 Coupled lines DRAM load Package Stub Resistor DIMM Lead In EKH - EyeKnowHow 11/11/10 17
  • 18. 4) Power Delivery Simulation PowerSI Simulation: PDN impedance over frequency EKH - EyeKnowHow 11/11/10 18
  • 19. 5) 2.5D Modeling PCB Layout Large Logic Cadence and Mentor to ADS Layout transfer package Simulation in Momentum Result: S-Parameter Model Co-Simulation with ADS time/frequency domain simulation Signals and Power Supply Integrity Layout accurate simulation X-talk (intera- and inter layer) Reflections Losses 3 coupled lines of a CA bus on a DIMM EKH - EyeKnowHow 11/11/10 19
  • 20. 6) 3D Modeling: Package / Connector Package and Connector Modeling ADS 3D Fieldsolver EMDS Substrate routing Bondwires FBGA Package balls Signal traces Power planes 16 Coupled Bondwires: Signal and Power EKH - EyeKnowHow 11/11/10 20
  • 21. 7) Measurement based Modeling Characterization of existing boards Measurement with VNA TDR/TDT Characterization up to 20 GHz BW TDR of Memory Riser Card EKH - EyeKnowHow 11/11/10 21
  • 22. 7) Measurement based Modeling Definition, Design and Layout of Characterization boards Lumped model fitting Insertion Loss Blue: Model Red: Measurement Testboard for S-Parameter Measurements FEXT ADS model fitted to measurement results NEXT EKH - EyeKnowHow 11/11/10 22
  • 23. 7) Measurement based Modeling Physical X-sections Measure what the manufacturer delivers Create model based on real Hardware Dielectric (FR4) Traces Cross section of PCB with blind and micro vias (transmission line) Vias EKH - EyeKnowHow 11/11/10 23
  • 24. 8) Correlation Measurements Dataeye @ 5.3Gb Measured vs. Simulated / Ball vs. Pad 2x65 Ohm (initial Setting) Measurement @ ball Simulated @ ball Simulated @ pad 2x45 Ohm (matched to the differential PCB Channel impedance) Measurement @ ball Simulated @ ball Simulated @ pad EKH - EyeKnowHow 11/11/10 24
  • 25. 9) Logic Analyzer Command Trace evaluation Digital timing Trace evaluation Spec compliant timings / Finding timing violations Digital Timing Settings / MRS setting EKH - EyeKnowHow 11/11/10 25
  • 26. 9) Logic Analyzer Command Trace evaluation Statistical Command sequence evaluation Timings: Statistical Access evaluation AL=3 BL=4 RL=4 TCCD=2 TCK=3750 TFAW=14 TPDN=0 TRAS=12 TRC=16 TRCD=4 TRFC=54 TRP=4 TRRD=3 TRTP=2 TRTW=2 TWR=4 TWTR=2 VDD=1800 WIDTH=64 WL=3 XT=1 Performance/Power Optimization Command Bank_00 Bank_01 Bank_02 Bank_03 Bank_04 Bank_05 Bank_06 Bank_07 Banks_All TOTAL RD 1289 402 1180 3884 0 0 0 7 0 6762 WR 1107 402 0 7 0 0 0 4 0 1520 ACT 45 31 31 30 0 0 0 1 0 138 Observed timings RD_AP WR_AP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name Min Max Name Min Max PRE 16 2 2 1 0 0 0 1 0 22 tRAS_bank_0 12 2025 tRC_bank_0 16 2150 PRE_A 0 0 0 0 0 0 0 0 30 30 tRAS_bank_1 259 2025 tRC_bank_1 761 2158 des 0 0 0 0 0 0 0 0 55843 55843 tRAS_bank_2 450 2020 tRC_bank_2 718 2182 nop 0 0 0 0 0 0 0 0 0 0 tRAS_bank_3 1874 2030 tRC_bank_3 2032 2122 MRS 0 0 0 0 0 0 0 0 0 0 tRAS_bank_4 - - tRC_bank_4 - - REF 0 0 0 0 0 0 0 0 31 31 tRAS_bank_5 - - tRC_bank_5 - - SRE 0 0 0 0 0 0 0 0 0 0 SRX 0 0 0 0 0 0 0 0 0 0 tRAS_bank_6 - - tRC_bank_6 - - PDE 0 0 0 0 0 0 0 0 0 0 tRAS_bank_7 573 573 tRC_bank_7 - - PDX 0 0 0 0 0 0 0 0 0 0 tRAS_rank 12 2030 tRC_rank 16 2182 PRE_I 0 0 0 0 0 0 0 0 0 0 PDCONT 0 0 0 0 0 0 0 0 0 0 tRCD_bank_0 1 5 tRP_bank_0* 4 124 BST 0 0 0 0 0 0 0 0 0 0 tRCD_bank_1 1 11 tRP_bank_1* 5 1763 DPD 0 0 0 0 0 0 0 0 0 0 tRCD_bank_2 1 6 tRP_bank_2* 5 268 tRCD_bank_3 1 10 tRP_bank_3* 5 142 tRCD_bank_4 - - tRP_bank_4* - - tRCD_bank_5 - - tRP_bank_5* - - tRCD_bank_6 - - tRP_bank_6* - - tRCD_bank_7 5 5 tRP_bank_7* 1089 1089 tRCD_rank 1 11 tRP_rank 4 1763 tRFC 55 55 tREFI 2072 2091 tRRD 3 2070 tCCD 2 77 EKH - EyeKnowHow 11/11/10 26
  • 27. 10) Failure analysis Memory test failure Analyis Evaluate log files from Software Memory tests Narrow down failure reason DQ vs. CA related fail Single DQ vs. DQS fail Read vs. Write fail Device vs. Signal integrity related fail Vref Margin test implementation Adjust VREF until fail and evaluate fail behavior Timing Margin test implementation Change Controller delays (DQS and CLK) until fail and evaluate fail behavior 12742808 12742822 FAILURE: possible bad address line at offset FAILURE: possible bad address line at offset 0x00000000 = 0x018A5141 = address 0x062D4504 address 0x099C0038 Expected value F9D2BAFB, Read value 8002BAFB Expected value F663FFC7, Read value 099C0038 Re-Read: Re-Read: Expected value F9D2BAFB, Read value 8002BAFB Expected value F663FFC7, Read value 099C0038 Expected value F9D2BAFB, Read value 8002BAFB Expected value F663FFC7, Read value 099C0038 Expected value F9D2BAFB, Read value 8002BAFB Expected value F663FFC7, Read value 099C0038 Expected value F9D2BAFB, Read value 8002BAFB Expected value F663FFC7, Read value 099C0038 Skipping to next test... EKH - EyeKnowHow 11/11/10 27
  • 28. 11) Design / Layout 4GB DDR2 Registered DDR2 RDIMM 4GB EKH - EyeKnowHow 11/11/10 28
  • 29. 11) Design / Layout DDR3 Unbuffered VLP DDR3 UBU VLP 1Rx8/2Rx8 ECC/non ECC: DIMM view Top view ECC Termination CA BUS RANK 0 Termination Bottom view ECC CA BUS RANK 1 EKH - EyeKnowHow 11/11/10 29
  • 30. 11) Design / Layout DDR3 Unbuffered VLP : Timing budget Setup/Hold: 558ps/336ps Setup/Hold: 532ps/368ps Setup/Hold: 511ps/336ps WEAK CASE 39 ohm Termination D0 D1 D2 Setup/Hold: 481ps /334ps Setup/Hold: 423ps/406ps Setup/Hold: 341ps/478ps D3 D8-ECC D4 Setup/Hold: 298ps/513ps Setup/Hold: 273ps/512ps Setup/Hold: 226ps/524ps D5 D6 D7 EKH - EyeKnowHow 11/11/10 30
  • 31. 12) EMC / EMI Investigations Spec. Limits & Measurements system specification limits (e.g. for PC, Server) measurement results DDR2 P-/R-DIMM on SUN Fire T2000 "Ontario" EKH - EyeKnowHow 11/11/10 31