SlideShare une entreprise Scribd logo
1  sur  44
SystemC Overview
林敬倫, 蘇文鈺
成大資訊
2010
Architecture
• C++ and STL
–
–
–
–
–
–
–
–

SystemC Simulation Kernel
Thread and Method
TLM 2.0 Lib
AMS (Not Stable yet)
Event and Sensitivity
Channel and Interface
Modules
Data Type
• Predefined Channels: Mutex, FIFO and Signals
– IP
– User Lib
Environment
• SystemC as a C++ class library, you need
– SystemC Library: can be downloaded at:
• http://www.systemc.org/downloads

– C++ Compiler: GNU C++, Sun C++,…
– O.S.: Solaris, Linux, UNIX, Windows
– Compiler command sequence, makefile, or others
similar
– GUI (Option available in tools like CoWare and
OpenESL)
Simple Example: Hello world
• Program規格如下
– 用SC_Method
– Clock=10 ns
– 每個clock印一下”Hello World”以及現在的時間
– 跑100 cycles
– 可用一般command line的方式compile
– 可用makefile
– 執行的過程與結果
Hello World程式專案說明
• 其中包含三個檔案main.cpp,
hello_module.h hello_module.cpp
• 可將main.cpp視同電路板,我們可以在上面
做接線等等的動作。
• hello_module可以被視為是一個具有process
功能的硬體元件。
Main.cpp
將所需元件的.h檔和systemC.h引入
Sc_main是systemC程式的進入點
宣告一組clk的訊號 週期為10ns

宣告一組hello_module的元件
將clk接上module的clk訊號上
開始進行模擬 模擬1000ns內的硬體
運作
Hello_module.h
宣告一組元件定義hello_module
宣告hello_module的訊號線clk
宣告hello_module的運作函式

hello_module的建構子
整組元件具有process(method)
process執行的函式Method_func
Process會經由clk正緣觸發
Hello_module.cpp
運作函式本體
訊號有產生改變才執行
印出模擬時間

印出hello word!
執行結果
Component
• A HW system is usually divided into several separate
components.
• Normally, components work independently until
communication is needed among components.
• Components can work synchronously or
asynchronously
• In HW design, certain hierarchy built from components
is required.
• Similar development methodology can be found in
CBSD (Component Based Software Development).
• In SystemC, components are usually called modules.
Wikipedia says:
• CBSD is a branch of software engineering, the priority of which is
the separation of concerns in respect of the wide-ranging
functionality available throughout a given software system.
Components are considered to be part of the starting platform for
service orientation throughout software engineering, for example
Web Services, and more recently, Service-Oriented Architecture
(SOA) - whereby a component is converted into a service and
subsequently inherits further characteristics beyond that of an
ordinary component.
• With regards to system-wide co-ordination, components
communicate with each other via interfaces. When a
component offers services to the rest of the system, it adopts a
provided interface which specifies the services that can be utilized
by other components and how.
DataFlow
• CBSD is often incorporated with dataflow
model.
• 顧名思義: 元件之間所需與所產出的資料是
用類似資料流的方式傳遞
• 而彼此之間也經常靠資料流在同步其動作
Wikipedia says:
• Dataflow is a software architecture based on
the idea that changing the value of a variable
should automatically force recalculation of the
values of other variables.
• SO, how to use dataflow in programming?
– Flow Based Programming.
Wikipedia says:
•

•

•

•

flow-based programming (FBP) is a programming paradigm that defines applications as networks
of "black box" processes, which exchange data across predefined connections by message passing.
These black box processes can be reconnected endlessly to form different applications without
having to be changed internally. FBP is thus naturally component-oriented.
The FBP development approach views an application not as a single, sequential, process, which
starts at a point in time, and then does one thing at a time until it is finished, but as a network of
asynchronous processes communicating by means of streams of structured data chunks, called
"information packets" (IPs). In this view, the focus is on the application data and the
transformations applied to it to produce the desired outputs. The network is defined externally to
the processes, as a list of connections which is interpreted by a piece of software, usually called the
"scheduler".
The processes communicate by means of fixed-capacity connections. A connection is attached to a
process by means of a port, which has a name agreed upon between the process code and the
network definition. More than one process can execute the same piece of code. At any point in
time, a given IP can only be "owned" by a single process, or be in transit between two processes.
Ports may either be simple, or array-type, as used e.g. for the input port of the Collate component
described below. It is the combination of ports with asynchronous processes that allows many longrunning primitive functions of data processing, such as Sort, Merge, Summarize, etc., to be
supported in the form of software black boxes.
The network definition is usually diagrammatic, and is converted into a connection list in some
lower-level language or notation. FBP is thus a visual programming language at this level. More
complex network definitions have a hierarchical structure, being built up from subnets with "sticky"
connections.
字太多, 看圖說故事比較快

http://www.edrawsoft.com/Data-Flow-Model-Diagram.php
How components are implemented in
SystemC?
• SC_Module: registered in SystemC simulation
kernel
• Elaboration
– Thread: SC_THREAD or SC_CTHREAD(now seldom
used, but may be useful for synthesizable SystemC
syntax)
– Method: SC_Method
SC_METHOD
• A simple member function of SC_MODULE
class.
• No arguments and no return values
• During simulation, SystemC simulation kernel
calls it repeatedly.
• It is also concurrently executed (in concept or
in user’s point of view).
SC_THREAD
• It can suspend itself. So, it allows time to pass by.
• Hence, when SC_THREAD is executed one time,
SC_METHOD may have been executed several times.
• Conceptually, it is like a software thread, but not
exactly because of the nature of the current simulation
kernel. We will touch this later when we introduce the
mechanism of this simulation kernel.
• SC_CTHREAD is a SC_THREAD requiring the sensitivity
with respect to a clock signal. That is why it may be
considered as synthesizable syntax.
Concurrency and Synchronization
Mechanisms
• Since all modules have to be executed concurrently in
user’s point of view, mechanisms have to be built to
maintain the consistency of concurrent execution.
• Events and Notification are applied.
• Event is implemented by sc_event class. notify, which
is a member function of sc_event, can be used.
• A module is invoked through the sensitivity to certain
events. For example, sensitive to a clock event or a bus
event.
• In SystemC, Static and Dynamic of event sensitivity
implementations are available.
Communication
• Like all dataflow or CB programming models,
communication among modules is important.
• Unlike Verilog, SystemC separates the
implementation mechanisms of computation and
communication. That is, modules are mainly for
computation. Communication is done through
provided interface and channel.
• Channel is used to interconnect modules.
• Port is used to connect channel to module.
• Interface can be used when implementing
channels.
System Component
Modules

Channels

Ports

Interface Only

Port plus
Interface

Events

Threads&Methods

Ports
Hierarchical Structure
• A component may contain several modules and
the component is itself a module.
• A component contains intra-communication
mechanisms such as ports interfaces, and
channels.
• A component also contains ports for intercommunication, which will be connected to some
channels.
• Events are contained for synchronization and
execution.
• Computation part is realized in internal modules.
Spec. of Example program
• 規格:

– 系統有兩個modules, 每一個module 又包含兩個
modules, 利用clock來做event
– 主要的兩個modules的工作只是互相交換資料, 簡單
運算後再傳回給對方
– 主要模組中的內部兩個模組又分成運算與存檔的工
作.
– 主要的兩個modules用簡單的bus連接,內部兩個模
組用簡單的channel連接
– 用SC_METHOD與SC_THREAD來實現之, 也就是一個
module用SC_METHOD, 另外一個module用
SC_THREAD
Example Program Abstract
• Thread module內有兩組sub module為save
module及alu module
– save module 用於將thread module現存的費氏數列
兩個數字存入檔案中
– alu module 利用已存費氏數列數字計算下兩組數字

• 兩組thread module 透過bus連接將計算好的下
兩位數字透過bus傳給另一組thread module使
整份檔案輸出一組完整的費氏數列並標註寫入
檔案的module
Data(1,1)
save

process

alu

Thread module0

Write port
Write port
BUS
Write port
Write port

CLK

save

process

alu

Thread module
Data(1,1)
save

process

Data(2,3)
alu

Thread module0

Write port
Write port
BUS
Write port
Write port

CLK

save

process

alu

Thread module
save

process

alu

Thread module0

Write port
Write port

Data(2,3)
BUS

Write port
Write port

CLK

save

process

alu

Thread module
save

process

alu

Thread module0

Write port
Write port
BUS
Write port

CLK

save

Data(2,3)

process

Write port

alu

Thread module
save

process

alu

Thread module0

Write port
Write port
BUS
Write port
Write port

CLK

save
Data(2,3)

process

alu

Thread module
save

process

alu

Thread module0

Write port
Write port
BUS
Write port
Write port

CLK

save

process

Data(2,3)

alu
Data(5,8)

Thread module
save

process

alu

Thread module0

Write port
Write port
BUS
Write port
Write port
Data(5,8)

CLK

save

process

alu

Thread module
save

process

alu

Thread module0

Write port
Write port

Data(5,8)
BUS

Write port
Write port

CLK

save

process

alu

Thread module
Data(5,8)
save

process

alu

Thread module0

Write port
Write port
BUS
Write port
Write port

CLK

save

process

alu

Thread module
Main.cpp
Bus_if.h
Alu.h
Alu.cpp
Bus.h
Bus.cpp
Save.h
Save.cpp
Thread.h
Thread.h
Thread.cpp

Contenu connexe

Tendances

Detecting hardware virtualization rootkits
Detecting hardware virtualization rootkitsDetecting hardware virtualization rootkits
Detecting hardware virtualization rootkitsEdgar Barbosa
 
Verilog HDL Verification
Verilog HDL VerificationVerilog HDL Verification
Verilog HDL Verificationdennis gookyi
 
How to Connect SystemVerilog with Octave
How to Connect SystemVerilog with OctaveHow to Connect SystemVerilog with Octave
How to Connect SystemVerilog with OctaveAmiq Consulting
 
structural modeling, hazards
structural modeling, hazardsstructural modeling, hazards
structural modeling, hazardsdennis gookyi
 
System verilog control flow
System verilog control flowSystem verilog control flow
System verilog control flowPushpa Yakkala
 
Advanced modeling techniques
Advanced modeling techniquesAdvanced modeling techniques
Advanced modeling techniquesdennis gookyi
 
Glow user review
Glow user reviewGlow user review
Glow user review冠旭 陳
 
Other Approaches (Concurrency)
Other Approaches (Concurrency)Other Approaches (Concurrency)
Other Approaches (Concurrency)Sri Prasanna
 
Sstic 2015 detailed_version_triton_concolic_execution_frame_work_f_saudel_jsa...
Sstic 2015 detailed_version_triton_concolic_execution_frame_work_f_saudel_jsa...Sstic 2015 detailed_version_triton_concolic_execution_frame_work_f_saudel_jsa...
Sstic 2015 detailed_version_triton_concolic_execution_frame_work_f_saudel_jsa...Jonathan Salwan
 
Hierachical structural modeling
Hierachical structural modelingHierachical structural modeling
Hierachical structural modelingdennis gookyi
 
System verilog important
System verilog importantSystem verilog important
System verilog importantelumalai7
 
E bpf and dynamic tracing for mariadb db as (mariadb day during fosdem 2020)
E bpf and dynamic tracing for mariadb db as (mariadb day during fosdem 2020)E bpf and dynamic tracing for mariadb db as (mariadb day during fosdem 2020)
E bpf and dynamic tracing for mariadb db as (mariadb day during fosdem 2020)Valeriy Kravchuk
 
Finding Bugs Faster with Assertion Based Verification (ABV)
Finding Bugs Faster with Assertion Based Verification (ABV)Finding Bugs Faster with Assertion Based Verification (ABV)
Finding Bugs Faster with Assertion Based Verification (ABV)DVClub
 
Implementation - Sample Runs
Implementation - Sample RunsImplementation - Sample Runs
Implementation - Sample RunsAdwiteeya Agrawal
 
Valgrind tutorial
Valgrind tutorialValgrind tutorial
Valgrind tutorialSatabdi Das
 
Java Jit. Compilation and optimization by Andrey Kovalenko
Java Jit. Compilation and optimization by Andrey KovalenkoJava Jit. Compilation and optimization by Andrey Kovalenko
Java Jit. Compilation and optimization by Andrey KovalenkoValeriia Maliarenko
 

Tendances (20)

Detecting hardware virtualization rootkits
Detecting hardware virtualization rootkitsDetecting hardware virtualization rootkits
Detecting hardware virtualization rootkits
 
Verilog HDL Verification
Verilog HDL VerificationVerilog HDL Verification
Verilog HDL Verification
 
How to Connect SystemVerilog with Octave
How to Connect SystemVerilog with OctaveHow to Connect SystemVerilog with Octave
How to Connect SystemVerilog with Octave
 
structural modeling, hazards
structural modeling, hazardsstructural modeling, hazards
structural modeling, hazards
 
System verilog control flow
System verilog control flowSystem verilog control flow
System verilog control flow
 
Synthesis
SynthesisSynthesis
Synthesis
 
Advanced modeling techniques
Advanced modeling techniquesAdvanced modeling techniques
Advanced modeling techniques
 
Glow user review
Glow user reviewGlow user review
Glow user review
 
3DD 1e Laura
3DD 1e Laura3DD 1e Laura
3DD 1e Laura
 
Other Approaches (Concurrency)
Other Approaches (Concurrency)Other Approaches (Concurrency)
Other Approaches (Concurrency)
 
Sstic 2015 detailed_version_triton_concolic_execution_frame_work_f_saudel_jsa...
Sstic 2015 detailed_version_triton_concolic_execution_frame_work_f_saudel_jsa...Sstic 2015 detailed_version_triton_concolic_execution_frame_work_f_saudel_jsa...
Sstic 2015 detailed_version_triton_concolic_execution_frame_work_f_saudel_jsa...
 
FIFOPt
FIFOPtFIFOPt
FIFOPt
 
Hierachical structural modeling
Hierachical structural modelingHierachical structural modeling
Hierachical structural modeling
 
Introduction to MPI
Introduction to MPIIntroduction to MPI
Introduction to MPI
 
System verilog important
System verilog importantSystem verilog important
System verilog important
 
E bpf and dynamic tracing for mariadb db as (mariadb day during fosdem 2020)
E bpf and dynamic tracing for mariadb db as (mariadb day during fosdem 2020)E bpf and dynamic tracing for mariadb db as (mariadb day during fosdem 2020)
E bpf and dynamic tracing for mariadb db as (mariadb day during fosdem 2020)
 
Finding Bugs Faster with Assertion Based Verification (ABV)
Finding Bugs Faster with Assertion Based Verification (ABV)Finding Bugs Faster with Assertion Based Verification (ABV)
Finding Bugs Faster with Assertion Based Verification (ABV)
 
Implementation - Sample Runs
Implementation - Sample RunsImplementation - Sample Runs
Implementation - Sample Runs
 
Valgrind tutorial
Valgrind tutorialValgrind tutorial
Valgrind tutorial
 
Java Jit. Compilation and optimization by Andrey Kovalenko
Java Jit. Compilation and optimization by Andrey KovalenkoJava Jit. Compilation and optimization by Andrey Kovalenko
Java Jit. Compilation and optimization by Andrey Kovalenko
 

En vedette

Track c-High speed transaction-based hw-sw coverification -eve
Track c-High speed transaction-based hw-sw coverification -eveTrack c-High speed transaction-based hw-sw coverification -eve
Track c-High speed transaction-based hw-sw coverification -evechiportal
 
Top five reasons why every DV engineer will love the latest systemverilog 201...
Top five reasons why every DV engineer will love the latest systemverilog 201...Top five reasons why every DV engineer will love the latest systemverilog 201...
Top five reasons why every DV engineer will love the latest systemverilog 201...Srinivasan Venkataramanan
 
A Systematic Approach to Creating Behavioral Models (white paper) v1.0
A Systematic Approach to Creating Behavioral Models (white paper) v1.0A Systematic Approach to Creating Behavioral Models (white paper) v1.0
A Systematic Approach to Creating Behavioral Models (white paper) v1.0Robert O. Peruzzi, PhD, PE, DFE
 
SystemVerilog Assertions (SVA) in the Design/Verification Process
SystemVerilog Assertions (SVA) in the Design/Verification ProcessSystemVerilog Assertions (SVA) in the Design/Verification Process
SystemVerilog Assertions (SVA) in the Design/Verification ProcessDVClub
 
UVM Ral model usage
UVM Ral model usageUVM Ral model usage
UVM Ral model usageParth Pandya
 
UVM Update: Register Package
UVM Update: Register PackageUVM Update: Register Package
UVM Update: Register PackageDVClub
 
Design and Implementation of an Advanced DMA Controller on AMBA-Based SoC
Design and Implementation of an Advanced DMA Controller on AMBA-Based SoCDesign and Implementation of an Advanced DMA Controller on AMBA-Based SoC
Design and Implementation of an Advanced DMA Controller on AMBA-Based SoCRabindranath Tagore University, Bhopal
 

En vedette (15)

MixedSignal UVM Demo CDNLive
MixedSignal UVM Demo CDNLiveMixedSignal UVM Demo CDNLive
MixedSignal UVM Demo CDNLive
 
Track c-High speed transaction-based hw-sw coverification -eve
Track c-High speed transaction-based hw-sw coverification -eveTrack c-High speed transaction-based hw-sw coverification -eve
Track c-High speed transaction-based hw-sw coverification -eve
 
Top five reasons why every DV engineer will love the latest systemverilog 201...
Top five reasons why every DV engineer will love the latest systemverilog 201...Top five reasons why every DV engineer will love the latest systemverilog 201...
Top five reasons why every DV engineer will love the latest systemverilog 201...
 
A Systematic Approach to Creating Behavioral Models (white paper) v1.0
A Systematic Approach to Creating Behavioral Models (white paper) v1.0A Systematic Approach to Creating Behavioral Models (white paper) v1.0
A Systematic Approach to Creating Behavioral Models (white paper) v1.0
 
SystemVerilog Assertions (SVA) in the Design/Verification Process
SystemVerilog Assertions (SVA) in the Design/Verification ProcessSystemVerilog Assertions (SVA) in the Design/Verification Process
SystemVerilog Assertions (SVA) in the Design/Verification Process
 
UVM Ral model usage
UVM Ral model usageUVM Ral model usage
UVM Ral model usage
 
UVM Update: Register Package
UVM Update: Register PackageUVM Update: Register Package
UVM Update: Register Package
 
stack
stackstack
stack
 
Design and Implementation of an Advanced DMA Controller on AMBA-Based SoC
Design and Implementation of an Advanced DMA Controller on AMBA-Based SoCDesign and Implementation of an Advanced DMA Controller on AMBA-Based SoC
Design and Implementation of an Advanced DMA Controller on AMBA-Based SoC
 
Queue
QueueQueue
Queue
 
Tree
TreeTree
Tree
 
Queue
QueueQueue
Queue
 
Processes and threads
Processes and threadsProcesses and threads
Processes and threads
 
Queuing Theory
Queuing TheoryQueuing Theory
Queuing Theory
 
SystemC
SystemCSystemC
SystemC
 

Similaire à Systemc overview 2010

System on Chip Design and Modelling Dr. David J Greaves
System on Chip Design and Modelling   Dr. David J GreavesSystem on Chip Design and Modelling   Dr. David J Greaves
System on Chip Design and Modelling Dr. David J GreavesSatya Harish
 
Cloudify workshop at CCCEU 2014
Cloudify workshop at CCCEU 2014 Cloudify workshop at CCCEU 2014
Cloudify workshop at CCCEU 2014 Uri Cohen
 
.net Based Component Technologies
.net Based Component Technologies.net Based Component Technologies
.net Based Component Technologiesprakashk453625
 
(ATS3-DEV04) Introduction to Pipeline Pilot Protocol Development for Developers
(ATS3-DEV04) Introduction to Pipeline Pilot Protocol Development for Developers(ATS3-DEV04) Introduction to Pipeline Pilot Protocol Development for Developers
(ATS3-DEV04) Introduction to Pipeline Pilot Protocol Development for DevelopersBIOVIA
 
VTU 6th Sem Elective CSE - Module 3 cloud computing
VTU 6th Sem Elective CSE - Module 3 cloud computingVTU 6th Sem Elective CSE - Module 3 cloud computing
VTU 6th Sem Elective CSE - Module 3 cloud computingSachin Gowda
 
Presentation on Behavioral Synthesis & SystemC
Presentation on Behavioral Synthesis & SystemCPresentation on Behavioral Synthesis & SystemC
Presentation on Behavioral Synthesis & SystemCMukit Ahmed Chowdhury
 
Concurrency Programming in Java - 01 - Introduction to Concurrency Programming
Concurrency Programming in Java - 01 - Introduction to Concurrency ProgrammingConcurrency Programming in Java - 01 - Introduction to Concurrency Programming
Concurrency Programming in Java - 01 - Introduction to Concurrency ProgrammingSachintha Gunasena
 
5.7 Parallel Processing - Reactive Programming.pdf.pptx
5.7 Parallel Processing - Reactive Programming.pdf.pptx5.7 Parallel Processing - Reactive Programming.pdf.pptx
5.7 Parallel Processing - Reactive Programming.pdf.pptxMohamedBilal73
 
Effective admin and development in iib
Effective admin and development in iibEffective admin and development in iib
Effective admin and development in iibm16k
 
Intro to Microsoft.NET
Intro to Microsoft.NET Intro to Microsoft.NET
Intro to Microsoft.NET rchakra
 
Runos OpenFlow Controller (eng)
Runos OpenFlow Controller (eng)Runos OpenFlow Controller (eng)
Runos OpenFlow Controller (eng)Alexander Shalimov
 
Tech presentation (part 1)
Tech presentation (part 1)Tech presentation (part 1)
Tech presentation (part 1)Abhijit Roy
 
Current & Future Use-Cases of OpenDaylight
Current & Future Use-Cases of OpenDaylightCurrent & Future Use-Cases of OpenDaylight
Current & Future Use-Cases of OpenDaylightabhijit2511
 
Diksha sda presentation
Diksha sda presentationDiksha sda presentation
Diksha sda presentationdikshagupta111
 
Lec 2 (parallel design and programming)
Lec 2 (parallel design and programming)Lec 2 (parallel design and programming)
Lec 2 (parallel design and programming)Sudarshan Mondal
 
Week # 1.pdf
Week # 1.pdfWeek # 1.pdf
Week # 1.pdfgiddy5
 
Pune-Cocoa: Blocks and GCD
Pune-Cocoa: Blocks and GCDPune-Cocoa: Blocks and GCD
Pune-Cocoa: Blocks and GCDPrashant Rane
 
06_1_design_flow.ppt
06_1_design_flow.ppt06_1_design_flow.ppt
06_1_design_flow.pptMohammedMianA
 

Similaire à Systemc overview 2010 (20)

System on Chip Design and Modelling Dr. David J Greaves
System on Chip Design and Modelling   Dr. David J GreavesSystem on Chip Design and Modelling   Dr. David J Greaves
System on Chip Design and Modelling Dr. David J Greaves
 
Cloudify workshop at CCCEU 2014
Cloudify workshop at CCCEU 2014 Cloudify workshop at CCCEU 2014
Cloudify workshop at CCCEU 2014
 
.net Based Component Technologies
.net Based Component Technologies.net Based Component Technologies
.net Based Component Technologies
 
(ATS3-DEV04) Introduction to Pipeline Pilot Protocol Development for Developers
(ATS3-DEV04) Introduction to Pipeline Pilot Protocol Development for Developers(ATS3-DEV04) Introduction to Pipeline Pilot Protocol Development for Developers
(ATS3-DEV04) Introduction to Pipeline Pilot Protocol Development for Developers
 
VTU 6th Sem Elective CSE - Module 3 cloud computing
VTU 6th Sem Elective CSE - Module 3 cloud computingVTU 6th Sem Elective CSE - Module 3 cloud computing
VTU 6th Sem Elective CSE - Module 3 cloud computing
 
Presentation on Behavioral Synthesis & SystemC
Presentation on Behavioral Synthesis & SystemCPresentation on Behavioral Synthesis & SystemC
Presentation on Behavioral Synthesis & SystemC
 
Concurrency Programming in Java - 01 - Introduction to Concurrency Programming
Concurrency Programming in Java - 01 - Introduction to Concurrency ProgrammingConcurrency Programming in Java - 01 - Introduction to Concurrency Programming
Concurrency Programming in Java - 01 - Introduction to Concurrency Programming
 
5.7 Parallel Processing - Reactive Programming.pdf.pptx
5.7 Parallel Processing - Reactive Programming.pdf.pptx5.7 Parallel Processing - Reactive Programming.pdf.pptx
5.7 Parallel Processing - Reactive Programming.pdf.pptx
 
1.My Presentation.pptx
1.My Presentation.pptx1.My Presentation.pptx
1.My Presentation.pptx
 
Effective admin and development in iib
Effective admin and development in iibEffective admin and development in iib
Effective admin and development in iib
 
Intro to Microsoft.NET
Intro to Microsoft.NET Intro to Microsoft.NET
Intro to Microsoft.NET
 
Runos OpenFlow Controller (eng)
Runos OpenFlow Controller (eng)Runos OpenFlow Controller (eng)
Runos OpenFlow Controller (eng)
 
Tech presentation (part 1)
Tech presentation (part 1)Tech presentation (part 1)
Tech presentation (part 1)
 
Current & Future Use-Cases of OpenDaylight
Current & Future Use-Cases of OpenDaylightCurrent & Future Use-Cases of OpenDaylight
Current & Future Use-Cases of OpenDaylight
 
Diksha sda presentation
Diksha sda presentationDiksha sda presentation
Diksha sda presentation
 
Lec 2 (parallel design and programming)
Lec 2 (parallel design and programming)Lec 2 (parallel design and programming)
Lec 2 (parallel design and programming)
 
Aca module 1
Aca module 1Aca module 1
Aca module 1
 
Week # 1.pdf
Week # 1.pdfWeek # 1.pdf
Week # 1.pdf
 
Pune-Cocoa: Blocks and GCD
Pune-Cocoa: Blocks and GCDPune-Cocoa: Blocks and GCD
Pune-Cocoa: Blocks and GCD
 
06_1_design_flow.ppt
06_1_design_flow.ppt06_1_design_flow.ppt
06_1_design_flow.ppt
 

Dernier

DevEX - reference for building teams, processes, and platforms
DevEX - reference for building teams, processes, and platformsDevEX - reference for building teams, processes, and platforms
DevEX - reference for building teams, processes, and platformsSergiu Bodiu
 
Gen AI in Business - Global Trends Report 2024.pdf
Gen AI in Business - Global Trends Report 2024.pdfGen AI in Business - Global Trends Report 2024.pdf
Gen AI in Business - Global Trends Report 2024.pdfAddepto
 
Unleash Your Potential - Namagunga Girls Coding Club
Unleash Your Potential - Namagunga Girls Coding ClubUnleash Your Potential - Namagunga Girls Coding Club
Unleash Your Potential - Namagunga Girls Coding ClubKalema Edgar
 
Advanced Test Driven-Development @ php[tek] 2024
Advanced Test Driven-Development @ php[tek] 2024Advanced Test Driven-Development @ php[tek] 2024
Advanced Test Driven-Development @ php[tek] 2024Scott Keck-Warren
 
The Ultimate Guide to Choosing WordPress Pros and Cons
The Ultimate Guide to Choosing WordPress Pros and ConsThe Ultimate Guide to Choosing WordPress Pros and Cons
The Ultimate Guide to Choosing WordPress Pros and ConsPixlogix Infotech
 
Advanced Computer Architecture – An Introduction
Advanced Computer Architecture – An IntroductionAdvanced Computer Architecture – An Introduction
Advanced Computer Architecture – An IntroductionDilum Bandara
 
TeamStation AI System Report LATAM IT Salaries 2024
TeamStation AI System Report LATAM IT Salaries 2024TeamStation AI System Report LATAM IT Salaries 2024
TeamStation AI System Report LATAM IT Salaries 2024Lonnie McRorey
 
Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024BookNet Canada
 
Connect Wave/ connectwave Pitch Deck Presentation
Connect Wave/ connectwave Pitch Deck PresentationConnect Wave/ connectwave Pitch Deck Presentation
Connect Wave/ connectwave Pitch Deck PresentationSlibray Presentation
 
TrustArc Webinar - How to Build Consumer Trust Through Data Privacy
TrustArc Webinar - How to Build Consumer Trust Through Data PrivacyTrustArc Webinar - How to Build Consumer Trust Through Data Privacy
TrustArc Webinar - How to Build Consumer Trust Through Data PrivacyTrustArc
 
SAP Build Work Zone - Overview L2-L3.pptx
SAP Build Work Zone - Overview L2-L3.pptxSAP Build Work Zone - Overview L2-L3.pptx
SAP Build Work Zone - Overview L2-L3.pptxNavinnSomaal
 
"ML in Production",Oleksandr Bagan
"ML in Production",Oleksandr Bagan"ML in Production",Oleksandr Bagan
"ML in Production",Oleksandr BaganFwdays
 
Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)
Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)
Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)Mark Simos
 
From Family Reminiscence to Scholarly Archive .
From Family Reminiscence to Scholarly Archive .From Family Reminiscence to Scholarly Archive .
From Family Reminiscence to Scholarly Archive .Alan Dix
 
Developer Data Modeling Mistakes: From Postgres to NoSQL
Developer Data Modeling Mistakes: From Postgres to NoSQLDeveloper Data Modeling Mistakes: From Postgres to NoSQL
Developer Data Modeling Mistakes: From Postgres to NoSQLScyllaDB
 
H2O.ai CEO/Founder: Sri Ambati Keynote at Wells Fargo Day
H2O.ai CEO/Founder: Sri Ambati Keynote at Wells Fargo DayH2O.ai CEO/Founder: Sri Ambati Keynote at Wells Fargo Day
H2O.ai CEO/Founder: Sri Ambati Keynote at Wells Fargo DaySri Ambati
 
New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024BookNet Canada
 
Streamlining Python Development: A Guide to a Modern Project Setup
Streamlining Python Development: A Guide to a Modern Project SetupStreamlining Python Development: A Guide to a Modern Project Setup
Streamlining Python Development: A Guide to a Modern Project SetupFlorian Wilhelm
 

Dernier (20)

DevEX - reference for building teams, processes, and platforms
DevEX - reference for building teams, processes, and platformsDevEX - reference for building teams, processes, and platforms
DevEX - reference for building teams, processes, and platforms
 
Gen AI in Business - Global Trends Report 2024.pdf
Gen AI in Business - Global Trends Report 2024.pdfGen AI in Business - Global Trends Report 2024.pdf
Gen AI in Business - Global Trends Report 2024.pdf
 
Unleash Your Potential - Namagunga Girls Coding Club
Unleash Your Potential - Namagunga Girls Coding ClubUnleash Your Potential - Namagunga Girls Coding Club
Unleash Your Potential - Namagunga Girls Coding Club
 
Advanced Test Driven-Development @ php[tek] 2024
Advanced Test Driven-Development @ php[tek] 2024Advanced Test Driven-Development @ php[tek] 2024
Advanced Test Driven-Development @ php[tek] 2024
 
The Ultimate Guide to Choosing WordPress Pros and Cons
The Ultimate Guide to Choosing WordPress Pros and ConsThe Ultimate Guide to Choosing WordPress Pros and Cons
The Ultimate Guide to Choosing WordPress Pros and Cons
 
DMCC Future of Trade Web3 - Special Edition
DMCC Future of Trade Web3 - Special EditionDMCC Future of Trade Web3 - Special Edition
DMCC Future of Trade Web3 - Special Edition
 
Advanced Computer Architecture – An Introduction
Advanced Computer Architecture – An IntroductionAdvanced Computer Architecture – An Introduction
Advanced Computer Architecture – An Introduction
 
TeamStation AI System Report LATAM IT Salaries 2024
TeamStation AI System Report LATAM IT Salaries 2024TeamStation AI System Report LATAM IT Salaries 2024
TeamStation AI System Report LATAM IT Salaries 2024
 
Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
 
Connect Wave/ connectwave Pitch Deck Presentation
Connect Wave/ connectwave Pitch Deck PresentationConnect Wave/ connectwave Pitch Deck Presentation
Connect Wave/ connectwave Pitch Deck Presentation
 
TrustArc Webinar - How to Build Consumer Trust Through Data Privacy
TrustArc Webinar - How to Build Consumer Trust Through Data PrivacyTrustArc Webinar - How to Build Consumer Trust Through Data Privacy
TrustArc Webinar - How to Build Consumer Trust Through Data Privacy
 
E-Vehicle_Hacking_by_Parul Sharma_null_owasp.pptx
E-Vehicle_Hacking_by_Parul Sharma_null_owasp.pptxE-Vehicle_Hacking_by_Parul Sharma_null_owasp.pptx
E-Vehicle_Hacking_by_Parul Sharma_null_owasp.pptx
 
SAP Build Work Zone - Overview L2-L3.pptx
SAP Build Work Zone - Overview L2-L3.pptxSAP Build Work Zone - Overview L2-L3.pptx
SAP Build Work Zone - Overview L2-L3.pptx
 
"ML in Production",Oleksandr Bagan
"ML in Production",Oleksandr Bagan"ML in Production",Oleksandr Bagan
"ML in Production",Oleksandr Bagan
 
Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)
Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)
Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)
 
From Family Reminiscence to Scholarly Archive .
From Family Reminiscence to Scholarly Archive .From Family Reminiscence to Scholarly Archive .
From Family Reminiscence to Scholarly Archive .
 
Developer Data Modeling Mistakes: From Postgres to NoSQL
Developer Data Modeling Mistakes: From Postgres to NoSQLDeveloper Data Modeling Mistakes: From Postgres to NoSQL
Developer Data Modeling Mistakes: From Postgres to NoSQL
 
H2O.ai CEO/Founder: Sri Ambati Keynote at Wells Fargo Day
H2O.ai CEO/Founder: Sri Ambati Keynote at Wells Fargo DayH2O.ai CEO/Founder: Sri Ambati Keynote at Wells Fargo Day
H2O.ai CEO/Founder: Sri Ambati Keynote at Wells Fargo Day
 
New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
 
Streamlining Python Development: A Guide to a Modern Project Setup
Streamlining Python Development: A Guide to a Modern Project SetupStreamlining Python Development: A Guide to a Modern Project Setup
Streamlining Python Development: A Guide to a Modern Project Setup
 

Systemc overview 2010

  • 2. Architecture • C++ and STL – – – – – – – – SystemC Simulation Kernel Thread and Method TLM 2.0 Lib AMS (Not Stable yet) Event and Sensitivity Channel and Interface Modules Data Type • Predefined Channels: Mutex, FIFO and Signals – IP – User Lib
  • 3. Environment • SystemC as a C++ class library, you need – SystemC Library: can be downloaded at: • http://www.systemc.org/downloads – C++ Compiler: GNU C++, Sun C++,… – O.S.: Solaris, Linux, UNIX, Windows – Compiler command sequence, makefile, or others similar – GUI (Option available in tools like CoWare and OpenESL)
  • 4. Simple Example: Hello world • Program規格如下 – 用SC_Method – Clock=10 ns – 每個clock印一下”Hello World”以及現在的時間 – 跑100 cycles – 可用一般command line的方式compile – 可用makefile – 執行的過程與結果
  • 5. Hello World程式專案說明 • 其中包含三個檔案main.cpp, hello_module.h hello_module.cpp • 可將main.cpp視同電路板,我們可以在上面 做接線等等的動作。 • hello_module可以被視為是一個具有process 功能的硬體元件。
  • 10. Component • A HW system is usually divided into several separate components. • Normally, components work independently until communication is needed among components. • Components can work synchronously or asynchronously • In HW design, certain hierarchy built from components is required. • Similar development methodology can be found in CBSD (Component Based Software Development). • In SystemC, components are usually called modules.
  • 11. Wikipedia says: • CBSD is a branch of software engineering, the priority of which is the separation of concerns in respect of the wide-ranging functionality available throughout a given software system. Components are considered to be part of the starting platform for service orientation throughout software engineering, for example Web Services, and more recently, Service-Oriented Architecture (SOA) - whereby a component is converted into a service and subsequently inherits further characteristics beyond that of an ordinary component. • With regards to system-wide co-ordination, components communicate with each other via interfaces. When a component offers services to the rest of the system, it adopts a provided interface which specifies the services that can be utilized by other components and how.
  • 12. DataFlow • CBSD is often incorporated with dataflow model. • 顧名思義: 元件之間所需與所產出的資料是 用類似資料流的方式傳遞 • 而彼此之間也經常靠資料流在同步其動作
  • 13. Wikipedia says: • Dataflow is a software architecture based on the idea that changing the value of a variable should automatically force recalculation of the values of other variables. • SO, how to use dataflow in programming? – Flow Based Programming.
  • 14. Wikipedia says: • • • • flow-based programming (FBP) is a programming paradigm that defines applications as networks of "black box" processes, which exchange data across predefined connections by message passing. These black box processes can be reconnected endlessly to form different applications without having to be changed internally. FBP is thus naturally component-oriented. The FBP development approach views an application not as a single, sequential, process, which starts at a point in time, and then does one thing at a time until it is finished, but as a network of asynchronous processes communicating by means of streams of structured data chunks, called "information packets" (IPs). In this view, the focus is on the application data and the transformations applied to it to produce the desired outputs. The network is defined externally to the processes, as a list of connections which is interpreted by a piece of software, usually called the "scheduler". The processes communicate by means of fixed-capacity connections. A connection is attached to a process by means of a port, which has a name agreed upon between the process code and the network definition. More than one process can execute the same piece of code. At any point in time, a given IP can only be "owned" by a single process, or be in transit between two processes. Ports may either be simple, or array-type, as used e.g. for the input port of the Collate component described below. It is the combination of ports with asynchronous processes that allows many longrunning primitive functions of data processing, such as Sort, Merge, Summarize, etc., to be supported in the form of software black boxes. The network definition is usually diagrammatic, and is converted into a connection list in some lower-level language or notation. FBP is thus a visual programming language at this level. More complex network definitions have a hierarchical structure, being built up from subnets with "sticky" connections.
  • 16. How components are implemented in SystemC? • SC_Module: registered in SystemC simulation kernel • Elaboration – Thread: SC_THREAD or SC_CTHREAD(now seldom used, but may be useful for synthesizable SystemC syntax) – Method: SC_Method
  • 17. SC_METHOD • A simple member function of SC_MODULE class. • No arguments and no return values • During simulation, SystemC simulation kernel calls it repeatedly. • It is also concurrently executed (in concept or in user’s point of view).
  • 18. SC_THREAD • It can suspend itself. So, it allows time to pass by. • Hence, when SC_THREAD is executed one time, SC_METHOD may have been executed several times. • Conceptually, it is like a software thread, but not exactly because of the nature of the current simulation kernel. We will touch this later when we introduce the mechanism of this simulation kernel. • SC_CTHREAD is a SC_THREAD requiring the sensitivity with respect to a clock signal. That is why it may be considered as synthesizable syntax.
  • 19. Concurrency and Synchronization Mechanisms • Since all modules have to be executed concurrently in user’s point of view, mechanisms have to be built to maintain the consistency of concurrent execution. • Events and Notification are applied. • Event is implemented by sc_event class. notify, which is a member function of sc_event, can be used. • A module is invoked through the sensitivity to certain events. For example, sensitive to a clock event or a bus event. • In SystemC, Static and Dynamic of event sensitivity implementations are available.
  • 20. Communication • Like all dataflow or CB programming models, communication among modules is important. • Unlike Verilog, SystemC separates the implementation mechanisms of computation and communication. That is, modules are mainly for computation. Communication is done through provided interface and channel. • Channel is used to interconnect modules. • Port is used to connect channel to module. • Interface can be used when implementing channels.
  • 21. System Component Modules Channels Ports Interface Only Port plus Interface Events Threads&Methods Ports
  • 22. Hierarchical Structure • A component may contain several modules and the component is itself a module. • A component contains intra-communication mechanisms such as ports interfaces, and channels. • A component also contains ports for intercommunication, which will be connected to some channels. • Events are contained for synchronization and execution. • Computation part is realized in internal modules.
  • 23. Spec. of Example program • 規格: – 系統有兩個modules, 每一個module 又包含兩個 modules, 利用clock來做event – 主要的兩個modules的工作只是互相交換資料, 簡單 運算後再傳回給對方 – 主要模組中的內部兩個模組又分成運算與存檔的工 作. – 主要的兩個modules用簡單的bus連接,內部兩個模 組用簡單的channel連接 – 用SC_METHOD與SC_THREAD來實現之, 也就是一個 module用SC_METHOD, 另外一個module用 SC_THREAD
  • 24. Example Program Abstract • Thread module內有兩組sub module為save module及alu module – save module 用於將thread module現存的費氏數列 兩個數字存入檔案中 – alu module 利用已存費氏數列數字計算下兩組數字 • 兩組thread module 透過bus連接將計算好的下 兩位數字透過bus傳給另一組thread module使 整份檔案輸出一組完整的費氏數列並標註寫入 檔案的module
  • 25. Data(1,1) save process alu Thread module0 Write port Write port BUS Write port Write port CLK save process alu Thread module
  • 26. Data(1,1) save process Data(2,3) alu Thread module0 Write port Write port BUS Write port Write port CLK save process alu Thread module
  • 27. save process alu Thread module0 Write port Write port Data(2,3) BUS Write port Write port CLK save process alu Thread module
  • 28. save process alu Thread module0 Write port Write port BUS Write port CLK save Data(2,3) process Write port alu Thread module
  • 29. save process alu Thread module0 Write port Write port BUS Write port Write port CLK save Data(2,3) process alu Thread module
  • 30. save process alu Thread module0 Write port Write port BUS Write port Write port CLK save process Data(2,3) alu Data(5,8) Thread module
  • 31. save process alu Thread module0 Write port Write port BUS Write port Write port Data(5,8) CLK save process alu Thread module
  • 32. save process alu Thread module0 Write port Write port Data(5,8) BUS Write port Write port CLK save process alu Thread module
  • 33. Data(5,8) save process alu Thread module0 Write port Write port BUS Write port Write port CLK save process alu Thread module
  • 36. Alu.h
  • 38. Bus.h