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Chapter 5basic computer organization design,[object Object],Preseneted  by : -,[object Object],    Nikhil  Kumar  Singh,[object Object],B.Sc  Computer  Sc. II yr ,[object Object],    8130,[object Object]
Topics included,[object Object]
INTERRUPT  INITIATED  INPUT/OUTPUT,[object Object],- Open communication only when some data has to be passed --> interrupt.,[object Object],- The I/O interface, instead of the CPU, monitors the I/O device. ,[object Object],-  When the interface founds that the I/O device is ready for data transfer, ,[object Object],	it generates an interrupt request to the CPU,[object Object],-  Upon detecting an interrupt, the CPU stops momentarily the task ,[object Object],	it is doing, branches to the service routine to process the data ,[object Object],	transfer, and then returns to the task it was performing.,[object Object],* IEN (Interrupt-enable flip-flop),[object Object],- can be set and cleared by instructions,[object Object],- when cleared, the computer cannot be interrupted,[object Object]
FLOWCHART  FOR  INTERRUPT  CYCLE,[object Object],=0,[object Object],=1,[object Object],Interrupt cycle,[object Object],Instruction cycle,[object Object],R,[object Object],Store return address,[object Object],Fetch and decode,[object Object],in location 0,[object Object],instructions,[object Object],M[0]  PC,[object Object],=0,[object Object],Execute,[object Object],IEN,[object Object],instructions,[object Object],Branch to location 1,[object Object],=1,[object Object],PC  1,[object Object],=1,[object Object],FGI,[object Object],=0,[object Object],IEN  0,[object Object],   R  0,[object Object],=1,[object Object],FGO,[object Object],=0,[object Object],R  1,[object Object]
- The interrupt cycle is a HW implementation of a branch,[object Object],   	and save return address operation.,[object Object],- At the beginning of the next instruction cycle, the ,[object Object],   	instruction that is read from memory is in address 1.,[object Object],- At memory address 1, the programmer must store a branch instruction ,[object Object],	that sends the control to an interrupt service routine,[object Object],- The instruction that returns the control to the original ,[object Object],	program is  "indirect BUN   0",[object Object]
REGISTER  TRANSFER  OPERATIONS  IN  INTERRUPT CYCLE,[object Object],Memory,[object Object], Before interrupt,[object Object], After interrupt cycle,[object Object],256,[object Object],0,[object Object],0,[object Object],0,[object Object],BUN,[object Object],1120,[object Object],1,[object Object],0,[object Object],BUN,[object Object],1120,[object Object],PC = 1,[object Object],Main,[object Object],Main,[object Object],255,[object Object],255,[object Object],Program,[object Object],Program,[object Object],PC = 256,[object Object], 256,[object Object],1120,[object Object],1120,[object Object],I/O,[object Object],I/O,[object Object],Program,[object Object],Program,[object Object],1,[object Object],BUN,[object Object],0,[object Object],1,[object Object],BUN,[object Object],0,[object Object], Register Transfer Statements for Interrupt Cycle,[object Object],	- R  F/F  1     if IEN (FGI + FGO)T0T1T2,[object Object], T0T1T2 (IEN)(FGI + FGO):   R  1,[object Object],- The fetch and decode phases of the instruction cycle,[object Object],   	must be modified Replace T0, T1, T2  with  R'T0, R'T1, R'T2,[object Object],- The interrupt cycle :,[object Object],	RT0:	AR  0,  TR  PC,[object Object],	RT1:	M[AR]  TR,  PC  0,[object Object],	RT2:	PC  PC + 1,  IEN  0,  R  0, SC  0,[object Object]
12,[object Object],12,[object Object],From bus,[object Object],To bus,[object Object],AR,[object Object],D',[object Object],7,[object Object],I,[object Object],Clock,[object Object],LD,[object Object],T,[object Object],3,[object Object],INR,[object Object],T,[object Object],2,[object Object],CLR,[object Object],R,[object Object],T,[object Object],0,[object Object],D,[object Object],T,[object Object],4,[object Object],CONTROL  OF  REGISTERS  AND  MEMORY,[object Object],Address Register; AR,[object Object],Scan all of the register transfer statements that change the content of AR:,[object Object],R’T0:      AR  PC            LD(AR),[object Object],R’T2:      AR  IR(0-11)    LD(AR),[object Object],D’7IT3:   AR  M[AR]       LD(AR),[object Object],RT0:       AR  0               CLR(AR),[object Object],D5T4:     AR  AR + 1      INR(AR),[object Object],LD(AR) = R'T0 + R'T2 + D'7IT3,[object Object],CLR(AR) = RT0,[object Object],INR(AR) = D5T4,[object Object]
DESIGN  OF  BASIC  COMPUTER,[object Object],Hardware Components of BC ,[object Object],A memory unit:     4096 x 16.,[object Object],Registers:  ,[object Object],           AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC,[object Object],Flip-Flops(Status):  ,[object Object],           I, S, E, R, IEN, FGI, and FGO,[object Object],Decoders:         a 3x8 Opcode decoder,[object Object],                           a 4x16 timing decoder,[object Object],Common bus:   16 bits,[object Object],Control logic gates:,[object Object],Adder and Logic circuit:   Connected to AC,[object Object],Control Logic Gates,[object Object],- Input Controls of the nine registers,[object Object],- Read and Write Controls of memory,[object Object],- Set, Clear, or Complement Controls of the flip-flops,[object Object],- S2, S1, S0  Controls to select a register for the bus,[object Object],- AC, and Adder and Logic circuit,[object Object]

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