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The Cell Processor Computing of tomorrow  or yesterday? Open Systems Design and Development 2007-04-12  |  Heiko J Schick <schickhj@de.ibm.com> © 2007 IBM Corporation
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
1 Introduction
Cell History ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The problem is… … the view from the computer room!
Outlook Source: Kurzweil “ Computer performance increases since 100 years exponential !!!”
But what could you do if all  objects  were   intelligent… … and connected?
What could you do with  unlimited computing power…   for pennies? Could you predict the path of a storm  down to the square kilometer? Could you identify another 20% of proven oil reserves without drilling one hole?
2 Limiters to Processor  Performance
Power Wall / Voltage Wall ,[object Object],[object Object],[object Object],[object Object],[object Object],Source: Tom’s Hardware Guide 1
Memory Wall ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],2
Frequency Wall ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],3
Microprocessor Efficiency ,[object Object],[object Object],[object Object],[object Object],[object Object],Source: Tom’s Hardware Guide Increasing performance requires increasing efficiency !!!
Attacking the Performance Walls ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
3 Cell Architecture
Cell BE Processor ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Key Attributes of Cell ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Power Processor Element (PPE) ,[object Object],[object Object],[object Object],[object Object]
Synergistic Processor Elements (SPEs) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
SPE BLOCK DIAGRAM Permute Unit Load-Store Unit Floating-Point Unit Fixed-Point Unit Branch Unit Channel Unit Result Forwarding and Staging Register File Local Store (256kB) Single Port SRAM 128B Read 128B Write DMA Unit Instruction Issue Unit / Instruction Line Buffer 8 Byte/Cycle 16 Byte/Cycle 128 Byte/Cycle 64 Byte/Cycle On-Chip Coherent Bus
Element Interconnect Bus ,[object Object],[object Object],[object Object],[object Object],Element Interconnect Bus (EIB)
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Element Interconnect Bus (EIB) 16B 16B 16B 16B Data Arb 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B SPE0 SPE2 SPE4 SPE6 SPE7 SPE5 SPE3 SPE1 MIC PPE BIF/IOIF0 IOIF1
Example of eight concurrent transactions MIC SPE0 SPE2 SPE4 SPE6 BIF / IOIF1 Ramp 7 Controller Ramp 8 Controller Ramp 9 Controller Ramp 10 Controller Ramp 11 Controller Controller Ramp 0 Controller Ramp 1 Controller Ramp 2 Controller Ramp 3 Controller Ramp 4 Controller Ramp 5 Controller Ramp 6 Controller Ramp 7 Controller Ramp 8 Controller Ramp 9 Controller Ramp 10 Controller Ramp 11 Data Arbiter Ramp 7 Controller Ramp 8 Controller Ramp 9 Controller Ramp 10 Controller Ramp 11 Controller Controller Ramp 5 Controller Ramp 4 Controller Ramp 3 Controller Ramp 2 Controller Ramp 1 Controller Ramp 0 PPE SPE1 SPE3 SPE5 SPE7 IOIF1 PPE SPE1 SPE3 SPE5 SPE7 IOIF1 PPE SPE1 SPE3 SPE5 SPE7 IOIF1 MIC SPE0 SPE2 SPE4 SPE6 BIF / IOIF0 Ring1 Ring3 Ring0 Ring2 controls
I/O and Memory Interfaces   ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
4 Cell Platform
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Cell  processor can support many systems Cell BE Processor XDR tm XDR tm IOIF0 IOIF1 Cell BE Processor XDR tm XDR tm IOIF BIF Cell BE Processor XDR tm XDR tm IOIF Cell BE Proessor XDR tm XDR tm IOIF BIF Cell BE Processor XDR tm XDR tm IOIF Cell BE Processor XDR tm XDR tm IOIF BIF Cell BE Processor XDR tm XDR tm IOIF SW
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chassis 2x (+12V  RS-485,USB,GbEn) Rambus Design: DRAM 1/2GB Cell BE Processor H8 SP Blade Input Power &Sense Level Convert GbE Phy BladeCenter  Interface Blade Cell BE Processor South Bridge Rambus Design: DRAM 1/2GB South Bridge IB 4X IB 4X Blade QS20 Hardware Description
QS20 Blade (w/o heatsinks)
QS20 Blade Assembly ,[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Options - InfiniBand
Cell Software Stack Firmware Applications SLOF powerpc architecture dependent code Cell Broadband Engine Linux memory management device drivers gcc ppc64, spu backend glibc Hardware RTAS Secondary Boot Loader powerpc- and cell- specific Linux code Low-level FW scheduler (pSeries) (PMac) cell User space Linux common code device drivers
Cell BE Development Platform Cell BE Firmware Graphics Std Devices Developer Workstation Cell Linux kernel Lower-level programming interface Basic Cell runtime: lib_spe, spelibc, … Basic Cell toolchain: gcc, binutils, gdb, oprofile, … Cell aware tooling Application Framework (segment specific) Standard Linux Development Environment    ppc64 Cell optimized libraries Cell specialized compilers Higher-level programming interface Application-level programming interface Tooling Libraries Cell enablement Cell exploitation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],SDK1.0 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],SDK1.1 Execution platform: Cell Simulator  Hosting platform: Linux/86 (FC4) 11/2005 7/2006 SDK 2.0 12/2006 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],SDK1.0.1 Execution platform: Cell Simulator  Cell Blade 1 rev 2 Hosting platform: Linux/86 (FC4) Linux/Cell (FC4)* Linux/Power (FC4)* Execution platform: Cell Simulator  Cell Blade 1 rev 3 Hosting platform: Linux/86 (FC5) Linux/Cell (FC5)* Linux/Power (FC5)* Refresh Execution platform: Cell Simulator  Cell Blade 1 rev 3 Hosting platform: Linux/86 (FC5) Linux/Cell (FC5)* Linux/Power (FC5)* 2/2006 Refresh 9/2006 SDK1.1.1 ,[object Object],[object Object],[object Object],* Subset of tools
Cell library  content (source) ~ 156k loc ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],http://www.alphaworks.ibm.com/tech/cellsw
5 Cell Applications
Peak GFLOPs FreeScale  DC 1.5 GHz PPC 970  2.2 GHz AMD DC  2.2 GHz Intel SC 3.6 GHz Cell  3.0 GHz
Cell Processor Example Application Areas ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Opportunities for Cell BE Blade ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Petroleum Industry A&D Comm Industrial Cell Assets Consumer Public Finance
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],http://folding.stanford.edu/FAQ-PS3.html Dr. V. S. Pande, folding@home, Distributed Computing Project, Stanford University
Ported by 235 584 tetrahedra 48 000 nodes 28 iterations in NKMG solver In  3.8 seconds Sustained Performance for large Objects:  52 GFLOP/s Multigrid Finite Element Solver on Cell using the free SDK www.digitalmedics.de ls7-www.cs.uni-dortmund.de
Computational Fluid Dynamics Solver on Cell Ported by Sustained Performance for large Objects:  Not yet benchmarked (3/2007) using the free SDK www.digitalmedics.de ls7-www.cs.uni-dortmund.de
Computational Fluid Dynamics Solver on Cell A Lattice-Boltzmann Solver Developed by Fraunhofer IWTM http://www.itwm.fraunhofer.de/
Terrain Rendering Engine (TRE) and IBM Blades Systems and Technology Group Commodity Cell BE Blade Add Live Video, Aerial Information, Combat Situational Awareness Next-Gen GCS Combine Data & Render Aircraft data / Field Data BladeCenter-1  Chassis QS20
Example:  Medical Computer Tomography (CT) Scans Image whole heart in 1 rotation 4D CT –  includes time 2 slices 4 slices 8 slices 16 slices 32 slices 64  slices 128 slices 256  slices Current CT  Products   Future CT  Products
The moving image is aligned to the fixed image as the registration proceeds. Fixed Image Moving Image Registration Process “ Image Registration” Using Cell
6 Cell Programming
Small single-SPE models – a sample ,[object Object]
[object Object],Small single-SPE models – PPE controlling program
Using SPEs ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],PowerPC (PPE) SPU Local Store MFC N SPE Puts Results PPE Puts Text Static Data Parameters SPE executes PowerPC (PPE) SPU Local Store MFC N SPE Puts Results PPE Puts Initial Text Static Data Parameters System Memory SPE Independently Stages Text & Intermediate Data Transfers while executing
Using SPEs ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],SPU Local Store MFC N SPU Local Store MFC N Parallel-stages PowerPC (PPE) System Memory PowerPC (PPE) System Memory SPU Local Store MFC N SPU Local Store MFC N Multi-stage Pipeline  SPU Local Store MFC N
Large single-SPE programming models ,[object Object],[object Object],[object Object],SPE  Program System Memory PPE controller  maps system memory for  SPE DMA trans. DMA  transactions Local Store
Large single-SPE programming models – I/O data ,[object Object],[object Object],System memory int ip[32] int op[32] SPE program: op = func(ip) DMA DMA Local store int g_ip[512*1024] int g_op[512*1024]
Large single-SPE programming models ,[object Object],[object Object],[object Object],[object Object],[object Object],System memory SW cache entries SPE program Local store Global objects
Large single-SPE programming models ,[object Object],[object Object],[object Object],[object Object],[object Object],System memory Local store SPE plug-in b SPE plug-in a SPE plug-in e SPE plug-in a SPE plug-in b SPE plug-in c SPE plug-in d SPE plug-in e SPE plug-in f
Large single-SPE prog. models – Job Queue ,[object Object],[object Object],Job queue System memory Local store code/data n code/data n+1 code/data n+2 code/data … Code n Data n SPE kernel DMA
Large single-SPE programming models - DMA ,[object Object],[object Object],[object Object],Time I Buf 1 (n) O Buf 1 (n) I Buf 2 (n+1) O Buf 2 (n-1) SPE program: Func (n) output n-2 input n Output n-1 Func (input n ) Input n+1 Func (input n+1 ) Func (input n-1 ) output n Input n+2 DMAs SPE exec. DMAs SPE exec.
Large single-SPE programming models - CESOF ,[object Object],_EAR_g_foo structure Local Store Space Effective Address Space DMA  transactions CESOF EAR symbol resolution Char g_foo[512] Char local_foo[512]
Parallel programming models – Job Queue ,[object Object],[object Object],[object Object],[object Object],PPE SPE1 Kernel() SPE0 Kernel() SPE7 Kernel() System Memory I n . I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 O n . O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 0 … ..
Parallel programming models – Pipeline / Streaming ,[object Object],[object Object],[object Object],[object Object],PPE SPE1 Kernel 1 () SPE0 Kernel 0 () SPE7 Kernel 7 () System Memory I n . . I 6 I 5 I 4 I 3 I 2 I 1 I 0 O n . . O 6 O 5 O 4 O 3 O 2 O 1 O 0 … .. DMA DMA
Multi-tasking SPEs – LS resident multi-tasking ,[object Object],[object Object],[object Object],Task a Task b Task c Task d Task x Event Dispatcher Local Store SPE n Event Queue a c a d x a c d
Multi-tasking SPEs – Self-managed multi-tasking ,[object Object],[object Object],System memory Local store task n task n+1 task n+2 Task … Code n Data n SPE kernel task n’ task queue Job queue
libspe sample code ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
libspe sample code ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
libspe sample code ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Linux on Cell/B.E. kernel components ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
SPU file system ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
PPE on Cell is a 100% compliant ppc64! ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Using SPEs: Task Based Abstraction    APIs provided by user space libraries ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
spu_create ,[object Object],[object Object],[object Object],[object Object]
spu_run ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
PPE programming interfaces ,[object Object],[object Object],[object Object],[object Object],[object Object]
spe create thread implementation ,[object Object],[object Object],[object Object],[object Object]
More libspe interfaces ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
GNU tool chain ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Object file format ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
gcc on the PPE ,[object Object],[object Object],[object Object]
gcc on the SPE ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Existing proprietary applications ,[object Object],[object Object],[object Object],[object Object],[object Object]
Obviously missing ,[object Object],[object Object],[object Object],[object Object],[object Object]
Questions! Thank you very much for your attention.
7 Appendix
Documentation  (new or recently updated) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Documentation  (new or recently updated) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Links ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The Cell Processor

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The Cell Processor

  • 1. The Cell Processor Computing of tomorrow or yesterday? Open Systems Design and Development 2007-04-12 | Heiko J Schick <schickhj@de.ibm.com> © 2007 IBM Corporation
  • 2.
  • 4.
  • 5. The problem is… … the view from the computer room!
  • 6. Outlook Source: Kurzweil “ Computer performance increases since 100 years exponential !!!”
  • 7. But what could you do if all objects were intelligent… … and connected?
  • 8. What could you do with unlimited computing power… for pennies? Could you predict the path of a storm down to the square kilometer? Could you identify another 20% of proven oil reserves without drilling one hole?
  • 9. 2 Limiters to Processor Performance
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  • 21. SPE BLOCK DIAGRAM Permute Unit Load-Store Unit Floating-Point Unit Fixed-Point Unit Branch Unit Channel Unit Result Forwarding and Staging Register File Local Store (256kB) Single Port SRAM 128B Read 128B Write DMA Unit Instruction Issue Unit / Instruction Line Buffer 8 Byte/Cycle 16 Byte/Cycle 128 Byte/Cycle 64 Byte/Cycle On-Chip Coherent Bus
  • 22.
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  • 24. Example of eight concurrent transactions MIC SPE0 SPE2 SPE4 SPE6 BIF / IOIF1 Ramp 7 Controller Ramp 8 Controller Ramp 9 Controller Ramp 10 Controller Ramp 11 Controller Controller Ramp 0 Controller Ramp 1 Controller Ramp 2 Controller Ramp 3 Controller Ramp 4 Controller Ramp 5 Controller Ramp 6 Controller Ramp 7 Controller Ramp 8 Controller Ramp 9 Controller Ramp 10 Controller Ramp 11 Data Arbiter Ramp 7 Controller Ramp 8 Controller Ramp 9 Controller Ramp 10 Controller Ramp 11 Controller Controller Ramp 5 Controller Ramp 4 Controller Ramp 3 Controller Ramp 2 Controller Ramp 1 Controller Ramp 0 PPE SPE1 SPE3 SPE5 SPE7 IOIF1 PPE SPE1 SPE3 SPE5 SPE7 IOIF1 PPE SPE1 SPE3 SPE5 SPE7 IOIF1 MIC SPE0 SPE2 SPE4 SPE6 BIF / IOIF0 Ring1 Ring3 Ring0 Ring2 controls
  • 25.
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  • 30. QS20 Blade (w/o heatsinks)
  • 31.
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  • 33. Cell Software Stack Firmware Applications SLOF powerpc architecture dependent code Cell Broadband Engine Linux memory management device drivers gcc ppc64, spu backend glibc Hardware RTAS Secondary Boot Loader powerpc- and cell- specific Linux code Low-level FW scheduler (pSeries) (PMac) cell User space Linux common code device drivers
  • 34.
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  • 38. Peak GFLOPs FreeScale DC 1.5 GHz PPC 970 2.2 GHz AMD DC 2.2 GHz Intel SC 3.6 GHz Cell 3.0 GHz
  • 39.
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  • 42. Ported by 235 584 tetrahedra 48 000 nodes 28 iterations in NKMG solver In 3.8 seconds Sustained Performance for large Objects: 52 GFLOP/s Multigrid Finite Element Solver on Cell using the free SDK www.digitalmedics.de ls7-www.cs.uni-dortmund.de
  • 43. Computational Fluid Dynamics Solver on Cell Ported by Sustained Performance for large Objects: Not yet benchmarked (3/2007) using the free SDK www.digitalmedics.de ls7-www.cs.uni-dortmund.de
  • 44. Computational Fluid Dynamics Solver on Cell A Lattice-Boltzmann Solver Developed by Fraunhofer IWTM http://www.itwm.fraunhofer.de/
  • 45. Terrain Rendering Engine (TRE) and IBM Blades Systems and Technology Group Commodity Cell BE Blade Add Live Video, Aerial Information, Combat Situational Awareness Next-Gen GCS Combine Data & Render Aircraft data / Field Data BladeCenter-1 Chassis QS20
  • 46. Example: Medical Computer Tomography (CT) Scans Image whole heart in 1 rotation 4D CT – includes time 2 slices 4 slices 8 slices 16 slices 32 slices 64 slices 128 slices 256 slices Current CT Products Future CT Products
  • 47. The moving image is aligned to the fixed image as the registration proceeds. Fixed Image Moving Image Registration Process “ Image Registration” Using Cell
  • 49.
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  • 81.
  • 82. Questions! Thank you very much for your attention.
  • 84.
  • 85.
  • 86.

Notes de l'éditeur

  1. VMX AltiVec SIMD instructions on IBM PowerPC processors Less speculative logic
  2. VMX AltiVec SIMD instructions on IBM PowerPC processors Less speculative logic
  3. Switch gibt es noch nicht
  4. Dr. V. S. Pande, Distributed Computing Project, Stanford University (permission given for showing the video as well) Folding@Home on the PS3: the Cure@PS3 project INTRODUCTION Since 2000, Folding@Home (FAH) has led to a major jump in the capabilities of molecular simulation. By joining together hundreds of thousands of PCs throughout the world, calculations which were previously considered impossible have now become routine. FAH has targeted the study of of protein folding and protein folding disease, and numerous scientific advances have come from the project. Now in 2006, we are looking forward to another major advance in capabilities. This advance utilizes the new Cell processor in Sony’s PLAYSTATION 3 (PS3) to achieve performance previously only possible on supercomputers. With this new technology (as well as new advances with GPUs ), we will likely be able to attain performance on the 100 gigaflop scale per computer. With about 10,000 such machines, we would be able to achieve performance on the petaflop scale . With software from Sony, the PlayStation 3 will now be able to contribute to the Folding@Home project, pushing Folding@Home a major step forward. Our goal is to apply this new technology to push Folding@Home into a new level of capabilities, applying our simulations to further study of protein folding and related diseases, including Alzheimer’s Disease, Huntington&apos;s Disease, and certain forms of cancer. With these computational advances, coupled with new simulation methodologies to harness the new techniques, we will be able to address questions previously considered impossible to tackle computationally, and make even greater impacts on our knowledge of folding and folding related diseases. ADVANCED FEATURES FOR THE PS3 The PS3 client will also support some advanced visualization features. While the Cell microprocessor does most of the calculation processing of the simulation, the graphic chip of the PLAYSTATION 3 system (the RSX) displays the actual folding process in real-time using new technologies such as HDR and ISO surface rendering. It is possible to navigate the 3D space of the molecule using the interactive controller of the PS3, allowing us to look at the protein from different angles in real-time. For a preview of a prototype of the GUI for the PS3 client, check out a screenshot or one of these videos ( 355K avi , 866K avi , 6MB avi , 6MB avi -- more videos and formats to come). There is also a &amp;quot;bootleg&amp;quot; video of Sony&apos;s presentation on FAH that is now on YouTube (although the audio and video quality is pretty bad). http://fah-web.stanford.edu/cgi-bin/main.py?qtype=osstats
  5. Cell Blade systems compute and compress images. These images are then delivered via the network to clients for decompression and display. GPStream framework can be used to deliver the images to mobile clients via wireless. This is really an example of situational awareness. In this specific case, the Predator Unmanned Aerial Vehicle has a small camera mounted in the nose (blue circle would be live video), the surroundings would be rendered for the remote pilot to help them avoid turning into a mountain or no fly zone. We this this is also valid for commercial aircraft for night, poor weather, etc.
  6. Ein erfahrener Arzt kann aus Schnittbildern sehr viel herauslesen. Aber 3dimensionale Bilder, dynamisch, d.h. Unter Einschluß des Faktors Zeit eröffnen völlig neue Diagnosemöglichkeiten. Medical imaging is another area that is progressing rapidly and creating a new more demanding workload. Today an average exam generates 1GByte of data you can’t go to the future adding time dependent analysis without an application-optimized system. An average exam generates 1GBytes of data (for one Digital x-ray or simple CT scan - much more for complicated CT or MRI studies) We estimate that 10^2-10^4 floating point operations are used to capture, process and analyze a Byte of medical data So, a typical exam requires 10^11- 10^13 operations Assume an exam must be completed in “real time” (5 minutes?) to be of diagnostic use This requires 0.3- 33GF/s of compute power – delivered today by single processor Intel workstations Scanner technology will rapidly evolve to generate 10-20x the amount of data in the same scan time Sixteen Slice CT Scanner 600-2000 slices per exam  300 MB – 1 GB per exam CT Scan workflow – typical helical scan multi-slice acquisition Stage 1: Interpolate data to generate equivalent “step-and-shoot” slices Stage 2: Filtered Back-Projection to generate 2D slice view (Fourier filter + numerical integration) Stage 3: Volume rendering (optional—many radiologists prefer to look at slices, but with increasing resolution/slice count, it may become mandatory) Note (1) Stage 2 should be trivially parallelizable (scale out) Note (2) Increase in the number of slices acquired simultaneously  increased computational cost for “cone-effect” corrections. Note (3) There are claims that improved algorithms can reduce the computational burden enormously (UIUC Technology Licensing Office) Example: 313MB of raw scan data  5 x 1MB images (cross-sections?). Each image takes 19 seconds to process on a 3GHz Wintel box. High resolution 3000 slice run (from machines like the new Siemens Somatom 64) might take ~16 hours to process on such a commodity system. Note that the 3GB of 2D image data can be accommodated within main memory. PV-4D (www.pv-4d.com) Showcase at Supercomputing 2005 / Cebit 2006 About 4 times faster than Opteron with same algorithm If fully optimized, projected about &gt; 6 times faster than Opteron Last minute prototype running on four Cell blades Stereo display using shutter glasses, 8-10 frames per second - Achieving this frame rate using two blades at a time - Four blades required for data set size Data sets about 1.6GB in size - Beating heart (400x400x400 voxels, 6 samples) - CFD simulation (~600x200x100 voxels, 40 samples)
  7. Handling large data Handling large code SIMD aspect?
  8. Q: What’s the parameters to spe_create_thread…
  9. Handling large data Handling large code SIMD aspect?
  10. Handling large data Handling large code SIMD aspect?
  11. Middleware / libraries likely to be optimized - media, e.g., mplayer - encryption, e.g., OpenSSH PPE = P ower P rocessor E lement