S3 Group: Custom Mixed SIgnal SoCs

Custom Mixed-Signal SoC
Donnacha O‟Riordan

Silicon

© 2012 Silicon & Software Systems Ltd. All rights reserved. 05/07/2012

Agenda
• Drivers for Mixed-Signal

• Example applications

• An IP Provider Perspective

• Methodology Challenges

• Conclusion

© 2012 Silicon & Software Systems Ltd. All rights reserved. 05/07/2012 1

About Silicon BU
Global, Market leading provider of MSIP and professional services to
OEMs/System vendors and semiconductor companies worldwide, lowering
the risk in IC development and accelerating time to revenue of our customers

Silicon Highlights Value Proposition
• Satellite transceiver redesign • New Product Development
delivered an 85% BOM
• BOM Reduction
reduction
• Performance Leading Mixed
• Complete Turnkey service,
Signal IP Portfolio
delivering spec to packaged-
tested parts • Proven Team, Processes &
Methodologies over 25+
• World’s most advanced
years
independent ADC/DAC
company • Lower Risk and Faster TTM


Global Locations
OFFICES

SALES & SUPPORT

Eindhoven, The Netherlands
Dublin / Cork, Ireland
Wroclaw, Poland
Chicago, US New Jersey, US Beijing, China
Prague, Czech Republic
Lisbon, Portugal Shanghai
San Jose, US Kfar Saba, Israel

Hong Kong

Singapore


Comprehensive Capability
• From system architecture to detailed design

Team Communication
• Applications Experts
• System Architects
• RF Circuit Designers
• Analog / MS Designers
• Embedded SW
• DSP Engineers
• Digital FPGA/IC Designers
• Board / Validation Design


SoC Integration: Drivers
• BOM Cost Drives Integration
– Majority of consumer electronics ICs cost less than $3
– More connectivity options, higher data rates & richer applications

Integration


SoC Integration: Impact
• Analog and RF often on the same die as digital
– Camera, Display, DVD, connectivity etc. are Analog interfaces
– CMOS is becoming more suitable for RF


SoC Integration: Profitability
• BOM Cost reduction roadmap
– Single Chip RFIC – SiP – Dual IC
– CMOS is becoming more suitable for RF

RF SoC Roadmap
$30,000,000

$25,000,000

$20,000,000 SiP

$15,000,000
RF SoC
$10,000,000

$5,000,000

$-
0 500,000 1,000,0001,500,0002,000,0002,500,0003,000,000
Unit Volume


Power Reduction: Drivers
• No longer just an issue for portable devices
– Battery technology still lags for portable devices
– Mains powered applications have packaging & thermal issues
– „Green‟ marketing and regulations

Energy Usage - FOXTEL Standard STBs 1999-2007
25

20
Energy Use (Whr)

15

10

5
Standby mode (Watt) On mode (Watt)
0
1999 2000 Later 2001 2002 2003 2003 2003 2003 2006 2007
UEC UEC 2000 UEC UEC UEC UEC Pace Pa Pace Pace
600 700 UEC 720iF 720iX 1000 1000 420 420
ce 250 250
720F (sat) (cab) (sat) (cab) (sat) (cab)
Source: Don Brooks, NewsCorp consumer Technology Summit 2008


Power Reduction: Impact
• More complex power supply networks needed
– Digital SoCs with 40+ power domains and multiple supplies
– Power Management Integration increasing (cost/customisation)


Increasing Digital in Analog: Drivers
• Digital is looking very attractive
– Scaling: Increasing importance of power and area
– Porting: Many IDMs moving to fabless and fablite
– Resolution: Increasing signal processing content on SoC


Increasing Digital in Analog: Impact
• More Digital-infused „Analog‟ systems
– Digital compensation
– Digital error correction
– Digital calibration
– Digital RF (TI DRP etc)
– Over-sampling ADC
– Sigma-Delta data-converters etc
– Digitally Controlled DC-DC


The „Analog Shell‟
• More and more ICs have mixed-signal content
– 2007: 80% of TSMC ICs have 20% mixed-signal content
– 2010: 90% of TSMC ICs have 20% mixed-signal content

Source: Maria Marced, VP – TSMC Europe


Agenda




• Conclusion


Pipeline ADC IP Block
• Pipeline ADC 12bits @ 250Msps
– Embedded S/H to reduce power
– Digital background calibration
– Small block of Analog plus RTL based Digital

• Methodology
– Matlab system level optimisation
– RTL plus Spectre simulation
– Compare Matlab with Implementation

• Benefits
– Fast/thorough system optimisation
– Accurate circuit/RTL level checks


Content Addressable Memory IC
• 5Mb Content Addressable Memory IC
– Digital control and decoding etc
– Analog memory, sense amps etc
– Large Analog plus semi/full-custom Digital

• Methodology
– Used UltraSim for extracted simulation
– Varied accuracy depending on block type

• Benefits
– Very robust and accurate
– Able to generate .lib files very quickly
– Simulate large number of elements


Envelop Tracking Power IC
• Custom Analog and Standard Digital
– AFE containing all DACs and associated circuitry like BIAS block, POR
block, Clocking block, pads – custom design.
– Digital core – Standard digital logic block containing all digital blocks
functionality and digital pads.
– JESD204A data interface analog PHY block and pads – custom design

• Methodology
– Pre-harden Analog macros
– Mixed mode simulations
• Benefits
– Low risk in a complex development
– On-time, On-Budget


ISM Band Transceiver IC
• 2.4GHz Nanometer Transceiver
– RF, Analog, Digital and Processor SoC
– Very large, complex and varied IC

• Methodology
– Verilog-AMS plus Verilog plus ISS
– Re-used as schematic test harness
– Calibrated AMS models versus schematic

• Benefits
– Allowed use-case and connectivity analysis
– Architectural Digital / Analog control loop
– Saved NRE and Time-To-Market


Agenda




• Conclusion


Motivation for Mixed-Signal IP
• Lower costs, Reduced risk and Faster Time-To-Market
– IP usage spreads cost of development
– Analog / Mixed-Signal is more difficult in nanometer
– Re-use can reduce time-to-market by 50%

Source: Numetrics, “Achieving Maximum Reuse Leverage: Lessons from benchmarking 1000+ IC projects”


Consumer Technologies: Time-to-Market

Source: KPMG GSA Consumer Electronics Report 2008


Customer Expectations: Plug-And-Play IP

Robust Low Power
Proven in silicon Special modes
Good Isolation Run at 1.2V
Integration views Low quiescent

Cost Support
Area/Yield/Test Customize specs
No Analog opt. Integration
License/Royalty Validation


Agenda




• Conclusion


Accurate/Fast Full-Chip Analysis

Power Reduction
Architecture selection
HW-SW-MS Partitioning
Supply levels & islands


Analog Porting Automation
• Analog porting simply takes too much time
– Logic synthesis > 100x improvement, behavioural > 1000x
– Need significant speed-up of Analog porting
– Particularly important for layout issues at 40nm and below


Agenda




• Conclusion


Conclusion
• Mixed-Signal content in ICs is increasing
– Drivers are BOM Cost reduction & Process economics
– More integration, digital correction & power management
– Wireless transceivers, memory ICs, mixed-mode blocks

• Current state-of-the-art mixed-mode design
– Relies on co-simulation using FastSPICE and Verilog-AMS

• Improvement to maximize benefits
– Better fast architectural & power analysis
– Analog automation for porting etc


Questions?
info@s3group.com


S3 Group: Custom Mixed SIgnal SoCs

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