Dynamic clocked cmos

1. Dynamic and Pass-
Transistor Logic
Prof. Vojin G. Oklobdzija
References (used for creation of the presentation material):
1. Masaki, “Deep-Submicron CMOS Warms Up to High-Speed Logic”, IEEE
Circuits and Devices Magazine, November 1992.
2. Krambeck, C.M. Lee, H.S. Law, “High-Speed Compact Circuits with CMOS”,
IEEE Journal of Solid-State Circuits, Vol. SC-13, No 3, June 1982.
3. V.G. Oklobdzija, R.K. Montoye, “Design-Performance Trade-Offs in CMOS-
Domino Logic”, IEEE Journal of Solid-State Circuits, Vol. SC-21, No 2, April
1986.

2. References:
4. Goncalves, H.J. DeMan, “NORA: A Racefree Dynamic CMOS Technique
for Pipelined Logic Structures”, IEEE Journal of Solid-State Circuits,
Vol. SC-18, No 3, June 1983.
5. L.G. Heller, et al, “Cascode Voltage Switch Logic: A Differential CMOS
Logic Family”, in 1984 Digest of Technical Papers, IEEE International
Solid-State Circuits Conference, February 1984.
6. L.C.M.G. Pfennings, et al, “Differential Split-Level CMOS Logic for
Subnanosecond Speeds”, IEEE Journal of Solid-State Circuits, Vol. SC-
20, No 5, October 1985.
7. K.M. Chu, D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques:
Differential Cascode Voltage Switch Logic Versus Conventional Logic",
IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4, August 1987.
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 2

3. References:
Pass-Transistor Logic:
8. S. Whitaker, “Pass-transistor networks optimize n-MOS logic”,
Electronics, September 1983.
9. K. Yano, et al, “A 3.8-ns CMOS 16x16-b Multiplier Using
Complementary Pass-Transistor Logic”, IEEE Journal of Solid-State
Circuits, Vol. 25, No 2, April 1990.
10. K. Yano, et al, “Lean Integration: Achieving a Quantum Leap in
Performance and Cost of Logic LSIs", Proceedings of the Custom
Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
11. M. Suzuki, et al, “A 1.5ns 32b CMOS ALU in Double Pass-Transistor
Logic”, Journal of Solid-State Circuits, Vol. 28. No 11, November 1993.
12. N. Ohkubo, et al, “A 4.4-ns CMOS 54x54-b Multiplier Using Pass-
transistor Multiplexer”, Proceedings of the Custom Integrated Circuits
Conference, San Diego, California, May 1-4, 1994.
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 3

4. References:
13. V. G. Oklobdzija and B. Duchêne, “Pass-Transistor Dual Value Logic For
Low-Power CMOS,” Proceedings of the 1995 International Symposium on
VLSI Technology, Taipei, Taiwan, May 31-June 2nd, 1995.
14. F.S. Lai, W. Hwang, “Differential Cascode Voltage Switch with the Pass-
Gate (DCVSPG) Logic Tree for High Performance CMOS Digital
Systems”, Proceedings of the 1993 International Symposium on VLSI
Technology, Taipei, Taiwan, June 2-4, 1995
15. A. Parameswar, H. Hara, T. Sakurai, “A Swing Restored Pass-Transistor
Logic Based Multiply and Accumulate Circuit for Multimedia
Applications”, Proceedings of the Custom Integrated Circuits Conference,
San Diego, California, May 1-4, 1994.
16. T. Fuse, et al, “0.5V SOI CMOS Pass-Gate Logic”, Digest of Technical
Papers, 1996 IEEE International Solid-State Circuits Conference, San
Francisco February 8, 1996.
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 4

5. Dynamic CMOS Logic
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6. (a) Dynamic CMOS Latch (a), Dynamic CMOS
Master-Slave Latch (b)
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7. Dynamic Manchester Carry Chain
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8. Radiation induced charge
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9. Accidental charge caused by capacitive or inductive coupling between the signal
lines Y and Z. (a)
Prevention by inserting and inverter between the affected line and the pass-
transistor switch (b)
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10. CMOS Domino Logic
CMOS logic block (a), Domino Logic (b)
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11. CMOS Domino Logic
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12. CMOS Domino Logic Operation
0
1 1 1
1
0
1
0 1 1
0 1
1
0
Dominos
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13. CMOS Domino Logic: Charge Re-Distribution
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14. Variations of CMOS Domino Logic:
NORA Logic
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15. CVS and DCVS Logic
IBM
(Heller et al. 1984)
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16. Cascode Voltage Switch Logic CVS
IBM
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17. DCVS Logic (IBM)
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18. DCVS Logic (IBM)
(a) (b)
Differential Cascode Voltage Switch Logic:
(a) Static DCVLS (b) Dynamic DCVSL
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19. DCVS Logic vs CMOS
DCVS Logic consisting of two shared CMOS consisting of two separate:
nMOS transistor switching networks nMOS and pMOS transistor
switching networks
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20. Transistor sharing in DCVS Logic:
Implementation of 3-input XOR function
Q Q
A A A A
B B B B
C C
Q=a ⊕ b ⊕ c
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21. Switching Asymmetry in DCVSL
This asymmetry causes
current spikes and increased
power consumption !
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22. Pass-Transistor Logic
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23. Pass-Transistor Logic
(a) (b)
(a) XOR function implemented with pass-transistor
circuit, (b) Karnaough map showing derivation of the
XOR function
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24. Pass-Transistor Logic
General topology of pass-transistor
function generator
Karnaough map of 16 possible
functions that can be realized
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25. Pass-Transistor Logic
Function generator
implemented with pass-
transistor logic
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26. Pass-Transistor Logic
Threshold voltage drop at the Voltage drop does not exceed Vth
output of the pass-transistor when there are multiple
gate transistors in the path
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27. Pass-Transistor Logic
Elimination of the threshold voltage drop by:
(a) pairing nMOS transistor with a pMOS
(b) using a swing-restoring inverter
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28. Complementary Pass-Transistor Logic
(CPL)
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29. Basic logic functions in CPL
A B B A A B A A A A A B
B B
B B
A B B A A B
A B B A A C B C
B
C
B
C
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30. CPL Logic
A A
A A
B
n1 n2
B B
n3 n4
B
C
Q Qb C
S S (a) (b)
S S
XOR gate
Sum circuit
CPL provides an efficient implementation of XOR function
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31. CPL Inverter
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32. Double Pass-Transistor Logic (DPL):
VDD
A B B A
AND/NAND
A B
B B
A A
O
O
A B A B A B A B XOR/XNOR
B A
A B
A B
B A
A B
O
O
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33. Double Pass-Transistor Logic (DPL):
XOR
One bit full-adder:
Sum circuit
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34. Double Pass-Transistor Logic (DPL):
DPL Full Adder
The critical path traverses two
transistors only
(not counting the buffer)
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35. Formal Method for CPL Logic Derivation
Markovic et al. 2000
(a) Cover the Karnaugh-map with largest possible cubes
(overlapping allowed)
(b) Express the value of the function in each cube in terms of
input signals
(c) Assign one branch of transistor(s) to each of the cubes and
connect all the branches to one common node, which is the
output of NMOS pass-transistor network
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36. Formal Method for P-T Logic Derivation
Complementary function can be implemented from the same circuit
structure by applying complementarity principle:
Complementarity Principle: Using the same circuit topology, with
pass signals inverted, complementary logic function is constructed
in CPL.
By applying duality principle, a dual function is synthesized:
Duality Principle: Using the same circuit topology, with gate signals
inverted, dual logic function is constructed.
Following pairs of basic functions are dual:
AND-OR (and vice-versa)
NAND-NOR (and vice-versa)
XOR and XNOR are self-dual (dual to itself)
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37. Derivation of P-T Logic
A AND A NAND
B B
A OR A OR
B B
B B B
0 1 0 1 0 1
0 0 0 0 1 1 A 0 1 1
A 1 0 1 A 1 1 0 1 1 0
L 1 L 2 L 1 L 2 L 1 L 2
A B A B A B
L 2 L 1 L 2 L 1 L 1 L 2
B B B
B B B
AND NAND (OR) OR
Copmplementarity: AND  NAND; Duality: AND  OR
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38. Derivation of CPL Logic
Complementarity: AND  NAND
B
B
A 0 1 A B A B A B A B
L 2 L 1
0 0 0
B B
B B
A 1 0 1
L 1 L 2
AND NAND OR NOR
(a) (b) (c)
Duality: AND  OR
NAND  NOR
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39. Derivation of CPL Logic
B
B
A 0 1 A A A A
L 2 L 1
0 0 1
B
B
A 1 1 0
L 1 L 2
XOR XNOR
(a) (b)
(a) XOR function Karnaugh map, (b) XOR/XNOR circuit
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40. Synthesis of three-input CPL logic
A C B A C B
BC C L 1 L 2 L 3
A 00 01 11 10
A
L 1
0 0 0 0 0 A
B
L 2
A 1 0 0 1 0 B
L 3
B
AND NAND
(a) (b)
(a) AND function Karnaugh map, (b) AND/NAND circuit
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41. Double Pass-Transistor Logic (DPL):
Synthesis Rules
1. Two NMOS branches can not be overlapped covering logic 1s.
Similarly, two PMOS branches can not be overlapped covering logic
0s.
2. Pass signals are expressed in terms of input signals or supply.
Every input vector has to be covered with exactly two branches.
3. At any time, excluding transitions, exactly two transistor
branches are active (any of the pairs NMOS/PMOS, NMOS/NMOS
and PMOS/PMOS are possible), i.e. they both provide output current.
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42. Double Pass-Transistor Logic (DPL):
Synthesis Rules
Complementarity Principle: Complementary logic function in
DPL is generated after the following modifications:
• Exchange PMOS and NMOS devices. Invert all pass and gate
signals
Duality Principle: Dual logic function in DPL is generated
when:
• PMOS and NMOS devices are exchanged, and VDD and GND
signals are exchanged.
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43. DPL Synthesis:
B A B A
B
B L 4 L 2
A 0 1
L 3
A B A B
0 0 0
L 4 AND NAND
A 1 0 1 A B
A B
L 3 L 1
L 1 L 2
GND GND +V DD +V DD
(a) (b)
(a) AND function Karnaugh map (b) AND/NAND circuit
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44. DPL Synthesis: OR/NOR circuit
+V DD +V DD B A
A B A B
OR NOR
A B A B
B A GND GND
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45. DPL Synthesis:
B A B A
B Complementarity
B L 4 L 2
A 0 1 Principle:
L 3
A B A B Exchange PMOS
0 0 0 and NMOS
L 4 AND NAND
devices. Invert
A 1 0 1 A B
all pass and gate
A B
L 3 L 1
signals
L 1 L 2
AND  NAND
GND GND +V DD +V DD
(a) AND function Karnaugh map (b) AND/NAND circuit
+V DD +V DD B A Duality
Principle:
A B A B PMOS and
NMOS devices
OR NOR are exchanged,
and VDD and
A B A B
GND signals
are exchanged:
B A GND GND AND  OR
NAND  NOR
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