1. √
A 190MHz 4nV/ Hz Analog Baseband Chain of
Synthetic Aperture Radar (SAR) Receiver
Faizah Abu Bakar, Qaiser Nehal, Pekka Ukkonen, Ville Saari and Kari Halonen
Aalto University School of Science and Technology
Department of Micro and Nanosciences
P.0 Box 11000, FIN-00076 Aalto, Finland
Email: faizah@cc.hut.fi
Baseband chain Test out/in
Clock
Abstract— An analog baseband chain for a Synthetic Aperture Quadrature VGA LPF OBUF
mixer
Radar (SAR) receiver implemented in a 130nm CMOS technol- Data out I
ADC
ogy is presented in this paper. Occupying 0.23mm2 of silicon
area, the baseband chain consists of a three-stage Variable Gain Input buffer
Amplifier (VGA), a 5th-order gm-C Low Pass Filter (LPF) and an RFin LO
Bias &
0º control
Output Buffer (OBUF). The gain of the chain can be controlled
90º
by tuning the control voltages of the VGA and has a range from Test out/in
25dB to 34dB. In addition, the LPF has an 8dB gain to meet the VGA LPF OBUF
required dynamic range of the following block. The bandwidth of Data out Q
ADC
the LPF is programmable from 120MHz to 190MHz by means of
capacitor matrices. The chain, which uses a 1.2V supply voltage,
√ Clock
achieves 4nV/ Hz of input-referred noise density and -42dBV
in-band IIP3.
Fig. 1. SAR receiver.
I. I NTRODUCTION the anti-aliasing filtering before signal digitization. Since this
Because of insensitivity to weather conditions to process is a wideband LPF, the flatness of the magnitude response
images day and night, SAR is playing a major role in earth in the passband is crucial. The OBUF is designed to drive a
observation [1]. For a high resolution, wide swadth image, high-resolution analog-to-digital converter (ADC).
the receive antenna is comprised of multiple parallel con-
nected sub-apertures (i.e multiple individual receive cells). To III. C IRCUIT D ESCRIPTION
overcome the performance and reliability limitations as well
as to reduce the size and power consumption, it is advan- A. Variable Gain Amplifier
tageous to realize these receive cells with integrated circuits The VGA shown in Fig. 2, consists of three gain stages
(ICs). A wideband high-performance analog baseband chain VGA 1, VGA 2, VGA 3, and a DC offset correction network.
implemented in a 130nm CMOS technology for such a SAR The negative DC feedback network removes the DC offset
receive cell is described in this paper. The paper is organized as voltage originating from the RF front-end and the device mis-
follows. Section II describes the receiver architecture. Section matches in the VGA. The VGA should have 1GHz bandwidth
III presents the circuit design of VGA, LPF and OBUF. The over its entire gain tuning range. This ensures that the shape
measured performance of the circuit is reported in Section IV of the filter response is not affected by the VGA.
and conclusions are presented in Section V. The first gain stage shown in Fig. 3, is a fixed gain,
II. R ECEIVER A RCHITECTURE resistively loaded source coupled pair. It uses negative Miller
capacitors (NMC) (Cc1a and Cc1b ) to cancel the parasitic gate-
A SAR receiver under development employs a direct con- drain capacitances (Cgd1a and Cgd1b ) of M 1a and M 1b [2]. This
version architecture and consists of 1GHz VGA, a 190MHz reduces the input capacitance of the VGA and the capacitive
LPF and an OBUF as shown in Fig. 1. In a direct-conversion load of the mixer. Since the VGA stages are dc coupled to
receiver, the noise of the analog baseband circuit typically has each other, a common-mode feedback amplifier is used in each
a significant effect on the total noise figure of the receiver. stage to stabilize the output dc voltage of each stage against
Moreover, the baseband chain is required to have several dBs process,voltage and temperature (PVT) variations. Assuming
of gain owing to the moderate gain of the RF front-end. In this that NMC (Cc1a and Cc1b ) completely cancel the parasitic
design, the VGA is placed at the baseband input to provide gate-drain capacitances (Cgd1a and Cgd1b ) of M 1a and M 1b , the
most of the gain and, hence, to reduce the noise contribution voltage gain of VGA 1 can be written as
of the subsequent receiver blocks. The baseband circuit also
includes a DC-offset compensation circuit to overcome DC gm1a RD1a
Av (s) ≈ − , (1)
offset errors. The LPF following the VGA is needed to perform (sRg1 Cgs1a + 1)(sRD1a CL1 + 1)
978-1-4244-8971-8/10$26.00 c 2010 IEEE

2. VDD
VIN VGA 1 VGA 2 VGA 3 VOUT
RD2a RD2b
RF RCM1 RCM2
VCMFB
gmf Cc2a
RF Cc2b
CF CF
VOUT2
DC Offset Correction CL2 CL2
Realization of Rs Rg2 Rg2
Fig. 2. Block diagram of the fully differential three-stage VGA. Vgate M2a M2b
VDD VIN2+ VIN2-
RD1a RD1b Rs
Switchable Capacitor Matrix
RCM1 RCM2
VCMFB
Cc1a Cs
Cc1b
Cs1
VOUT1 Cf Cf
Cs2
CL1 CL1
Cs3 M6a M6b
Rg1 VCM
Rg1
VIN1+ VIN1- CMFB Amplifier
M1a M1b
Cf
Fig. 4. Schematic of the VGA stage 2 (or stage 3).
M5
VCM as
CMFB Amplifier
gm2a RD2a
Av (s) ≈ − . (7)
(1 + gm2a Rs )( ws + 1)( ws + 1)
2 p2 p3
Fig. 3. Schematic of the VGA stage 1.
The voltage gain of VGA 2 (or VGA 3) can be varied by
where Rg1 represents the output resistance of the preceding changing the value of Rs as can be seen from (7). Fig. 4
mixer and CL1 represents the equivalent load capacitance at shows that Rs can be implemented as a cascade connection of
the node VOUT 1 . transistors. Therefore the gate voltage Vgate of these transistors
The next two stages VGA 2 and VGA 3, are variable gain can be used to change the voltage gain. It must be noted that
degenerated differential pairs shown in Fig. 4. Here again changing the value of Rs also affects the pole-zero cancellation
NMC (Cc2a and Cc2b ) are used to reduce the input capacitance of wz1 and wp1 . Therefore the capacitor Cs is realized as
of these stages. The net result of using NMC is that the overall a Switchable Capacitor Matrix to ensure proper pole-zero
bandwidth of the VGA is 1GHz over the entire gain tuning cancellation.
range. Assuming that the NMC (Cc2a and Cc2b ) completely
cancel the parasitic gate-drain capacitances (Cgd2a and Cgd2b ) B. Low-Pass Filter
of M 2a and M 2b , the voltage gain of VGA 2 (or VGA 3) can The implemented low-pass filter is a 5th-order Chebyshev
be written as with a 0.3dB passband ripple. The passband-edge frequency of
gm2a RD2a ( ws + 1) the filter is programmable from 120MHz to 190MHz with 5-bit
Av (s) ≈ − z1
, binary-weighted switched-capacitor matrices. This wideband
(1 + gm2a Rs )( ws + 1)( ws + 1)( ws + 1)
2 p1 p2 p3 LPF is responsible for anti-aliasing filtering before the analog-
(2)
to-digital conversion.
where
The filter is realized as a continuous-time gm-C leapfrog
1 filter. It was synthesized using a lossy prototype as presented
wz1 = , (3)
Rs Cs in [3], and uses similar filter topology as in [4]. In this lossy
1 + (gm2a Rs /2) prototype gm-C based filter, the load resistance is removed
wp1 ≈ , (4) from the RLC prototype to minimize the loss of the last filter
Rg2 Cgs2a + Rs (Cs + (Cgs2a /2))
1 1 1 stage as in [3]. As opposite to [4], in this filter design, all
wp2 ≈ + + , (5) poles are realized using the leapfrog topology (Signal Flow
Rs Cs Rg2 Cgs2a 2Rg2 Cs
1 Graph method), resulting in a simpler structure as shown in
wp3 = . (6) Fig. 5.
RD2a CL2
The transconductor uses a pseudo-differential topology, as
In (4) and (5) Rg2 represents the source resistance of the depicted in Fig. 6. Since no internal poles are present, this
driving input source and in (6) CL2 represents the equivalent simple structure is suitable for a wideband filter. A common-
load capacitance at the node VOUT 2 . The zero wz1 resulting mode feedforward (CMFF) circuit is included to obtain in-
from the capacitive degeneration can be made to cancel the put common-mode rejection, and a common-mode feedback
pole wp1 . In this case the voltage gain of (2) can be rewritten (CMFB) circuit to fix the output common-mode voltage of

3. Vdd
Vin+ Vout+
Vin- k1gm gm gm gm gm Vout-
VCM VCM
gm gm gm gm gm
VCM
V_ERROR
Fig. 5. 5th-order gm-C low pass filter.
Fig. 7. Mirror-error compensation circuit.
OUTN OUTP INP INN
INP INN INP INN OUTN OUTP INP INN filter stages as derived from [4]:
V_ERROR
ADC
Q1,ef f = where k1 = 4 (8)
CMFF CMFB CMFF
ADC + 1 + k1
INP OUTP
gm
INN OUTN
The Q factor of the other filter stages is equal to the DC gain
gm
value of the transconductors.
Fig. 6. Transcconductor circuit. C. Output Buffer
The input capacitance of the ADC is in the same order
the transconductor. Since the approach used is to accept a low of magnitude (≈400 fF) with the load capacitor of the last
DC gain for the transconductors, all filter transconductors are filter stage. Therefore, the OBUF is needed after the LPF to
designed to have a 26dB nominal gain. drive the ADC. A single stage OBUF with balanced NMOS
One major issue with high frequency filter is the flatness of input transistor pair is designed as shown in Fig. 8. Instead of
the magnitude response throughout the passband. In this filter active loads, it has resistive loads to improve the linearity of
design, five factors are affecting the frequency response of the the whole baseband chain.
filter. The factors are: VDD
1. The accuracy of the DC gain of the transconductors. RL1 RL1
2. The accurate biasing of the transconductor which is manda- OUTN OUTP
tory for an accurate gm value.
VCM-control
3. The ron resistance of the switches used in the capacitor
matrices, affecting the Q factor of the capacitor matrices. INP MN1 INN
MN1
4. The parasitic capacitances in the filter.
5. The leakage of the NMOS switches.
The variations means of a transconductor’s gain as a result
of the PVT variation is controlled by negative resistance Fig. 8. Output buffer.
circuit. A test integrator with a negative resistance circuit is
implemented on a chip to measure the correct control voltage
for the negative resistance circuit. With this test structure, the IV. M EASUREMENT R ESULTS
exact value of the control voltage is obtained to get the desired The baseband chain was fabricated in a 130nm CMOS
26dB gain of the transconductors. process, and bonded directly to a 4-layer PCB. The circuit
There is always a systematic error in the PMOS current occupies 0.23mm2 of silicon area. Fig. 9 shows the measured
mirror. Since the transconductance of the pseudo-differential magnitude response of the chain at different gain settings.
transconductors depends on the input common-mode level, The imbalance between the I and Q paths is an important
accurate biasing is essential in this filter design. A mirror- parameter for the demodulation of the analog signal. I/Q
error compensation circuit which adds the common-mode error imbalance measurements have been obtained by the use of
with reverse polarity to the common-mode reference signal is mixed-mode S-parameters. The magnitude imbalance is less
designed as shown in Fig. 7. The common-mode level errors than ±0.4dB and the phase imbalance is ±5◦ in the passband,
in the transconductors are cancelled by feeding the reverse- as shown in Fig. 10. The imbalance increases near the corner
polarity common-mode reference signal to the V_ERROR gate frequency due to the slight difference in the passband-edge
at the CMFB circuit. frequency between both branches.
To provide an 8dB of gain, the first feedforward transcon- Simulated magnitude response of VGA is shown in Fig. 11.
ductor is scaled by 4. With this scaling, the effective Q factor It has more than 1GHz bandwidth with variable gain from
of the first filter stage is lower than the Q factor of the other 10dB to 30dB.

4. 35 Vgate = 0.60
40
Vgate = 0.628
Vgate = 0.65
35 30 Vgate = 0.679
Vgate = 0.713
Vgate = 0.768
30 25 Vgate = 0.885
25
Gain (dB)
20
Gain (dB)
20
15
15
10
10
5
5
0 6 7 8
0 6 7 8 9
10 10 10 10 10 10 10
Frequency (Hz) Frequency (Hz)
Fig. 9. Measured magnitude response with different gain setting. Fig. 11. Simulated magnitude response of VGA.
0.4
Magnitude IQ imbalance (dB) conversion SAR receiver. The baseband chain has a VGA to
0.2
supply most of the gain, a 5th-order gm-C as an anti-aliasing
dB
0
−0.2
filter and an OBUF to drive a high-resolution ADC. The filter
−0.4
corner frequency can be tuned from 120MHz to 190MHz using
8
10
switched-capacitor matrices. The achieved I and Q magnitude
10 Phase IQ imbalance (deg) and phase imbalance is good in the passband with less than
5 ±0.4dB in magnitude and within ±5◦ in phase. Low input-
√
degrees
0
referred noise density of 4nV/ Hz is also achieved.
−5
−10
8
10
Frequency (Hz)
Fig. 10. IQ imbalance.
√
Low input-referred noise density of 4nV/ Hz is achieved
as a result of low noise performance of the VGA. The
measured -42dBV in-band IIP3 is due to the high signal
swing at the input of LPF. The high input signal swing causes
the LPF to compress the signal at its output, resulting in a
Fig. 12. Baseband micrograph.
degraded IIP3 performance.
Table I summarizes the performance of the chain and ACKNOWLEDGMENT
compares it to other reported baseband chains.
This work is supported by the European Space Agency
TABLE I (ESA).
T HE B ASEBAND P ERFORMANCE S UMMARY
R EFERENCES
Reference This work [5] [6]
Process 130nm 90nm 180nm [1] P. Berens, “Introduction to synthetic aperture radar,” in Advanced Radar
Signal and Data Processing, Educational Notes RTO-EN-SET-086, 2006,
Supply voltage 1.2V 1.4V 1.8 pp. 3–1–3–14.
Filter Order 5 6 6 [2] Haines, G. and Mataya, J. and Marshall, S., “IF amplifier using Cc
Gain(dB) 25-34 13.5-67.5 10-55 compensated transistors,” in Solid-State Circuits Conference. Digest of
Passband edge 120MHz 10MHz and 264MHz Technical Papers. 1968 IEEE International, vol. XI, Feb. 1968.
[3] M. Kaltiokallio, S. Lindfors, V. Saari and J. Ryynanen, “Design of Precise
frequency to 190MHz 100MHz Gain Gm-C-leapfrog filters,” in Proc. IEEE International Symposium on
√ √
Input-referred 4nV/ Hz 19nV/ Hz - Circuits and Systems, 2007, pp. 3534–3537.
noise density (at nominal gain) (at high gain) [4] V. Saari, M. Kaltiokallio, S Lindfors, J.Ryynanen and K.A.I Halonen,
In band IIP3 -42dBV rms 2dBm - “A 240-MHz Low-Pass Filter With Variable Gain in 65-nm CMOS for
a UWB Radio Receiver,” IEEE Transactions on Circuits and Systems-I:
(at nominal gain) (at high gain) -
Regular Papers, vol. 56, no. 7, pp. 1488–1499, 2009.
Power (mW) 44a 13.5 - [5] Elmala, M., Carlton, B., Bishop, R. and Soumyanath, K., “A 1.4V,
Active silicon area 0.23 mm2 0.55 mm2 1.25 mm2 13.5mW, 10/100MHz 6th Order Elliptic Filter/VGA with DC-offset Cor-
a simulated, one channel baseband chain rection in 90nm CMOS [WLAN applications],” in IEEE Radio Frequency
Integrated Circuits (RFIC) Symposium, 2005, pp. 189–192.
[6] Jeongwook Koh, Hanseung Lee, Jung-Eun Lee, Choong-Yul Cha, Hyun-
V. C ONCLUSION Su Chae, Eun-Chul Park, Chun-Deok Suh, Hoon-Tae Kim, “Analog
Baseband Chain in a 0.18 um Standard Digital CMOS Technology for
An analog baseband chain with variable gain from 25dB- IEEE802.15.3a (UWB) Receiver ,” in IEEE Region 10 TENCON, 2005,
34dB is presented in this paper. The circuit is aimed at a direct- pp. 1–4.