Model-Driven Physical-Design for Future Nanoscale Architectures
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Model-Driven Physical-Design for Future Nanoscale Architectures
- 1. Model-Driven Physical-Design for Future Nanoscale Architectures Ciprian TEODOROV Lab-STICC MOCS November, 28th 2011
- 2. Thesis statement Generic physical-design framework based on a common vocabulary is the key to taming nanoscale architectures.
- 3. Context Society Needs • Smaller & denser circuits which consume much less power However • Current technology (CMOS) reaches its limits State of the art • Different architectural propositions based on emergent technologies Model-Driven Physical-Design for Future 3 Nanoscale Architectures
- 4. Examples Quantum • quantum-dot cellular automata Molecular • Tour’s Nanocell Crossbar • NanoPLA, CMOL, NASIC, FPNI Model-Driven Physical-Design for Future 4 Nanoscale Architectures
- 5. What is a Crossbar ? Crosspoint Different devices: • Diode • FET • Etc. Model-Driven Physical-Design for Future 5 Nanoscale Architectures
- 6. utilization and performance. 5N I Ah c rs . ACr ie u S ct t e Example: NASIC Large scale computing systems may be designed using the NASIC fabric and the associated framework of building blocks, xnwFET based circuits, and logic styles discussed in the preceding sections. This section discusses two key architectures for the NASIC fabric: the WISP- 0 general purpose processor and a massively parallel architectural framework with programmable templates for image processing. 5 .1 W te i grc s ( I P Ie ra nP eoW-) r S m os r S 0 WISP-0 is a stream processor that implements a 5-stage microprocessor pipeline architecture including fetch, decode, register file, execute and write back stages. WISP-0 consists of five nanotiles: Program Counter (PC), ROM, Decoder (DEC), Register File (RF) and Arithmetic Logic Unit (ALU). Figure 17 shows its layout. A nanotile is shown as a box surrounded by dashed lines in the figure. In WISP designs, in order to preserve the density advantages of nanodevices, data is streamed through the fabric with minimal control/feedback paths. All hazards Figure 17. WISP-0 Processor Floorplan are exposed to the compiler. It uses dynamic circuits and pipelining on the wires to eliminate the need for explicit flip-flops and therefore improve the density considerably. WISP-0 supports a simple instruction set including nop, mov, movi, add and multiply functions. It uses a 7-bit instruction format with 3-bit instruction and 2-bit source and destination addresses. The WISP-0 is used as a design prototype for evaluating key metrics such as area and performance as well as the impact of various fault- tolerance techniques on chip yield and process variation mitigation. Additional enhancements to this design are Figure 18. WISP-0 Program Counter ongoing in the NASIC group. Model-Driven Physical-Design for Future 6 5. . 1 W - Pgm ue 1 I P r r C nr S0 o a o t Nanoscale Architectures
- 7. Common Features of Crossbar Fabrics Nanowire based Regularity of assembly leads to: • a crossbar-like structure • PLA and/or FPGA-like fabric architecture CMOS superstructure, thus a nano-CMOS interface Large number of defects Logic implementation Model-Driven Physical-Design for Future 7 Nanoscale Architectures
- 8. Differences Between Crossbar Fabrics Architectural differences • Nano-role, CMOS-role • Fabrication strategy Physical parameters used for evaluation • CMOS/NW pitch / device characteristics Evaluation strategies • Yield simulation • Place & Route on predefined array Hypotheses during evaluation • Defect/Faults models Model-Driven Physical-Design for Future 8 Nanoscale Architectures
- 9. Research Questions How to maximize the reuse of design-tools? Is it possible to create a generic design toolkit? How to separate the algorithmic and architectural concerns? How to add a tools axis to design-space exploration problem? How to integrate multi-level fault tolerance? Model-Driven Physical-Design for Future 9 Nanoscale Architectures
- 10. Contributions Model-driven physical- R2D NASIC: Nanoscale design @ nanoscale architecture template Max-rate Common Tools as model Reified design DSE bootstrap pipeline vocabulary transformation flow methodology routing Model-Driven Physical-Design for Future 10 Nanoscale Architectures
- 11. Outline MoNaDe Toolkit • Overview • Structural Domain Modeling • Tool Modeling • Design flow Modeling R2D NASIC • Overview • Analytic evaluation • Characteristics R2D NASIC Evaluation Results • Surface / Performance • Max-rate pipeline evaluation • Room for improvements Conclusion & Perspectives Model-Driven Physical-Design for Future 11 Nanoscale Architectures
- 12. Outline MoNaDe Toolkit • Overview • Structural Domain Modeling • Tool Modeling • Design flow Modeling R2D NASIC • Overview • Analytic evaluation • Characteristics R2D NASIC Evaluation Results • Surface / Performance • Max-rate pipeline evaluation • Room for improvements Conclusion & Perspectives Model-Driven Physical-Design for Future 12 Nanoscale Architectures
- 13. System RTL Circuit Fabric Device Model-Driven Physical-Design for Future 13 Nanoscale Architectures
- 14. MoNaDe Toolkit Typical Defect/ Faults Application Packing Architecture Tools Placement UI Routing Metrics P&R Output Model-Driven Physical-Design for Future 14 Nanoscale Architectures
- 15. Structural Domain Modeling Common abstract model • Hierarchical annotated port graph • Specialized to model applications and architectures • Provides a common vocabulary (Entities and API) • Enables the creation of generic utilities Model-Driven Physical-Design for Future 15 Nanoscale Architectures
- 16. Hierarchical Annotated Port Graph Model-Driven Physical-Design for Future 16 Nanoscale Architectures
- 17. Structural Modeling: NASIC case Model-Driven Physical-Design for Future 17 Nanoscale Architectures
- 18. Model-Driven Physical-Design for Future 18 Nanoscale Architectures
- 19. Structural Modeling: NanoPLA Model-Driven Physical-Design for Future 19 Nanoscale Architectures
- 20. Tools as Transformations Decouple the algorithms from the domain models The tools are implemented as composite model-to- model transformations The tools refine the domain models Integration of external tools and algorithms Model-Driven Physical-Design for Future 20 Nanoscale Architectures
- 21. Transformation Meta-Model Model-Driven Physical-Design for Future 21 Nanoscale Architectures
- 22. Architectural Model Application Model Placed App Model RRGraph Extraction TGraph Extraction Nets Extraction RRGraph TGraph Nets add routes update costs add AT add RT Pathfinder Routes Post-routing FPGA Model Refinement Model-Driven Physical-Design for Future 22 Nanoscale Architectures
- 23. Tool-Flow Modeling Reified tool-flow as a composite transformation The physical-design tool-flow is a DAG of tools Capacity to create tool-flow derivations Enables incremental tool-flow creation Enables Architecture/Tools exploration Model-Driven Physical-Design for Future 23 Nanoscale Architectures
- 24. Tool-Flow Hierarchy Example NAbstractFlow VPRBasedFlow MadeoBasedFlow DirectPlaceRoute NCellBasedSynthesis NFlowBasedSynthesis VPRDirectPlaceAndRoute CompleteArrayDirectPR SimpleFSwitchPathEqualisationFlow LagrangianTimingDrivenFlow SimpleDirectedFSSwitchPathEqFlow LagrangianPathEqualisationFlow MAX-RATE SimpleDirectedAlongRoutePathEqFlow BASELINE DirectPlaceRouteDirectedConnections Model-Driven Physical-Design for Future 24 Nanoscale Architectures
- 25. Outline MoNaDe Toolkit • Overview • Structural Domain Modeling • Tool Modeling • Design flow Modeling R2D NASIC • Overview • Analytic evaluation • Characteristics R2D NASIC Evaluation Results • Surface / Performance • Max-rate pipeline evaluation • Room for improvements Conclusion & Perspectives Model-Driven Physical-Design for Future 25 Nanoscale Architectures
- 26. NASIC 2D Routing Problem Model-Driven Physical-Design for Future 26 Nanoscale Architectures
- 27. Model-Driven Physical-Design for Future 27 Nanoscale Architectures
- 28. R2D NASIC – Routing & Timing Model-Driven Physical-Design for Future 28 Nanoscale Architectures
- 29. Results – NW Length Model-Driven Physical-Design for Future 29 Nanoscale Architectures
- 30. Performance vs Input width 1,80E+09 1,60E+09 1,40E+09 1,20E+09 Frequency (Hz) 1,00E+09 8,00E+08 6,00E+08 4,00E+08 2,00E+08 0,00E+00 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 # of inputs Model-Driven Physical-Design for Future 30 Nanoscale Architectures
- 31. R2D NASIC – Main Characteristics Compatibility with NASIC technology and fabrication Adaptability to technological and applicative constraints Compatibility with NASIC fault-tolerance techniques Custom placement and routing due to structural regularity Max-rate pipeline designs due to pipelined routing architecture Simplified delay estimation Model-Driven Physical-Design for Future 31 Nanoscale Architectures
- 32. Outline MoNaDe Toolkit • Overview • Structural Domain Modeling • Tool Modeling • Design flow Modeling R2D NASIC • Overview • Analytic evaluation • Characteristics R2D NASIC Evaluation Results • Surface / Performance • Max-rate pipeline evaluation • Room for improvements Conclusion & Perspectives Model-Driven Physical-Design for Future 32 Nanoscale Architectures
- 33. R2D NASIC MoNaDe Toolflow Application SIS PLA Explore UI Architecture Tools PLAMap Placement UI Routing Metrics P&R Output Model-Driven Physical-Design for Future 33 Nanoscale Architectures
- 34. Normalized Density Gain over 45nm BASELINE standard cell 100 48X 24X 17X 12X 10 9X 2X 1.32X 1 alu4 apex2 apex4 des ex5p misex3 seq Model-Driven Physical-Design for Future 34 Nanoscale Architectures
- 35. Speed BASELINE Operating frequency of the slowest logic stage / throughput 1000 Too slow 167MHz 100 67MHz Frequency 43MHz 40MHz 29MHz 27MHz 10 9MHz 1 alu4 apex2 apex4 des ex5p misex3 seq Results assume 1GHz for the slowest logic stage Model-Driven Physical-Design for Future 35 Nanoscale Architectures
- 36. Max-Rate Pipeline System Add REs Model-Driven Physical-Design for Future 36 Nanoscale Architectures
- 37. Model-Driven Physical-Design for Future 37 Nanoscale Architectures
- 38. R2D NASIC MoNaDe Toolflow Application SIS PLA Explore UI Architecture Tools PLAMap Placement UI Routing Max-Rate Router Metrics P&R Output Model-Driven Physical-Design for Future 38 Nanoscale Architectures
- 39. Net Performance Improvement MAX-RATE Model-Driven Physical-Design for Future 39 Nanoscale Architectures
- 40. Normalized Density Gain over 45nm standard cell MAX-RATE 48X 24X 17X 12X 13X 12X 9X 10 3X 2X 1.32X 1.24X 1 0.46X 0.1 0.06X 0.03X 0.01 Baseline Max-Rate alu4 apex2 apex4 des ex5p misex3 seq Model-Driven Physical-Design for Future 40 Nanoscale Architectures
- 41. Performance*Area Gain MAX-RATE 1000 274X 100 66X 61X 40X 14X 10 5X 1 alu4 apex2 apex4 des ex5p misex3 seq 0.32X 0.1 Model-Driven Physical-Design for Future 41 Nanoscale Architectures
- 42. Room for Improvement: STDEV of Routing Block Usage MAX-RATE Model-Driven Physical-Design for Future 42 Nanoscale Architectures
- 43. Outline MoNaDe Toolkit • Overview • Structural Domain Modeling • Tool Modeling • Design flow Modeling R2D NASIC • Overview • Analytic evaluation • Characteristics R2D NASIC Evaluation Results • Surface / Performance • Max-rate pipeline evaluation • Room for improvements Conclusion & Perspectives Model-Driven Physical-Design for Future 43 Nanoscale Architectures
- 44. Conclusions Generic physical-design toolkit for nanoscale crossbar fabrics • Model-driven approach: structure, algorithmics, and flow reified. • Two main abstraction levels considered • Quantitative incremental DSE, bootstrapped with standard tools + new exploration axis Nanoscale architecture template • Enables arbitrary routing for NASIC • Shows the impact of pipelined (dynamic logic) routing Model-Driven Physical-Design for Future 44 Nanoscale Architectures
- 45. Future Research MoNaDe toolkit • Formalize the models and the API • Hardware accelerated physical-design using external transformations • Create an optimizing tool-flow execution engine • Open infrastructure for architectural exploration in the context of new technologies Nanoscale architectures @ techno level • Fault tolerance for dynamic routing • Parameter variability impact on multi-tile design • Clock distribution in highly constrained 2D topologies Nanoscale architecture @ design level • Creation and/or improvement of pipeline aware tools (placement, routing, etc) • Study the extent to which dynamic logic evaluation impacts the physical design for other architectures besides R2D NASIC Model-Driven Physical-Design for Future 45 Nanoscale Architectures
- 46. Model-Driven Physical-Design for Future 46 Nanoscale Architectures
- 47. Configuration Management Configuration types: • Structural • Fine-grain functional • Coarse-grain functional Configuration state-machine reified in the model Different configuration policies • One-time configuration • Reconfiguration Model-Driven Physical-Design for Future 47 Nanoscale Architectures
- 48. Fault-Modeling and Injection Domain concepts specialized to faulty entities • FET -> StuckAt0FET and StuckAt1FET Two ways to inject faults: • Object swapping: injects faulty devices by replacing model instances • Fault-configuration: uses a probabilistic configuration controller Model-Driven Physical-Design for Future 48 Nanoscale Architectures
- 49. Fault-Modeling and Injection - Details NFET StuckAt1 60% NFET 10% StuckAt1 NULL 30% 30% NULL StuckAt0 StuckAt0 Model-Driven Physical-Design for Future 49 Nanoscale Architectures
Notes de l'éditeur
- Physical, Material, Power-Thermal, Technological, Economical
- Physical, Material, Power-Thermal, Technological, Economical
- 16X average
- 54MHz average
- 36X better on average
- 4X better than CMOS