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UNIT - I
The 8085 Microprocessor



         Prepared By,
Mr.R-THANDAIAH PRABU M.E.,
        Lecturer - ECE
     thandaiah@gmail.com
RE
                                           TU
                5 CH
              08 R AR              IT EC
             8 O
                   SS               TI ON
              CE         &        RA
         P RO                GU
    RO                    FI
MIC                C   ON
            PI   N
The 8085 and Its Busses
•   The 8085 is an 8-bit general purpose microprocessor that can
    address 216 =64K Byte of memory.
•   It has 40 pins and uses +5V for power. It can run at a maximum
    frequency of 3 MHz.
     – The pins on the chip can be grouped into 6 groups:
          • Address Bus.
          • Data Bus.
          • Control and Status Signals.
          • Power supply and frequency.
          • Externally Initiated Signals.
          • Serial I/O ports.

                             SJCET
Intel 8085 Pin Configuration




             SJCET
8085 MICROPROCESSOR
Functional Blocks
•   Registers                • Increment/ Decrement
•   ALU                        Address Latch
•   Instruction Decoder      • Interrupt Control
•   Address Buffer           • Serial I/O Control
•   Address/Data Buffer      • Timing and control
                               circuitry



                     SJCET
Registers

           • General purpose
             Registers
           • Temporary Registers
           • Special Purpose
             Register
           • 16 Bit Registers



   SJCET
The Flags register
                 – There is also the flags register whose bits are affected by the arithmetic &
                   logic operations.
                     • S-sign flag
                           – The sign flag is set if bit D7 of the accumulator is set after an
                             arithmetic or logic operation.
                  CY       – 0- + Ve        1- -Ve
                     • Z-zero flag
             P



                           – Set if the result of the ALU operation is 0. Otherwise is reset. This
                             flag is affected by operations on the accumulator as well as other
        AC




                             registers. (DCR B).
                     • AC-Auxiliary Carry
    Z




                           – This flag is set when a carry is generated from bit D3 and passed
                             to D4 . This flag is used only internally for BCD operations.
S




                     • P-Parity flag
                           – After an ALU operation if the result has an even no of 1’s the p-
                             flag is set. Otherwise it is cleared. So, the flag can be used to
                             indicate even parity.
                     • CY-carry flag
                           – CY = carry is set when result generates a carry. Also a borrow
                             flag.
                                           SJCET
PROGRAM COUNTER (PC) AND STACK
         POINTER (SP)
• These are two 16-bit registers used to hold memory
  addresses.
• PC:
   – The function of the PC is to point to the memory address from
     which the next byte is to be fetched.
   – When a byte (machine code) is being fetched, the program counter
     is incremented by one to point to the next memory location.
• SP:
   – It points to a memory location in R/W memory, called the stack.
   – The beginning of the stack is defined by loading a 16-bit address in
     the stack pointer.
   – The PC will automatically update when calling to /returning from
     Subroutines.
The ALU
• In addition to the arithmetic & logic circuits, the ALU
  includes the accumulator, which is part of every
  arithmetic & logic operation.

• Also, the ALU includes a temporary register used for
  holding data temporarily during the execution of the
  operation. This temporary register is not accessible by
  the programmer.



                        SJCET
The Address and Data Busses
•   The address bus has 8 signal lines A8 – A15 which are
    unidirectional.
•   The other 8 address bits are multiplexed (time shared) with the 8
    data bits.
     – So, the bits AD0 – AD7 are bi-directional and serve as A0 –
        A7 and D0 – D7 at the same time.
          • During the execution of the instruction, these lines carry
            the address bits during the early part, then during the
            late parts of the execution, they carry the 8 data bits.
     – In order to separate the address from the data, we can use a
        latch to save the value before the function of the bits
        changes.

                              SJCET
INCREMENT/ DECREMENT ADDRESS LATCH
              Interrupt Control:
           Fetch, Decode & execute
  RST 5.5, RST 6.5, RST 7.5, TRAP, & INTR

             Serial I/O Control
                SOD & SID

          Timing and Control Circuitry
    Its control fetching, decoding, execution


                     SJCET
Frequency Control Signals
•   There are 3 important pins in the frequency control group.
     – X0 and X1 are the inputs from the crystal or clock
       generating circuit.
         • The frequency is internally divided by 2.
             – So, to run the microprocessor at 3 MHz, a clock
                running at 6 MHz should be connected to the X0
                and X1 pins.

     – CLK (OUT): An output clock pin to drive the clock of the
       rest of the system.

•   We will discuss the rest of the control signals as we get to them.
                               SJCET
The Control and Status Signals
 • There are 4 main control and status signals. These are:
        • ALE: Address Latch Enable. This signal is a pulse that
          become 1 when the AD0 – AD7 lines have an address on
          them. It becomes 0 after that. This signal can be used to
          enable a latch to save the address bits from the AD lines.
        • RD: Read. Active low indicates that the data must be
          read from the selected memory location or I/O port via
          data bus.
        • WR: Write. Active low indicates that the data must be
          written into the selected memory location or I/O port via
          data bus..
        • IO/M: This signal specifies whether the operation is a
          memory operation (IO/M=0) or an I/O operation
          (IO/M=1).
        • S1 and S0 : Status signals to specify the kind of
          operation being performed .Usually un-used in small
          systems.          SJCET
GE
                  UA
              N G
             A M
            L A
          LY GR
         B O
        M R
    S SE P
A

         SJCET
ADDRESSING MODES
• IMMEDIATE
     MVI A,05(H) LXI H,0050(H)
• DIRECT
      LDA 0208(H)
• REGISTER
     MOV B,C           ADD B
• REGISTER INDIRECT
     LDAX B
• INHERENT
     HLT          STC(SET CARRY FLAG)

                   SJCET
NOTATIONS                MEANING


    M       Memory location pointed by HL reg pair


    r                    8- bit register


    rp                  16-bit register


    rs                  Source register


    rd                Destination register


   addr                 16-bit address



              SJCET
Data Transfer Group
•   MVI r, data (8- Bit)
•   MVI M, data (8- Bit)
•   MOV rd, rs
•   MOV M, rs
•   MOV rd, M
•   LXI rp, data (16 bit)
•   STA addr
•   LDA addr
•   SHLD addr
•   LHLD addr
•   STAX addr
•   LDAX rp
•   XCHG
                            SJCET
•   MOV Rd,Rs              MOV B,C
•   MVI R,8bit             MVI A,05H
•   LXI Rp,16bit           LXI B,2050
•   MOV R,M                MOV D,M
•   MOV M,R                MOV M,E
•   LDA 16 bit             LDA 8005H
•   STA 16 bit             STA 8006H
•   LDAx Rp                LDAx B
•   STAX Rp                STAX D
                   SJCET
ARITHEMATIC GROUP
•   ADD r          •   SUB r      •   INR r
•   ADD M          •   SUB M      •   INR M
•   ADI data (8)   •   SUI data   •   INX rp
•   ADC r          •   SBB r      •   DCR r
•   ADC M          •   SBB M      •   DCR M
•   ACI data (8)   •   SBI data   •   DCX rp
•   DAD rp         •   DAA

                        SJCET
•   ADD R              ADD B
•   ADI 8bit           ADI 59H
•   SUB R               SUB C
•   SUI 8bit           SUI 37H
•   INR R              INR D
•   DCR R              DCR B
•   INR M              INR M
•   DCR M              DCRB M
•   INX Rp             INX B
•   DCX Rp     SJCET
LOGIC GROUP
•   ANA r              •   ORI data
•   ANA M              •   CMP r
•   ANI data           •   CMP M
•   XRA r              •   CPI data
•   XRA M              •   STC
•   XRI data           •   CMC
•   ORA r              •   CMA
•   ORA M
               SJCET
•   ANA R/M            ANA D
•   ANI 8bit
•   ORA R/M            ORA C
•   ORI 8bit
•   XRA R/M            XRA D
•   XRI 8bit
•   RLC
•   RAL
•   RRC
•   RAR
•   CMP R/M    SJCET
BRANCH GROUP
• JUMP
  INSTRUCTION
• CALL and
  RETURN
  INSTRUCTION
• RESTART
  INSTRUCTION


                SJCET
•   JMP 16bit Address
•   JZ 16bit Address
•   JNZ 16bit Address
•   JC 16bit Address
•   JNC 16bit Address

• HLT       Stop processing and wait
• NOP       Don’t perform anything - delay


                   SJCET
STACK OPERATION I/O &
    CONTROL GROUP
• PUSH
• POP
• RESTART
  RST n




            SJCET
INSTRUCTION FORMATS

 1 BYTE INSTRUCTION      2 BYTE INSTRUCTION   3 BYTE INSTRUCTION




                                                     JMP 6200H ---
MOV A,B --- 78H       MVI B, 02 --- 06H 02
                                                       C3H 00 62




                                SJCET
INSTRUCTION SET




     SJCET
INSTUCTION SET




                                       MODIFICATION              CONTROL
                 MOVEMENT
                                       INSTUCTIONS             INSTRUCTIONS
                INSTUCTIONS




      GROUP-0          GROUP – 1         GROUP – 2                    GROUP – 3B I/O &
       DATA              DATA           ARITHEMATI     GROUP -3A      MACHINE
     TRANSFER          TRANSFER          C & LOGIC      BRANCH        CONTROL




MVI,INR,DCR,LDA,                                      JNZ,JNC,JC,      HLT,ENABLE
                                     AND,ADD,
 STA,RAR,CMC,                                           JZ etc.,        ,DISABLE,
 CMA,STC,DAA,           MOV           OR,XOR
                                       etc.,          PROGRAM              INTR
DAD,LDAX,SHLD,                                        CONTROL           PROCESS
 INX,RIM ETC.,                                                          CONTROL

                                       SJCET
BYTE ORGANIZATION
                     GROUP - 0

0       0       R         R        R        I0    I0    I0

                         GROUP - 1

0       1       R         R        R        S     S     S

                         GROUP - 2

1       0       A1        A1       A1       S     S     S

                         GROUP - 3

    1       1       Cb        Cb       Cb    B0    B0    B0
                          SJCET
CODE FOR RECEIVING AND SENDING
               REGISTERS/PAIRS

RESSISTERS   AADDRESS CODE      RESSISTERS   ADDRESS CODE

    B             000              B–C            00
    C             001
    D             010              D–E            01
    E             011
    H             100              H–L            10
    L             101
    M             110               SP            11
    A             111




                        SJCET
INFORMATION OPERATIONS (I0 I0 I0)

     ADDRESS                      OPERATION
I0     I0      I0
0      0       0                   NOT USED
0      0       1      IMMETIATE OPERATION REGISTER PAIR
0      1       0                 LOAD / STORE
0      1       1     INCREMENT/ DECREMENT REGISTER PAIR
1      0       0          INCREMENT SINGLE REGISTER
1      0       1          DECREMENT SINGLE REGISTER
1      1       0    IMMETIATE OPERATION ON SINGLE REGISTER
1      1       1               REGISTER SHIFTING


                       SJCET
ARITHEMATIC AND LOGICAL OPERATIONS (A1 A1 A1)


     ADDRESS                     OPERATION
A1     A1      A1
0      0       0                    ADD
0      0       1            ADD WITH CARRY (ADC)
0      1       0               SUBTRACT (SUB)
0      1       1       SUBTRACT WITH BORROW (SBB)
1      0       0                LOGICAL AND
1      0       1             EXCLUSIVE OR (X-OR)
1      1       0               LOGICAL OR (OR)
1      1       1                  COMPARE



                    SJCET
CONDITIONS OF BRANCH ( Cb Cb Cb)


     ADDRESS                    OPERATION
Cb     Cb      Cb
0      0       0              IF NOT ZERO (JNZ)
0      0       1                IF ZERO (JZ)
0      1       0              IF NO CARRY(JNC)
0      1       1                IF CARRY (JC)
1      0       0             IF ODD PARITY (JPO)
1      0       1            IF EVEN PARITY (JPE)
1      1       0            WAS IT POSITIVE (JP)
1      1       1            WAS IT NEGATIVE (JM)


                    SJCET
BRANCH OPERATIONS (B0 B0 B0)


     ADDRESS                     OPERATION
B0     B0      B0
0      0       0             CONDITIONAL RETURN
0      0       1                SIMPLE RETURN
0      1       0              CONDITIONAL JUMP
0      1       1             UNCONDITIONAL JUMP
1      0       0              CONDITIONAL CALL
1      0       1                 SIMPLE CALL
1      1       0            SPECIAL A/L OPERATIONS
1      1       1     SPECIAL UNCONDITIONAL JUMPS


                    SJCET
MVI B, BYTE
0       0       R         R        R        I0      I0      I0

    0       0       0        0         0        1       1       0

                         MOV B,C

0       1       R        R         R        S       S       S

0       1       0         0        0        0       0       1


                             ADD B

    1       0       A1        A1       A1   S           S       S

    1       0       0        0         0        0       0       0
                          SJCET
Static RAM                               Dynamic RAM
Static RAM contains less memory cells Dynamic RAM contains more memory
per unit area                         cells as compare to static RAM per unit
                                      area
It has less access time, hence faster    Its access time is greater than static
memories                                 RAMs
Static RAM consists of number of flip-   Dynamic RAM stores the data as a
flops. Each flip-flop stores one bit     charge on the capacitor. It consists of
                                         MOSFET and the capacitor for each
                                         cell
Refreshing circuitry is not required     Refreshing circuitry is required to
                                         maintain the charge on the capacitor
                                         after every few milliseconds
Cost is more                             Cost is less




   SJCET
MACHINE CYCLES AND THEIR
     TIMING OF 8085:
 Timing Diagram is a graphical representation. It represents the execution
    time taken by each instruction in a graphical format. The execution time
    is represented in T-states.

 Instruction Cycle:
 The time required to execute an instruction is called instruction cycle.

 Machine Cycle:
    The time required to access the memory or input/output devices is called
   machine cycle.

 T-State:
 The machine cycle and instruction cycle takes multiple clock periods.
 A portion of an operation carried out in one system clock period is called as
    T-state.
• Clock Signal
The 8085 divides the clock frequency provided at x1 and x2 inputs
   by 2 which is called operating frequency.

                                             Rise time and fall time




      T-State
      1 Clock cycle




                             SJCET
• Single Signal
Single signal status is represented by a line. It may have status either
   logic 0 or logic 1 or tri-state



              Logic 1
                                 Tri state
Logic 0




                               SJCET
• Group of signals

Group of signals is also called a bus.
Eg: Address bus, data bus




                Valid state


             State changes
             State changes               Tri state
                                         Tri state




                          SJCET
SJCET
Instruction cycle
                            Instruction cycle



   Machine cycle1
   Machine cycle1     Machine cycle 2
                      Machine cycle 2           Machine cycle 5
                                                Machine cycle 5




T – State 1 T – State 2 T – State 3
T – State 1 T – State 2 T – State 3               T – State 6
                                                  T – State 6



                              SJCET
The 8085 microprocessor has 5 basic machine
             cycles. They are


   1.Opcode fetch cycle (4T)
   2.Memory write cycle (3 T)
   3.I/O read cycle (3 T)
   4.Memory read cycle (3 T)
   5.I/O write cycle (3 T)
•   Each instruction of the 8085 processor consists of one to five
    machine cycles, i.e., when the 8085 processor executes an
    instruction, it will execute some of the machine cycles in a
    specific order.

•   The processor takes a definite time to execute the machine cycles.
    The time taken by the processor to execute a machine cycle is
    expressed in T-states.

•   One T-state is equal to the time period of the internal clock signal
    of the processor.

•   The T-state starts at the falling edge of a clock.

•   In this time, the first, 3 T-states are used for fetching the opcode
    from memory and the remaining T-states are used for internal
    operations by the processor.
Opcode Fetch Machine Cycle
• The first step of executing any instruction is the Opcode fetch
  cycle.
   – In this cycle, the microprocessor brings in the instruction’s
      Opcode from memory.
        • To differentiate this machine cycle from the very similar
          “memory read” cycle, the control & status signals are set
          as follows:
             – IO/M=0, s0 and s1 are both 1.
   – This machine cycle has four T-states.
        • The 8085 uses the first 3 T-states to fetch the opcode.
        • T4 is used to decode and execute it.
   – It is also possible for an instruction to have 6 T-states in an
      opcode fetch machine cycle.

                           SJCET
Timing Diagram for Opcode Fetch Machine Cycle

              SJCET
Memory Read Machine Cycle of 8085:

• The memory read machine cycle is executed by the
  processor to read a data byte from memory.

• The processor takes 3T states to execute this cycle.

• The instructions which have more than one byte word
  size will use the machine cycle after the opcode fetch
  machine cycle.




                         SJCET
Memory Read Machine Cycle
• The memory read machine cycle is
  exactly the same as the opcode fetch
  except:
  – It only has 3 T-states
  – The s0 signal is set to 0 instead.




                     SJCET
The Memory Read Machine Cycle
  – To understand the memory read machine cycle, let’s study the
    execution of the following instruction:
     • MVI A, 32
  – In memory, this instruction looks like:
     • The first byte 3EH represents the opcode for loading a byte
       into the accumulator (MVI A), the second byte is the data to
       be loaded.
  – The 8085 needs to read these two bytes from memory before it
    can execute the instruction. Therefore, it will need at least two
    machine cycles.
        – The first machine cycle is the opcode fetch discussed
           earlier.
        – The second machine cycle is the Memory Read Cycle.
                                                     2000H   3E

                                                     2001H   32


                            SJCET
Timing Diagram for Memory Read Machine Cycle
                  SJCET
Memory Write Machine Cycle of 8085:

• The memory write machine cycle is executed by the
  processor to write a data byte in a memory location.

• The processor takes, 3T states to execute this machine
  cycle.




                        SJCET
The Memory Write Operation
• In a memory write operation:
  – The 8085 places the address (2065H) on the
    address bus
  – Identifies the operation as a memory write
    (IO/M=0, s1=0, s0=1).
  – Places the contents of the accumulator on the
    data bus and asserts the signal WR.
  – During the last T-state, the contents of the data
    bus are saved into the memory location.


                      SJCET
Timing Diagram for Memory Write Machine Cycle


             SJCET
SJCET
INTERFACING I/O AND PERIPHERAL
               DEVICES:

1. For data transfer from input device to processor
   the following operations are performed.

•    The input device will load the data to the port.

•    When the port receives a data, it sends message to
     the processor to read the data.

•    The processor will read the data from the port.

•    After a data have been read by the processor the
     input device will load the next data into the port.



                          SJCET
2. For data transfer from processor to output device the following
operations are performed.

•The processor will load the data to the port.

•The port will send a message to the output device to read the data.

•The output device will read the data from the port.

•After the data have been read by the output device the processor can load
the next data to the port.

•The various INTEL 110 port devices are 8212, 8155/8156, 8255, 8355
and 8755.

•8212

•The 8212 is a 24 pin IC.
•It consists of eight number of D-type latches.
•It has 8-input lines DI1 to DI8 and 8-output lines DO1 to DO8
•The 8212 can be used as an input or output device
•It has two selecting device DS1 (low) and DS2.

                              SJCET
SJCET
SJCET
Dimensions of Memory
   • Memory is usually measured by two numbers: its length
     and its width (Length X Width).
           » The length is the total number of locations.
           » The width is the number of bits in each location.
– The length (total number of locations) is a
  function of the number of address lines.
          # of memory locations = 2( # of address lines)
   • So, a memory chip with 10 address lines would have
                210 = 1024 locations (1K)
   • Looking at it from the other side, a memory chip with 4K
     locations would need
             Log2 4096=12 address lines
The 8085 and Memory
• The 8085 has 16 address lines. That means it
  can address
     216 = 64K memory locations.
   – Then it will need 1 memory chip with 64 k
     locations, or 2 chips with 32 K in each, or 4 with
     16 K each or 16 of the 4 K chips, etc.


• how would we use these address lines to
  control the multiple chips?
SJCET
To communicate with other devices two interfacing
devices are used

Memory Interfacing
I/o Interfacing

MEMORY INTERFACING
• Require:
Select a chip
Identify the register
Enable the appropriate buffer



                         SJCET
Memory interfacing techniques
 • Techniques

 Absolute Decoding / Full Decoding
 Linear Decoding / Partial Decoding




                  SJCET
Absolute Decoding / Full Decoding




               SJCET
I/O Intefacing
• I/O devices can be interfaced to an 8085

I/O Mapped I/O
Memory Mapped I/O




                  SJCET
I/O Mapped I/O

• IN addr8
the content of port is moved to A- Register

• OUT addr8
The content of A register is moved to port



                  SJCET
Memory Mapped I/O

•   Mov r,m     LDA addr
•   LHLD addr   ADD M
•   XRA M       MOV m,r
•   STA addr




                 SJCET
Comparison of memory mapped I/O and Peripheral I/O


 Characteristics           Memory Mapped           I/O Mapped
 Device address            16 bit                  8 bit
 Control signals for I/O   MEMW        MEMR        IOR     IOW
 Instruction available     STA, LDA, LDAX,         IN & OUT
                           STAX etc.,
 Data Transfer             between any register    Between I/O and
                           and I/O                 accumulator
 Maximum no of I/O         64k                     Independent
 Execution speed           13T for STA &LDA        10T
 Hardware                  More hardware require   Less hardware



                                    SJCET

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8085 MICROPROCESSOR

  • 1. UNIT - I The 8085 Microprocessor Prepared By, Mr.R-THANDAIAH PRABU M.E., Lecturer - ECE thandaiah@gmail.com
  • 2. RE TU 5 CH 08 R AR IT EC 8 O SS TI ON CE & RA P RO GU RO FI MIC C ON PI N
  • 3. The 8085 and Its Busses • The 8085 is an 8-bit general purpose microprocessor that can address 216 =64K Byte of memory. • It has 40 pins and uses +5V for power. It can run at a maximum frequency of 3 MHz. – The pins on the chip can be grouped into 6 groups: • Address Bus. • Data Bus. • Control and Status Signals. • Power supply and frequency. • Externally Initiated Signals. • Serial I/O ports. SJCET
  • 4. Intel 8085 Pin Configuration SJCET
  • 6. Functional Blocks • Registers • Increment/ Decrement • ALU Address Latch • Instruction Decoder • Interrupt Control • Address Buffer • Serial I/O Control • Address/Data Buffer • Timing and control circuitry SJCET
  • 7. Registers • General purpose Registers • Temporary Registers • Special Purpose Register • 16 Bit Registers SJCET
  • 8. The Flags register – There is also the flags register whose bits are affected by the arithmetic & logic operations. • S-sign flag – The sign flag is set if bit D7 of the accumulator is set after an arithmetic or logic operation. CY – 0- + Ve 1- -Ve • Z-zero flag P – Set if the result of the ALU operation is 0. Otherwise is reset. This flag is affected by operations on the accumulator as well as other AC registers. (DCR B). • AC-Auxiliary Carry Z – This flag is set when a carry is generated from bit D3 and passed to D4 . This flag is used only internally for BCD operations. S • P-Parity flag – After an ALU operation if the result has an even no of 1’s the p- flag is set. Otherwise it is cleared. So, the flag can be used to indicate even parity. • CY-carry flag – CY = carry is set when result generates a carry. Also a borrow flag. SJCET
  • 9. PROGRAM COUNTER (PC) AND STACK POINTER (SP) • These are two 16-bit registers used to hold memory addresses. • PC: – The function of the PC is to point to the memory address from which the next byte is to be fetched. – When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location. • SP: – It points to a memory location in R/W memory, called the stack. – The beginning of the stack is defined by loading a 16-bit address in the stack pointer. – The PC will automatically update when calling to /returning from Subroutines.
  • 10. The ALU • In addition to the arithmetic & logic circuits, the ALU includes the accumulator, which is part of every arithmetic & logic operation. • Also, the ALU includes a temporary register used for holding data temporarily during the execution of the operation. This temporary register is not accessible by the programmer. SJCET
  • 11. The Address and Data Busses • The address bus has 8 signal lines A8 – A15 which are unidirectional. • The other 8 address bits are multiplexed (time shared) with the 8 data bits. – So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the same time. • During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits. – In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes. SJCET
  • 12. INCREMENT/ DECREMENT ADDRESS LATCH Interrupt Control: Fetch, Decode & execute RST 5.5, RST 6.5, RST 7.5, TRAP, & INTR Serial I/O Control SOD & SID Timing and Control Circuitry Its control fetching, decoding, execution SJCET
  • 13. Frequency Control Signals • There are 3 important pins in the frequency control group. – X0 and X1 are the inputs from the crystal or clock generating circuit. • The frequency is internally divided by 2. – So, to run the microprocessor at 3 MHz, a clock running at 6 MHz should be connected to the X0 and X1 pins. – CLK (OUT): An output clock pin to drive the clock of the rest of the system. • We will discuss the rest of the control signals as we get to them. SJCET
  • 14. The Control and Status Signals • There are 4 main control and status signals. These are: • ALE: Address Latch Enable. This signal is a pulse that become 1 when the AD0 – AD7 lines have an address on them. It becomes 0 after that. This signal can be used to enable a latch to save the address bits from the AD lines. • RD: Read. Active low indicates that the data must be read from the selected memory location or I/O port via data bus. • WR: Write. Active low indicates that the data must be written into the selected memory location or I/O port via data bus.. • IO/M: This signal specifies whether the operation is a memory operation (IO/M=0) or an I/O operation (IO/M=1). • S1 and S0 : Status signals to specify the kind of operation being performed .Usually un-used in small systems. SJCET
  • 15. GE UA N G A M L A LY GR B O M R S SE P A SJCET
  • 16. ADDRESSING MODES • IMMEDIATE MVI A,05(H) LXI H,0050(H) • DIRECT LDA 0208(H) • REGISTER MOV B,C ADD B • REGISTER INDIRECT LDAX B • INHERENT HLT STC(SET CARRY FLAG) SJCET
  • 17. NOTATIONS MEANING M Memory location pointed by HL reg pair r 8- bit register rp 16-bit register rs Source register rd Destination register addr 16-bit address SJCET
  • 18. Data Transfer Group • MVI r, data (8- Bit) • MVI M, data (8- Bit) • MOV rd, rs • MOV M, rs • MOV rd, M • LXI rp, data (16 bit) • STA addr • LDA addr • SHLD addr • LHLD addr • STAX addr • LDAX rp • XCHG SJCET
  • 19. MOV Rd,Rs MOV B,C • MVI R,8bit MVI A,05H • LXI Rp,16bit LXI B,2050 • MOV R,M MOV D,M • MOV M,R MOV M,E • LDA 16 bit LDA 8005H • STA 16 bit STA 8006H • LDAx Rp LDAx B • STAX Rp STAX D SJCET
  • 20. ARITHEMATIC GROUP • ADD r • SUB r • INR r • ADD M • SUB M • INR M • ADI data (8) • SUI data • INX rp • ADC r • SBB r • DCR r • ADC M • SBB M • DCR M • ACI data (8) • SBI data • DCX rp • DAD rp • DAA SJCET
  • 21. ADD R ADD B • ADI 8bit ADI 59H • SUB R SUB C • SUI 8bit SUI 37H • INR R INR D • DCR R DCR B • INR M INR M • DCR M DCRB M • INX Rp INX B • DCX Rp SJCET
  • 22. LOGIC GROUP • ANA r • ORI data • ANA M • CMP r • ANI data • CMP M • XRA r • CPI data • XRA M • STC • XRI data • CMC • ORA r • CMA • ORA M SJCET
  • 23. ANA R/M ANA D • ANI 8bit • ORA R/M ORA C • ORI 8bit • XRA R/M XRA D • XRI 8bit • RLC • RAL • RRC • RAR • CMP R/M SJCET
  • 24. BRANCH GROUP • JUMP INSTRUCTION • CALL and RETURN INSTRUCTION • RESTART INSTRUCTION SJCET
  • 25. JMP 16bit Address • JZ 16bit Address • JNZ 16bit Address • JC 16bit Address • JNC 16bit Address • HLT Stop processing and wait • NOP Don’t perform anything - delay SJCET
  • 26. STACK OPERATION I/O & CONTROL GROUP • PUSH • POP • RESTART RST n SJCET
  • 27. INSTRUCTION FORMATS 1 BYTE INSTRUCTION 2 BYTE INSTRUCTION 3 BYTE INSTRUCTION JMP 6200H --- MOV A,B --- 78H MVI B, 02 --- 06H 02 C3H 00 62 SJCET
  • 29. INSTUCTION SET MODIFICATION CONTROL MOVEMENT INSTUCTIONS INSTRUCTIONS INSTUCTIONS GROUP-0 GROUP – 1 GROUP – 2 GROUP – 3B I/O & DATA DATA ARITHEMATI GROUP -3A MACHINE TRANSFER TRANSFER C & LOGIC BRANCH CONTROL MVI,INR,DCR,LDA, JNZ,JNC,JC, HLT,ENABLE AND,ADD, STA,RAR,CMC, JZ etc., ,DISABLE, CMA,STC,DAA, MOV OR,XOR etc., PROGRAM INTR DAD,LDAX,SHLD, CONTROL PROCESS INX,RIM ETC., CONTROL SJCET
  • 30. BYTE ORGANIZATION GROUP - 0 0 0 R R R I0 I0 I0 GROUP - 1 0 1 R R R S S S GROUP - 2 1 0 A1 A1 A1 S S S GROUP - 3 1 1 Cb Cb Cb B0 B0 B0 SJCET
  • 31. CODE FOR RECEIVING AND SENDING REGISTERS/PAIRS RESSISTERS AADDRESS CODE RESSISTERS ADDRESS CODE B 000 B–C 00 C 001 D 010 D–E 01 E 011 H 100 H–L 10 L 101 M 110 SP 11 A 111 SJCET
  • 32. INFORMATION OPERATIONS (I0 I0 I0) ADDRESS OPERATION I0 I0 I0 0 0 0 NOT USED 0 0 1 IMMETIATE OPERATION REGISTER PAIR 0 1 0 LOAD / STORE 0 1 1 INCREMENT/ DECREMENT REGISTER PAIR 1 0 0 INCREMENT SINGLE REGISTER 1 0 1 DECREMENT SINGLE REGISTER 1 1 0 IMMETIATE OPERATION ON SINGLE REGISTER 1 1 1 REGISTER SHIFTING SJCET
  • 33. ARITHEMATIC AND LOGICAL OPERATIONS (A1 A1 A1) ADDRESS OPERATION A1 A1 A1 0 0 0 ADD 0 0 1 ADD WITH CARRY (ADC) 0 1 0 SUBTRACT (SUB) 0 1 1 SUBTRACT WITH BORROW (SBB) 1 0 0 LOGICAL AND 1 0 1 EXCLUSIVE OR (X-OR) 1 1 0 LOGICAL OR (OR) 1 1 1 COMPARE SJCET
  • 34. CONDITIONS OF BRANCH ( Cb Cb Cb) ADDRESS OPERATION Cb Cb Cb 0 0 0 IF NOT ZERO (JNZ) 0 0 1 IF ZERO (JZ) 0 1 0 IF NO CARRY(JNC) 0 1 1 IF CARRY (JC) 1 0 0 IF ODD PARITY (JPO) 1 0 1 IF EVEN PARITY (JPE) 1 1 0 WAS IT POSITIVE (JP) 1 1 1 WAS IT NEGATIVE (JM) SJCET
  • 35. BRANCH OPERATIONS (B0 B0 B0) ADDRESS OPERATION B0 B0 B0 0 0 0 CONDITIONAL RETURN 0 0 1 SIMPLE RETURN 0 1 0 CONDITIONAL JUMP 0 1 1 UNCONDITIONAL JUMP 1 0 0 CONDITIONAL CALL 1 0 1 SIMPLE CALL 1 1 0 SPECIAL A/L OPERATIONS 1 1 1 SPECIAL UNCONDITIONAL JUMPS SJCET
  • 36. MVI B, BYTE 0 0 R R R I0 I0 I0 0 0 0 0 0 1 1 0 MOV B,C 0 1 R R R S S S 0 1 0 0 0 0 0 1 ADD B 1 0 A1 A1 A1 S S S 1 0 0 0 0 0 0 0 SJCET
  • 37. Static RAM Dynamic RAM Static RAM contains less memory cells Dynamic RAM contains more memory per unit area cells as compare to static RAM per unit area It has less access time, hence faster Its access time is greater than static memories RAMs Static RAM consists of number of flip- Dynamic RAM stores the data as a flops. Each flip-flop stores one bit charge on the capacitor. It consists of MOSFET and the capacitor for each cell Refreshing circuitry is not required Refreshing circuitry is required to maintain the charge on the capacitor after every few milliseconds Cost is more Cost is less SJCET
  • 38. MACHINE CYCLES AND THEIR TIMING OF 8085: Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T-states. Instruction Cycle: The time required to execute an instruction is called instruction cycle. Machine Cycle: The time required to access the memory or input/output devices is called machine cycle. T-State: The machine cycle and instruction cycle takes multiple clock periods. A portion of an operation carried out in one system clock period is called as T-state.
  • 39. • Clock Signal The 8085 divides the clock frequency provided at x1 and x2 inputs by 2 which is called operating frequency. Rise time and fall time T-State 1 Clock cycle SJCET
  • 40. • Single Signal Single signal status is represented by a line. It may have status either logic 0 or logic 1 or tri-state Logic 1 Tri state Logic 0 SJCET
  • 41. • Group of signals Group of signals is also called a bus. Eg: Address bus, data bus Valid state State changes State changes Tri state Tri state SJCET
  • 42. SJCET
  • 43. Instruction cycle Instruction cycle Machine cycle1 Machine cycle1 Machine cycle 2 Machine cycle 2 Machine cycle 5 Machine cycle 5 T – State 1 T – State 2 T – State 3 T – State 1 T – State 2 T – State 3 T – State 6 T – State 6 SJCET
  • 44. The 8085 microprocessor has 5 basic machine cycles. They are 1.Opcode fetch cycle (4T) 2.Memory write cycle (3 T) 3.I/O read cycle (3 T) 4.Memory read cycle (3 T) 5.I/O write cycle (3 T)
  • 45. Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the 8085 processor executes an instruction, it will execute some of the machine cycles in a specific order. • The processor takes a definite time to execute the machine cycles. The time taken by the processor to execute a machine cycle is expressed in T-states. • One T-state is equal to the time period of the internal clock signal of the processor. • The T-state starts at the falling edge of a clock. • In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor.
  • 46. Opcode Fetch Machine Cycle • The first step of executing any instruction is the Opcode fetch cycle. – In this cycle, the microprocessor brings in the instruction’s Opcode from memory. • To differentiate this machine cycle from the very similar “memory read” cycle, the control & status signals are set as follows: – IO/M=0, s0 and s1 are both 1. – This machine cycle has four T-states. • The 8085 uses the first 3 T-states to fetch the opcode. • T4 is used to decode and execute it. – It is also possible for an instruction to have 6 T-states in an opcode fetch machine cycle. SJCET
  • 47. Timing Diagram for Opcode Fetch Machine Cycle SJCET
  • 48. Memory Read Machine Cycle of 8085: • The memory read machine cycle is executed by the processor to read a data byte from memory. • The processor takes 3T states to execute this cycle. • The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle. SJCET
  • 49. Memory Read Machine Cycle • The memory read machine cycle is exactly the same as the opcode fetch except: – It only has 3 T-states – The s0 signal is set to 0 instead. SJCET
  • 50. The Memory Read Machine Cycle – To understand the memory read machine cycle, let’s study the execution of the following instruction: • MVI A, 32 – In memory, this instruction looks like: • The first byte 3EH represents the opcode for loading a byte into the accumulator (MVI A), the second byte is the data to be loaded. – The 8085 needs to read these two bytes from memory before it can execute the instruction. Therefore, it will need at least two machine cycles. – The first machine cycle is the opcode fetch discussed earlier. – The second machine cycle is the Memory Read Cycle. 2000H 3E 2001H 32 SJCET
  • 51. Timing Diagram for Memory Read Machine Cycle SJCET
  • 52. Memory Write Machine Cycle of 8085: • The memory write machine cycle is executed by the processor to write a data byte in a memory location. • The processor takes, 3T states to execute this machine cycle. SJCET
  • 53. The Memory Write Operation • In a memory write operation: – The 8085 places the address (2065H) on the address bus – Identifies the operation as a memory write (IO/M=0, s1=0, s0=1). – Places the contents of the accumulator on the data bus and asserts the signal WR. – During the last T-state, the contents of the data bus are saved into the memory location. SJCET
  • 54. Timing Diagram for Memory Write Machine Cycle SJCET
  • 55. SJCET
  • 56. INTERFACING I/O AND PERIPHERAL DEVICES: 1. For data transfer from input device to processor the following operations are performed. • The input device will load the data to the port. • When the port receives a data, it sends message to the processor to read the data. • The processor will read the data from the port. • After a data have been read by the processor the input device will load the next data into the port. SJCET
  • 57. 2. For data transfer from processor to output device the following operations are performed. •The processor will load the data to the port. •The port will send a message to the output device to read the data. •The output device will read the data from the port. •After the data have been read by the output device the processor can load the next data to the port. •The various INTEL 110 port devices are 8212, 8155/8156, 8255, 8355 and 8755. •8212 •The 8212 is a 24 pin IC. •It consists of eight number of D-type latches. •It has 8-input lines DI1 to DI8 and 8-output lines DO1 to DO8 •The 8212 can be used as an input or output device •It has two selecting device DS1 (low) and DS2. SJCET
  • 58. SJCET
  • 59. SJCET
  • 60. Dimensions of Memory • Memory is usually measured by two numbers: its length and its width (Length X Width). » The length is the total number of locations. » The width is the number of bits in each location. – The length (total number of locations) is a function of the number of address lines. # of memory locations = 2( # of address lines) • So, a memory chip with 10 address lines would have 210 = 1024 locations (1K) • Looking at it from the other side, a memory chip with 4K locations would need Log2 4096=12 address lines
  • 61. The 8085 and Memory • The 8085 has 16 address lines. That means it can address 216 = 64K memory locations. – Then it will need 1 memory chip with 64 k locations, or 2 chips with 32 K in each, or 4 with 16 K each or 16 of the 4 K chips, etc. • how would we use these address lines to control the multiple chips?
  • 62. SJCET
  • 63. To communicate with other devices two interfacing devices are used Memory Interfacing I/o Interfacing MEMORY INTERFACING • Require: Select a chip Identify the register Enable the appropriate buffer SJCET
  • 64. Memory interfacing techniques • Techniques Absolute Decoding / Full Decoding Linear Decoding / Partial Decoding SJCET
  • 65. Absolute Decoding / Full Decoding SJCET
  • 66. I/O Intefacing • I/O devices can be interfaced to an 8085 I/O Mapped I/O Memory Mapped I/O SJCET
  • 67. I/O Mapped I/O • IN addr8 the content of port is moved to A- Register • OUT addr8 The content of A register is moved to port SJCET
  • 68. Memory Mapped I/O • Mov r,m LDA addr • LHLD addr ADD M • XRA M MOV m,r • STA addr SJCET
  • 69. Comparison of memory mapped I/O and Peripheral I/O Characteristics Memory Mapped I/O Mapped Device address 16 bit 8 bit Control signals for I/O MEMW MEMR IOR IOW Instruction available STA, LDA, LDAX, IN & OUT STAX etc., Data Transfer between any register Between I/O and and I/O accumulator Maximum no of I/O 64k Independent Execution speed 13T for STA &LDA 10T Hardware More hardware require Less hardware SJCET