1. COTS Approach to Military Microprocessor MCMs
by
Tom Terlizzi
Vice President
Aeroflex
35 South Service Road
Plainview, L.I., N.Y. 11803
Phone: 516.752.2418 FAX: 516.694.6715
email: T2@AEROFLEX.COM
ABSTRACT
One of the major problems in fielding state of the art Military electronic systems is the lack of
militarized electronic components and their swift obsolescence. This paper describes the
development of a line of 64 bit MIPS-BasedTM Microprocessor Multi-Chip Modules (MCMs).
Solutions and obstacles encountered to support these products for over a decade and the
applicability of these solutions to other similar products are described.
KEY WORDS: MIPS-BasedTM 64 bit Microprocessor, Multi-Chip Modules (MCMs), Military, obsolescence.
Introduction
Military Original Equipment Manufacturers (OEMs) are facing a difficult situation in obtaining
high performance semiconductor components. Figure 1 illustrates that the percentage of
military value will decrease to 0.5% in 2005. This trend is the reason many semiconductor
vendors are exiting the Military and Space product markets. The economics cannot support
the infrastructure to deal with these products in low volume and low revenue content. Added
to this problem is the long life cycle of typical military products. This is not coincident with
Moore’s law or the demand for new commercial products as shown in Figure 2.
35%
30%
25%
20%
15%
10%
5%
0%
1955 1975 1995 *2005
Figure 1 - Percentage of U.S. Semiconductor Production Designated for Military Use
by Value1
Typical designs and product life cycles for wireless cell phones are at a point where there are
two designs per year. However, the volumes for cell phones are in the tens to hundreds of
1. Braun, Ernest and MacDonald, Stuart “Revolution in Miniature - The History and Impact of Semiconductor
Electronics”, pp80 (1982). Update Walt Lahti of ICE*.
1
2. millions per year. While military life cycles are in the order of tens of years and the volumes
are in the hundreds to thousands.
Table I - MCM Thermal Device Data
Die Power Junction θjc
Device Size Watts Temp. Rise °C/W
(inch) (max) (°C) (max)
R4400SC 0.498
x 14 5.78 0.413
Microprocessor 0.707
0.203
3PC218 SRAM x 0.5 1.08 2.16
0.232
0.065
CMOS Buffer x 0.25 2.82 11.28
0.067
Figure 2 - Typical Product Life Cycle
Multi Chip Modules Design Considerations
In 1992 Aeroflex’s initial military microprocessor MCM was the 1608 a 64-bit MIPS TM RISC
Microprocessor with 256K secondary cache memory. It was packaged in a 280 lead ceramic
quad flatpack (CQFP) as a custom design with a major military OEM. A photograph with
physical dimensions is shown in Figure 3 below.
2.525 MAX
R4400 MIPS RISC 85 Spaces at 0.025
Microprocessor Die
Pin 226 Pin 141
Pin 227 Pin 140
53 Spaces 1.768
at 0.025 MAX
.010
11 each Pin 280 Pin 87
16K x 16
Pin 1 Pin 86
SRAM Die
.175 MAX
.072 ±.01 .006
Note: Outside ceramic tie bars not shown for clarity.
Contains 1,516
Note: Ceramic Tie Bar Wire Bonds
Figure 3 - 64 Bit MIPs RISC Microprocessor MCM 1608
Table I lists the key components for the initial design and their attributes. Figure 4 is a
simplified block diagram showing the 256K of Level 2 (L2) cache.
MIPS is a registered trademark in the United States and other countries, and MIPS32, 4KEc, 4Kp,
SOC-it and MIPS-based are trademarks of MIPS Technologies, Inc.
2
3. SCData(127:0)
Secondary SCDchk(15:0)
or Level 2 SCDCS SCOE
(L2) Cache DQ143-DQ0
CE INTEGER EXECUTION UNIT
(9) 16K SCAddr0
A0 General Registers
OE by 16
SRAMs ALU/Multiply/Divide Primary
or Level 1
DATA/INSTRUCTION Pipeline/Control (L1) Cache
CACHE
A14:A1
CACHE/MMU
WE A15
BWH BWL 16K Byte 16K Byte
Instruction Data
Cache Cache
Cache
48 Entry Control System
GND TLB Interface
SCAddr MMU
(14:1)
FLOATING POINT
FPU ALU
BWH BWL SCAddr
17 Multiply/Divide
(2) 16K A15
Square Root
by 16
OE SRAMs
FP Register
CACHE TAG
A14:A1
Pipeline Control
A0
WE
CE DQ0-DQ31 R4400SC/MC Microprocessor
SCTag(24:0)
SCTCS SCWE
SCTchk(6:0)
Figure 4 - Simplified Block Diagram of the 64 Bit MIPs RISC
Microprocessor MCM 1608
3
4. Multichip Module Design Considerations
Electrical
Introduction
The electrical requirements for the initial MCMs specified a 66 Mhz clock rate with an
estimated 3.0 nanoseconds minimum rise time. The signal path is modeled as a simple R-C
series circuit as shown in Figure 5. The 3-db bandwidth can then be related to the pulse rise
time of the digital signals of the MCM. Since the system pulse rise time is 3.0 nanoseconds,
the required bandwidth is 116.6 MHz. As shown in Figure 6, to reproduce the rise time with
minimal distortion (<2%) would require passing the 5th harmonic or 5 x 116.6 MHz or 583.3
MHz.
– t ⁄ ( RC )
VOUT V OUT = V ( 1 – e )
V R
C R=RESISTANCE OF CONDUCTORS
C=CAPACITANCE OF THE SIGNAL PATH
1.00
.95
.90
.85
.80
PERCENTAGE OF FULL VOLTAGE
.75
.70
.65
.60
.55
.50
.45
.40
.35
.30
.25
.20
.15
.10
.05
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
2.2 RC TIME IN RC INCREMENTS
0.1 2.3
1 - 1
f3db = -------------- or C MAX = ----------------------------
-
2πRC 2π ( 5f 3db )R
2.2 1
t risetime = 2.2RC = ---------------
- C MAX = ------------------------------------------------------------
2πf 3db 2π × 583.3MHz × 3.75Ω
0.35
t risetime = ---------
-
f 3db C MAX = 72.6pf
Figure 5 - Simple RC Model of MCM Traces
4
5. For example, the resistance of a circuit with an 8 mil line width which is two inches long can
be calculated as follows:
l-
R = ρ × ---
w
where:
ρ = conductor sheet resistivity
l = length of conductor
w = width of conductor
If the sheet resistivity (ρ) is .015 ohms/❑ , then R = 3.75 ohms. Solving for the maximum
capacitance from Figure 5 results in CMAX = 72.6 pf or 36.3 pf/inch or 14.28 pf/cm.
4
Line Capacitance Co (PF/cm)
3
W h
2 t
εv h
1
0 4 8 12 16 20
Dielectric Thickness h (mils)
Figure 7 - Line Capacitance VS. Dielectric Thickness
Thus, the simplified model shows that high temperature alumina cofired ceramic (HTCC)
can be used with a two inch conductor run since for a variety of dielectric thickness and
conductor widths, the capacitance per unit length is less than 3.0 pf/cm, see Figure 7 (Per
typical manufacturer’s data sheet).
While other materials with lower dielectric constants are available (See Table II below), only
aluminum nitride has better thermal conductivity. However, in 1992 we felt at that time that
aluminum nitride had a higher technical risk and no extensive history of military qualification.
Therefore, alumina ceramic represented the lowest risk at that time.
Table II - Ceramic Material Characteristics
Thermal Conductivity
Ceramic Technology Dielectric Constant
W/m*k
Alumina 9.7 - 10.0 17
Aluminum Nitride (AlN) 8.5 150
Low temperature Cofired Ceramic 7.9 2
Mullite 6.8 5
Glass Ceramics (LEC) 5.0 2
5
6. 40
30
25
20
15
10
9
% ERROR
8
7
6
5
4
3
2
1
1 2 3 4 5 6 7
RISE TIME RATIO
t = risetime
t OUTPUT = t 2 INPUT + t 2SIGNALPATH
t INPUT
re: if -------------- = t SIGNALPATH
5
t 2INPUT
tOUTPUT = t 2 INPUT + ----------------
-
52
1
= t INPUT 1 + -----
-
25
tOUTPUT = tINPUT X 1.019 2% error
Figure 6 - Trace Rise Time vs Distortion
6
7. Propagation Delay and Line Length
Using the dielectric constant of alumina as 10 and the formula for propagation delay as:
Tpd = 0.0333 × ε in nSec/cm
if ε = 10 then Tpd = 0.1 nanoseconds/cm
Therefore, for a two inch conductor length, the maximum propagation delay would be:
2 inches x 2.54 cm/inch x .1nanoseconds/cm or 0.508 nanoseconds.
Since our signal lines are not terminated in the characteristic impedance of the transmission
line, there will be overshoot and ringing. However, if we restrict the line length to be
sufficiently short, then the signal will be still rising at time Td (see Figure 9) and the
reflections will be part of the rising edge (and also falling edge). With longer lines, the rise of
the signal will be completed and reflections will appear as overshoot and undershoot. The
maximum unterminated line length results in a maximum 15% ringing2, if the line length is
held to:
Tr
Lmax < ------------------
-
2 × Tpd
where
Tr = rise time
Tpd = propagation delay of line per unit length
This assumes that there is no capacitive loading on the line. If capacitive loading is present
then the Tpd term must be replaced by T'pd which is calculated as follows.
T ′ pd = Tpd × 1 + Cd
------
-
Co
Co = Capacitance ⁄ Length
Cd = Capacitive-loading ⁄ Length
2. Kaupp, H.R “Characteristics of Microstrip Transmission lines”, IEEE Transactions on Electronic Computers, Vol.
EC-16, No.2, April 1967, pp.185-193
7
8. For example, if an 8 mil thick dielectric tape and an 8 mil conductor line width are used then
the capacitance per unit length is approximately 2.5 pf/cm or 6.35 pf/inch (see Figure 7). If
the circuit has six 3 pf loads plus an output load of 10 pf at the receiving end 2 inches from
the driver then:
( 18 + 10 )
----------------------
-
1 + ----------------------
T ′ pd = 0.25nsecs × 5.08 -
2.5
= 0.25nsecs × 1.79
= 0.447n sec s
3nsecs -
L max < ----------------------------------- = 3.35in
2 × 0.447nsecs
This is a conservative requirement to meet for most of the MCM signals since the maximum
electrical signal length is 1.5quot; - 2quot;. For those signals that are critical, a Spice analysis is
performed, as well as insuring that the signal is routed over ground planes to insure
microstrip performance. Described below in Figure 8 are typical characteristic impedancee
for several dielectric thicknesses. Spice analysis waveforms are shown in Figure 9 for the
R4400SC MCM for the SRAM data address lines.
Calculated Data
60 4 × 2h
Zo = -------- ⋅ ln --------------------------------------
-
εγ 0.67 π ( 0.8w + t )
Characteristic Impedance Zo (Ω)
70
60
41.6 W h
50
40 t
30 εv h
20
10
0 4 8 12 16 20
Dielectric Thickness h (mils)
Figure 8 - Typical Characteristic Impedances
8
9. Output of Micro
<< 15%
Shorter Lengths
To SRAM
Addresses
Longer Lengths
To SRAM
Addresses
Td
<< 15%
Figure 9 - Spice Analysis Waveforms
Crosstalk
The crosstalk between two parallel lines 2 inches long on the same conductor layer is
approximated for a 3 nsec rise time as shown in Figure 10. The results indicate
approximately a 175mv crosstalk level for an 8 mil line and 8 mil space with an 8 mil
dielectric. The capacitance and inductive coupling are approximately 0.4 pf/cm and 1 nH /cm
respectively. The crosstalk levels are highly dependent on the driver chip output impedance
and loading at the far end. Therefore, the chips must be modeled using the specific device
and characteristic output impedance with a Spice simulator.
The physical layout was also designed to ensure that adjacent layer signal lines are
orthogonal. If there are layers that are not separated by power and ground, two levels away,
then they will routed so they are not parallel to minimize coupling.
CALCULATED CROSS TALK
300
250
CROSSTALK, mV (FAR END)
200
8 MIL LINE
8 MIL SPACE
150
100
50
0
5 8 10 12 18
Dielectric Thickness h (mils)
Figure 10 - Cross Talk vs Dielectric Thickness
9
10. Decoupling Capacitors
The MCM’s circuits can cause significant switching current transients which can cause VCC
to drop. When 3.3 volt logic signal levels change 2.5 volts (from a high to a low), the output
buffer circuit effectively sees a 40 ohm transmission line impedance. This change in voltage
causes an instantaneous output high current change of 62.5 mA. If sixty-four buffers
changed simultaneously, the current demand on the power supply would be 4 amps. If less
than a 0.1V VCC drop is specified, then we can solve for the decoupling capacitor by using:
dv dt
∴ C = I × -----
I = C × -----
- -
dt dv
C = 4 × 3.0nsecs = 0.12 µ F
--------------------
0.1V
C = 0.12 µ F
Twenty-three .01µF 0603 ceramic capacitors were used in the MCM for decoupling.
Power Distribution
The conductor material for high temperature cofired system is tungsten, with a sheet
resistivity of 15 milliohms per square maximum. Due to the sheet resistivity of tungsten, the
resistance of power and ground must be considered in the design layout stage to insure that
there will not be excessive voltage drops within the MCM.
Since we provided for fault isolation, in the event that a die shorts out, we routed at least one
separate power and ground pin to each row of SRAM die and to the microprocessor. This
also has the beneficial effect of reducing the inductance due to the paralleling of several
power and ground pins. For the R4400SC, the D.C. current was approximately 3 Amperes.
To obtain less than a 1% D.C voltage drop required the trace resistance to be R = V/I or
33mV/3A = 11 milliohms. Evenly splitting the resistance between power and ground yields
5.5 milliohms. Thus, the trace resistance between the power pin and the wirebond pad must
be less than 5.5 milliohms to eliminate excessive voltage drops. To achieve this requirement
multiple power and ground traces were used on the R4400SC microprocessor die. There are
approximately 100 power and ground pins used to distribute the heavy currents within the
chip.
Thermal Management
Using a simplified MCM layout for worst case thermal analysis the results are shown in
Figures 11 through 13 and Table I. The simplified finite element model does not show that
the die sits in a cavity. This reduces the ceramic thickness to 48mils and an extra “Phantom”
die is modeled to make the analysis symmetric. Thus, our thermal resistance numbers are
very conservative.
10
12. °C
C . 36
.36°
Figure 13 - R4400SC MCM Finite Element Analysis Cross Sectional
Thermal Gradients
Mechanical
Introduction
High temperature cofired ceramic (HTCC) technology offers the lowest risk solution to the
R4400SC MCM and is by far the most mature of the emerging MCM technologies. The
analysis of thermal constraints, routing density and electrical requirements including
maximum signal frequency and minimum rise times reveals that all are within HTCC
capability. Additionally, the die rework was a major concern and “Know Good Die” were not
available. HTCC is more forgiving to die rework than is organic or silicon substrates.
Package Construction
The packages is constructed with eight 8 mil thick tape layers resulting in a nominal base
thickness of 64 mils. The Microprocessor is centrally located in a cavity approximately 16
mils below the top surface. This improves wirebonding and die thermal conductivity. An
integral substrate provides the interconnect between all die and I/O pins. A two tier wire
bonding shelf enabled 1 mil aluminum wire bonding to the over 400 pads on a 4.3 mil pitch of
the R4400 microprocessor die. A 60 mil high cover seal ring is brazed to the alumina
providing the component cavity. All I/O pins are fabricated from Alloy 42 and brazed to the
alumina utilizing “dog leg” form. The opposite end of the leads will be attached to a
non-conductive alumina ceramic tie bar, to protect the leads from damage in assembly and
test. A 15 mil thick cover lid with a 6 mil step is seam welded to the kovar ring frame to
provide a hermetic seal.
12
13. Seal Ring and Seal Ring Metallization
The package seal ring material is kovar in accordance with MIL-PRF-38534, Type A. The
seal ring dimensions will be 30 mils wide by 60 mils high with a +/- 2 mil tolerance. The seal
ring (Figure 14) has an internal corner radius of 30 mils and an external radius of 60 mils.
The seal ring metallization will be 70 mils wide and internal and external radii of 60 mils to
ensure adequate braze fillets at the corners. This modified geometry has been qualified to
aircraft vibration and shock levels with no failures.
.135
.030
.045 .020 TYP
.010
.050 TYP .060 R
.030 R
SEAL RING
.010
.018 X .045 CONTACT PADS
LID ETCHED DOWN TO .005 FOR SEAM WELDING
µP
.015 Die
.175 MAX Cavity
.006
.064
See Detail A
.048
Detail A
Figure 14 - 1608 Package Construction
Package Leads
The lead frame material is Alloy 42 in accordance with MIL-PRF-38534, Type A. Due to the
lead forming anticipated, changes are offered to ensure lead integrity during forming. The
leads are 10 mils wide by 6 mils thick and brazed to the alumina in a “dog leg” form on a 18
mil by 45 mil braze pad. This configuration ensures adequate braze fillets around the entire
lead.
Lid design and deflection
Detailed analysis and empirical testing was performed on the final lid design. The 1608
MCM has a nickel plated kovar lid with dimensions 2.315” long by 1.315” wide . The etched
kovar lid has a base thickness of 20 mils . The perimeter has a 5 mil flange to provide for
seam sealing the hermetic enclosure. Aeroflex uses Rome Air Development Center (RADC)
technical report TR-81-382 – “Microcircuit Stress Analysis” as the basis for all lid deflection
calculations . This is supplemented by finite element analysis and empirical testing. Using
special fixtures and gagues, the actual lid deflection is measured under helium leak test
13
14. pressures to validate the lid design and analysis. Table III below lists the deflection
results versus bomb pressure encountered during fine and gross leak testing per
MIL-STD-883. The worst case minimum internal headroom was 20 mils. Thus, a bomb
pressure of 15 PSIG was selected to allow a minimum two times safety margin. If the
deflection analysis did not meet a 2x safety factor, then ceramic or gold plated kovar
spacers would be incorporated into the design. During die attach the spacers would be
epoxied or brazed on the top layer of the MCM package.
Table III - Lid Deflection vs Leak Test Bomb Pressures
Calculated deflection Actual Deflection
Bomb Pressure (PSIG
(Inch) (Inch)
15 0.007 0.009
30 0.015 0.0155
Obstacles, Obsolescence, and Solutions
Introduction
After our first die supplier in early 1993 was having difficulty producing the R4400
microprocessor die, Aeroflex was faced with developing multiple and other backup die
sources. Fortunately for the project the MIPS R4400 computer architecture was widely
available from ten vendors and four were willing to sell die. This accelerated our
development of a COTS philosophy prior to Dr. Perry’s edicts in 1994 to use commercial
technology in military systems.
Component Obsolescence – A Proactive Approach
Aeroflex Circuit Technology's (ACT) MIPS microprocessor product line includes a unique
Three-Pronged Approach3 to the component obsolescence issues plaguing the military
and high-reliability markets:
■ First is to provide cutting edge technology to their target markets
■ Second is to increase product life span by continually enhancing performance
while retaining the footprint and pinout compatibility.
■ Third is to provide for an orderly migration path to future products.
The GOAL: Take advantage of technological advances in the commercial and industrial
component environment.
■ Reduce costs at both the component and system level.
■ Gain access to, “Cutting Edge Technology!”
■ Reduce component and system lead times.
The REALITY: Accelerated exposure to component obsolescence for major OEM’s and
a new acronym DMS (Diminished Manufacturing Sources).
3. Terlizzi, Tom and Ramos, Frank “Component Obsolescence-A Proactive Approach” COTS-CON 2000
14
15. COTS products Life Cycles prove to be incompatible with military program Life Cycles and
funding requirements; obsolescence increases.
As an example of this reality, at a recent DMS conference an OEM complained about the
results of a redesign effort to replace obsolete components. Within a year 50% of the new
replacement components had obsolescence problems before commencing production.
Aeroflex in 1993 developed a long-term plan for this MIPS processor MCM with the
following criteria:
■ Mechanical: Select a package style and footprint
■ Electrical: Select a pinout with expansion capabilities and also upward
compatible
■ Functional: Evolve the MCM from 256K to 1M of L2 cache
Controlling costs and lead-time by design re-use is always one of the primary concerns.
We attempt to leverage investments in by keeping the footprint identical:
■ Package Tooling
■ Test Socket tooling
■ Test Software
■ Customer’s next level assembly experience, lead bend fixtures and tooling
Up screening of suitable commercially available product provides cutting edge technology
quickly to the military OEM:
Military Temperature Testing
Environmental Screening; including Burn in
IE. 4400 179 Pin CPGA 4700 179 Pin CPGA
Additionally, by providing the Military OEM product support by “evaluation adapters” which
provide a means to evaluate performance increases in their system with real software
instead of vague benchmarks (see Figure 15 ).
In 1997 Aeroflex made a strategic decision to follow the MIPS Technologies Roadmaps as
commercial applications would dictate future MIPS availability.
MIPS architecture had 50% of the total RISC market share. Also, MIPS was the highest
growth RISC architecture (1997,1998 & 1999) and the only true 64-bit architecture in volume
production at the time.
Even as we speak, Intel and AMD are now just shipping their first 64 bit machines (early
2003).
15
16. A CT-52 60P C-P 10-P OD
Figure 15 - “Evaluation Adapters”
Obsolescence
In 1997 we were faced with a major unannounced microprocessor die obsolescence due to
a die shrink. The die vendor failed to notify us of their change. With many cofired packages
in our stockroom and critical customer delivery schedules at risk a solution was urgently
needed.
Our solution was to develop a unque interposer which did not degrade the thermal
characteristics of the microprocessor die. Our sister division, MIC Technology came to the
rescue by developing, very quickly, a “picture frame” thin film multilayer on ceramic
interconnect as shown in Figure 16 and 17. This enabled us to get back in to production and
we are still shipping these parts today in 2003.
We have been fairly sucessful at die banking and last time MCM buys for our OEMs and the
government but it always a difficult last minute decsion for all of us.
1 mil Aluminum wire from
R4400 microprocessor
die to interposer
1 mil gold wire
Two tieded wirebonding shelf
and pads on MCM cofired
package - top layer
Figure 16 - Magnified View of Aeroflex’s MIC Technologies Thin Film
(“Picture Frame”) Interposer
16
17. Thin Film “Picture Frame” Interposer
Figure 17 - Thin Film “Picture Frame” Interposer
In 1999, to further extend the life of the MIPS microprocessor MCMs with L2 cache we
introduced the ACT-5271SC. This MCM was co-developed with one of our major OEMs,
Quantum Effect Designs (QED), and MIPS Technologies. The 5271SC MCM is shown in
Figure 18. QED was later acquired in 2000 by PMC-Sierra. We have continued our licensing
agreement for military and high rel market which was started in 1997 with QED.
Spin-off products from the initial MCM products were ACT5260PC and ACT7000SC. The
microprocessor die, phase lock loop components, decoupling capacitors are all packaged in
a 208 CQFP as shown in Figure 19. All these products are footprint and pinout compatible.
The only major difference is the core voltage and that the ACT7000SC has L2 cache on
board the microprocessor die. Figure 20 shows the ACT7000SC in a cavity down lead bend
format on a COTS VME Board.
2 MB SC: (Sync Burst Cache RAM)
Cache TAG CPU Cycle FIFO: 2 FPGA
RAM
Control CPLD
Configuration
Serial PROM: FPGA
PLL CLK Driver MIPS uP: RM5261
Figure 18 - ACT5271SC MCM
17
18. Figure 19 - ACT5260PC MCM
ACT7000SC with cavity down commercial foot-print
Figure 20 - Star 7 MVP Militarized COTS VME Bus Single Board Computer
18
19. Conclusion
Aeroflex has developed a COTS approach to Military Microprocessors MCMs for over a
decade using a unique synergy of partners as shown in Figure 21. The long product life
cycles of Military systems, recently evidenced by the 50th anniversary of the Boeing B-52
bomber, require a different strategy. While there have been many obstacles and
obsolescence issues encountered over the last decade, solutions are generated by using
electronic design, MCM packaging and business skills. Each of these aspects are important
but must be combined for the total economic solution.
Figure 21 - Synergy of Partners
Summary
1. Robust MCM packaging platform
■ HTCC provides many solutions to electrical, thermal and manufacturing requirements
for Military/Aerospace applications.
■ MCM technology offers technology insertion in same footprint
2. Provide Cutting Edge Technology to our Customers
■ Strategic arrangements and licensing agreements provides access to the latest
commercial technology
■ Robust MIP Technologies RISC computer architecture provides cost, power savings,
and high performance.
■ Hi-Rel Products available within months of the introduction of equivalent Commercial
product
■ Provide technical support and software tools using widely available commercial
development packages
■ Evaluation adapters allow software benchmarks early in program
19
20. 3. Increase Product Life Span By:
■ Maintaining IC Package Footprint and Pinout Compatibility to existing products while
providing Higher Performance in next generation products
■ Protect large investments in software and application code and quality software testing
4. Provide an Orderly Migration Path to the Future
■ CPU products at various points along the Price/Performance curve
■ Redesign when you need to; Not because you’re forced to by component
Acknowlegement
The author would like to thank the following people for their valuable insight, help and
patience: Paul Carment and Joe LaFiandra.
In addition thanks are due to all at PMC-Sierra, MIPS Technologies, and Aeroflex Circuit
Technology since the accomplishments summarized in this paper could only result from a
team effort.
20
