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3rd 3DDRESD: SysGen

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Marco Santambrogio
Marco Santambrogio

The document discusses system generation for dynamic reconfiguration in embedded systems design. It proposes a standard flow for system generation that can correctly and completely solve reconfiguration problems by characterizing the system and using the appropriate reconfiguration flow (e.g. module-based or early access partial reconfiguration). The goal is to abstract away the complexity of different Xilinx ISE versions and board requirements to provide a unified flow.

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SysGen - System Generation in Caronte flow - POLITECNICO DI MILANO D ynamic R econfigurability in E mbedded S ystems D esign Matteo Renesto: matteo.renesto@dresd.org
Context of Work ,[object Object],[object Object],[object Object]
State of Art ,[object Object],[object Object]
Proposed solution ,[object Object],[object Object],[object Object],[object Object],START Given a problem P, composed by a Project and HW – SW context. IF it is possible to solve that problem, that is to realize the project, THEN use right flow, in order to produce the right result ELSE Show why it’s not possible. END
Goal: A Standard Flow Reconfigurable Project System Characterization Acheronte: Module-Based INCA: EAPR Other: MB or EAPR or Other Error or Success System Generator
Key aspects ,[object Object],[object Object],[object Object]
System Characterization ,[object Object],[object Object],[object Object]
System Characterization ,[object Object],[object Object],[object Object],Why is important to know the characterization?
[object Object],[object Object],[object Object],[object Object],[object Object],How To Create a Reconfigurable Project
How To Create a Reconfigurable Project ,[object Object],[object Object],[object Object],[object Object],[object Object]
Matching our flow with Xilinx ISE In order to have a working flow, we have to analyze each case, and what that case allows us to do.   ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1 Module-Based ? ? ? ? Early Access ? ? ? ?
Module Based Flow ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
MB Flow with ISE 7.1: Acheronte ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
First Result ,[object Object],  ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1 Module-Based V Early Access X
Module Based with ISE 8 ,[object Object],[object Object],[object Object],[object Object]
The problem of ISE 8 ,[object Object],[object Object],[object Object],[object Object]
The problem of ISE 8 ,[object Object],[object Object]
The problem of ISE 8
The problem of ISE 8 ,[object Object],[object Object],[object Object]
Early Access Partial Reconfiguration ,[object Object],[object Object],[object Object]
EAPR on ISE 8.2: INCA Flow ,[object Object],[object Object]
Second Result ,[object Object],[object Object],  ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1 Module-Based V X Early Access X V
ISE 9.2 ,[object Object],  ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1 Module-Based V X X Early Access X V V
ISE 10.1 ,[object Object],[object Object],  ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1 Module-Based V X X X Early Access X V V ?
Conclusion ,[object Object],[object Object],[object Object]
Future Works ,[object Object]
Future Works ,[object Object],  ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1 ISE X.Y Module-Based V X X X X Early Access X V V ? X New Flow X X X X V
Questions? ?

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3rd 3DDRESD: SysGen

  • 1. SysGen - System Generation in Caronte flow - POLITECNICO DI MILANO D ynamic R econfigurability in E mbedded S ystems D esign Matteo Renesto: matteo.renesto@dresd.org
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  • 5. Goal: A Standard Flow Reconfigurable Project System Characterization Acheronte: Module-Based INCA: EAPR Other: MB or EAPR or Other Error or Success System Generator
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  • 11. Matching our flow with Xilinx ISE In order to have a working flow, we have to analyze each case, and what that case allows us to do.   ISE 7.1 ISE 8.2 ISE 9.2 ISE 10.1 Module-Based ? ? ? ? Early Access ? ? ? ?
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  • 18. The problem of ISE 8
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