1. B )MOS Transistor Fabrication
Problem

2. 1. Identify the two problem that exist
in CMOS Ttransistor operation:
 A) Latch up
- CMOS transistor not functioning properly.
- If the transistor gain and resistance increase
continuously, latch-up current can permanently damage or
destroying junctions. Therefore, the transistor can’t be use.
 B ) parasitic capacitance
- limiting their high frequency performance
- It becomes a problem with higher frequencies because
the very small distributed capacitances that exist will
have lower impedances at these frequencies

3. 2. Explain latch up and parasitic
capacitance effects on circuit operation
A ) latch up
 CMOS transistor not functioning properly.
 If the transistor gain and resistance increase
continuously, latch-up current can permanently
damage or destroying junctions. Therefore, the
transistor can’t be use.
B ) parasitic capacitance
 simulate grounding shorts, line linkage, feedback
paths and other generally undesirable features in the
circuit.

4. 3. Explain methods to overcome latch up and
parasitic capacitance problems in IC fabrication
 A ) latch up
 Latch up Protection Technology circuit were used.
 Move n well and n+ farther apart.
 Reduce the well and substrate resistances
 B ) parasitic capacitance
 A P-well blocked layer is formed directly beneath a
parasitic device.
 Partially disconnects the parasitic device from the
ground terminal to minimize the effective capacitive
impedance that is added to the total termination
impedance.

5. 4. Compare CMOS technology i.e P – well, N-well, twin
–tub, and SOI in terms of circuit performance due to
latch up and parasitic capacitance
Type of CMOS Latch up
P – well •Latch up problem arise.
• Parasitic capacitance
higher due to no insulator.
N – well •Latch up problem arise.
• Parasitic capacitance
higher due to no insulator.
Twin – tub •Reliability higher due to lower in parasitic capacitance.
SOI •No latch up
• Smaller parasitic
capacitance

6. C. Scalling Effect in MOS Devices

7. 1. Explain MOS Scaling Theory
 Technology scaling rate is approximately13% / year,
halving every 5 years. Besides increasing the number
of devices, scaling has had a profound impact on both
speed and power.
 Keeping the electric field patterns constant avoids
breakdown and other secondary effects.
 This leads to greater device density, higher speed and
reduced power consumption.

8. 2. Explain scaling impacts on circuits
performance and power
 Circuits performance
 Accuracy specification
 Weak inversion operation
power consumption.
 accuracy, bandwidth or speed of

9. 3. Explain CMOS scaling technology
evolution :
 A ) Submicron
The sub-micron CMOS technology has
channel length less than 1 micrometer

10.  B ) deep - submicron
deep sub micron refers to any
technology smaller than 180
nano or .18 micron currently we
have reached till 32 nano.

11. C ) nanotechnology
 Nano-processors with declining energy
 Ultra-small terra-bit level storage
 GHz frequency and bandwidth
 Integrated nano-sensors