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DVLSI_project_presentation_template.pptx

24 Mar 2023
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DVLSI_project_presentation_template.pptx

  1. E0 284: Digital VLSI Circuits Project: Title Name Author Program (Micro/ESE – please expand it) Indian Institute of Science (IISc), Bangalore 1
  2. Introduction 2 • Problem Statement • Dataset description • NOTE: Keep it to 1 slide.
  3. Network Description 3 • Network architecture [feed-forward, fully connected] • Network parameters - Number of Inputs, outputs, number of neurons in hidden layer, activation function for hidden layer, output format • NOTE: Keep it to 1 slide.
  4. Software Implementation 4 • Tasks you performed on MATLAB. • Highlight any optimizations you performed on given code. • Fixed point design approach: • Bit widths allocated for integer and fraction part. • Total memory needed for weights and biases (in bits). • Size of multiplier needed (Ex: 8 bit x 8 bit) • Scripting to get HW compatible data. • NOTE: Do not add any accuracy results here, there is a section for that later.
  5. LFSR Implementation 5 • Algorithm used to implement LFSR in Verilog/MATLAB. • Block diagram of LFSR.
  6. Hardware Specifications 6 • Frequency of operation • Latency – For 1 input image, measure the total cycles needed to complete the processing – from the clock cycle on which 1st part of input data is sent to design, till the cycle when output calculation is done and output can be read from design. • Initiation interval – Measure the minimum interval (in clock cycles) between 2 successive images being sent to HW such that they can be correctly recognized. • I/Os of your design in tabular form – with bit widths, direction, and description of the signals.
  7. Hardware Architecture 7 • Overall Block diagram of your design – showing all main sub-modules and data paths between them, and appropriate info (bit widths, signal names). • Describe in 1 line what each block does – Describe how inputs get processed to outputs/ what operation that block performs.
  8. Control FSM 8 • FSM diagram • Explain the control path very briefly – how many cycles does each state of the fsm take
  9. Hardware Schematic 9 • Picture of Schematic from Genus (post-synthesis)
  10. HW Simulation 10 • Description of testbench – How you are providing inputs to your design, how you are checking if output matches the expected value. • A sample picture of how the HW inputs looks like – if you have stored them in array, add a picture of part of that text file.
  11. HW Simulation 11 • Hidden Layer Output • Take a hidden layer neuron, show its output over a series of clock cycles in pre-synthesis simulation. • Compare it with MATLAB hidden layer output. • Justify your floating to fixed point conversion.
  12. Pre-synthesis Simulation Waveform 12 • Add picture of a sample simulation waveform of 1 input image (pre- synthesis) that has the important signals and captures from the moment input is provided to design till the output calculation is completed. • Add some labelling to help us understand what is happening.
  13. Post-synthesis Simulation Waveform 13 • Add picture of a sample simulation waveform 1 input image (post- synthesis) with the same input as earlier (pre-synth) picture for comparison. What is your conclusion from the 2 waveforms.
  14. Accuracy Results 14 • Software Accuracy: • Train data: • Testing with floating point weights: • Test data with fixed point weights: • Accuracy on HW: • Pre-synthesis: (10 images) • Post-synthesis: (same 10 images) • If there is an accuracy drop, why has it happened? • NOTE: Do not change this slide
  15. Synthesis Reports 15 • QOR and Power Reports from Synthesis.
  16. LEC Report 16 • Picture of LEC report, and your conclusion from it.
  17. Placement 17 • Picture of Placed Design
  18. Routing 18 • Picture of Routed Design
  19. Post-Routing Reports 19 • Setup and Hold Reports post-route • Power report • Geometry and Connectivity reports
  20. Design Highlights 20 • Describe key features/optimizations that you have done that can make your design stand out w.r.t. your peers.
  21. GDS 21 • Picture of successful GDS streamout from the terminal.
  22. Conclusions 22 • Number of neurons in hidden layer = • Accuracy on synthesized HW = • Clock Frequency = • Latency = • Initiation Interval = • Total Area = • Total Power (post-routing) = • Setup TNS and WNS (post-routing) = … and …. • Hold TNS and WNS (post-routing) = … and … • NOTE: Keep the format given here. Only fill the values
  23. Learning Outcomes 23 • What did you learn from this project? • NOTE: Keep it to 1 slide.
  24. 24 Thank You
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