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October 2019
PowerDRC / LVS
Advanced solution for physical verification of ICs
PV background2
o Physical Verification (PV) is a step in microchip design. The layout of a new device is
checked to find and fix errors before actual manufacturing
o The check is done by special EDA software - Design Rule Check (DRC) tool
o An error missing at this stage leads to creating malfunctioning microchip and costs
multi-million dollar losses for semiconductor manufacturers
o Another major factor is time. PV is one of the longest stages in the design process.
It may take several days for a DRC tool to make just one iteration on modern super
large microchips.
Corporate background
3
Founded in 2009 to develop the fastest & most accurate DRC technology
Privately held by KM Core (www.kmcore.com)
In 2015 launched POLYTEDA CLOUD spin-off to provide PowerDRC/LVS
operation in a cloud environment using innovative SaaS business model
(PVCLOUD)
World-wide presence:
o Headquarters, R&D and technical support team in Kiev, Ukraine
o Sales & Marketing provided by TEKSTART LLC (US, Taiwan, Israel, Japan),
Cadre Design System (India), Cogenda (China)
Our mission4
The main idea of PowerDRC/LVS is to speed up the
process of block-level and sign-off physical verification by
using One-Shot™ processing that delivers maximum hw
efficiency (CPU/RAM/disk) per one rule check
PowerDRC/LVS - advanced PV toolset5
DRC * - design rules checking in layout
LVS – layout vs schematic verification
RCX – parasitic extraction
NVN – schematic vs schematic netlists comparison
ERC – custom electrical rules checking (depends on foundry requirements)
XOR – full layer-by-layer comparison between two layouts
QuickDiff – diffing of layout versions to ensure ECO (engineering change
order)
Filler and mask layers generation (including text-based OPC)
(*) - PowerDRC supports antenna rules, density reports,
padring, latches and other special rules checking
PowerRDE – graphical debug
capabilities6
Graphical visualization of DRC violations or XOR discrepancies
LVS cross-probing with schematic
Highlighting of LVS extraction errors: open nets, multilabeled nets, floating
labels, malformed devices
Highlighting of parasitic devices
Highlighting of shorted nets via PowerLVS Short-Finder utility
7
Core technology
Window
Scanning
Unleashing
One-shot Processing
Unique, encapsulation
of rules, layers &
operations
 Combines multiple rules/layers checks
 Small and efficient memory footprint
 Processing by strips for multi-CPU
 Hierarchical processing of cell arrays and macro cells
 Processing speed is ~8-9 million transistors per hour per 1 CPU core
PowerDRC
8
Silicon-proven: almost all process nodes above 40nm inclusively
Effective at 32nm and 28nm
Fastest and most accurate natively flat DRC engine on the market
Predictable performance and behavior
Multi-CPU and hierarchical operations for linear performance gain
Parallel processing
9
PowerDRC benefits from parallel processing of:
Independent groups of rules (blocks)
Independent parts of layout (strips)
Blocks + strips combined together
Parallel tasks may be run in multi-CPU mode on:
A single host
PVCLOUD service (Amazon AWS platform)
Custom private cloud platform
Scalability proven with up to 128 CPUs
PowerLVS
10
Supports 7 effective comparison algorithms applied automatically depending
on the type of encountered blocks to ensure accuracy at the highest level of
performance
Silicon-proven: almost all process nodes above 40nm inclusively
Predictable performance and behavior
Supports extraction of array instances to get up to 10x performance increase
Provides Multi-label, Floating-label, Hier cells and Open nets reports
Graphical debug is provided by PowerRDE and Short Finder utility
PowerRCX – unique approach
11
PowerRCX provides extraction of parasitic devices with sufficiently high
accuracy without need for preliminary tuning of parameters with an 3rd-party
solver. Supports extraction in R, C and RC modes
Supports extraction of overlap (area), line-to-line coupling and fringe
capacitances
Silicon-proven: 250nm, 180nm, 150nm, 130nm
Accuracy matched against industry golden tools
Output SPICE netlist compatible
Graphical debug is provided by PowerRDE
Fab1 test 1
12
11300
3595
1625
1111
839
805
0 2000 4000 6000 8000 10000 12000
1 CPU Flat mode
8 CPU Flat mode
16 CPUs Flat mode
32 CPUs Flat mode
32 CPUs Hier mode
64 CPUs Flat mode
1 CPU Flat mode 8 CPU Flat mode 16 CPUs Flat mode 32 CPUs Flat mode 32 CPUs Hier mode 64 CPUs Flat mode
Sec 11300 3595 1625 1111 839 805
Chip A
Test name CHIP A
GDS size 660 MB
Area ~45 sq. mm
Specifics Standard logic, 6 metals
Process node 180 nm
Hardware configuration: 4 x Intel Xeon E5-2686 2.3GHz (64 CPU cores) , RAM: 128GB HDD: 10GB SAS+ 150GB
Software configuration: CentOS 7 64 bit, PowerDRC/LVS version: 2.5.0
Fab1 test 2
13
720
214
126
98
62
0 100 200 300 400 500 600 700 800
1 CPU Flat mode
8 CPUs Flat mode
16 CPUs Flat mode
32 CPUs Flat mode
64 CPUs Flat mode
1 CPU Flat mode 8 CPUs Flat mode 16 CPUs Flat mode 32 CPUs Flat mode 64 CPUs Flat mode
Sec 720 214 126 98 62
Chip B
Test name CHIP B
GDS size 160 MB
Area ~5 sq. mm
Specifics Power management, 4 metals
Process node 180 nm
Hardware configuration: 4 x Intel Xeon E5-2686 2.3GHz (64 CPU cores) , RAM: 128GB, HDD: 10GB SAS+ 150GB
Software configuration: CentOS 7 64 bit, PowerDRC/LVS version: 2.5.0
Fab2 test1
14
810
146
88
29
0 100 200 300 400 500 600 700 800 900
1 CPU Flat mode
8 CPU Flat mode
16 CPUs Flat mode
32 CPUs Flat mode
1 CPU Flat mode 8 CPU Flat mode 16 CPUs Flat mode 32 CPUs Flat mode
Sec 810 146 88 29
Chip B
Test name CHIP B
GDS size 15 MB, ~4 mln devices
Area ~20 sq. mm
Specifics 3xDRAM+3xBISTs+padring, 3 metal
Process node 250 nm
Hardware configuration: 4 x Intel Xeon E5-2686 2.3GHz (64 CPU cores), RAM: 128GB, HDD: 10GB SAS+ 150GB
Software configuration: CentOS 7 64 bit, PowerDRC/LVS version: 2.5.0
PowerLVS performance
15
Design specifics Extraction Comparison Total LVS time
40nm LP: analog blocks, logic gates and
memory arrays, ~ 500 million physical gates
14 h 12 h 26 h
250nm : baseband + pads, ~ 500K devices 17 min 11 min ~0.5 h
4nm custom: LCD 1440x1080 -analog blocks,
multi-layer memory arrays,
~ 50 million devices
3.5 h 1 min 3h 31min
Hardware configuration: Intel Xeon E5-2686 2.3GHz (available logical CPU cores: 1), RAM: 128GB,
HDD: 10GB SAS+ 150GB
Software configuration: CentOS 7 64 bit, PowerDRC/LVS version: 2.5.0
Unique features
Advantages from using efficient FLAT engine natively
Extremely efficient usage of hardware resources (RAM,
cache, CPU load)
Predictable performance
16
Run and Debug Environment (PowerRDE)
17
Allows user to:
Adjust DRC and LVS run parameters
Save/read run configuration
Run PowerDRC/LVS
View run progress
Review results
Debug violations, etc.
PowerDRC/LVS integration
18
PowerDRC/LVS has interoperability
with:
Cadence Virtuoso – CDBA and OA
NI-AWR Analog Office - native
KLayout – native
Symica DE – native and OA
ADS Keysight – native and OA
TexEDA LayTOOLs – native
Juspertor LayoutEditor – native and
OA
Supported foundry runsets
20
Sign-Off 40nm (G, LP)
65nm (LL, LP, SP)
180nm(G, LL)
180nm TS18
(SL, PM, RF, IS)
250nm
(SGB25V, SGH24H4)
130nm
(SG13S/G2)
180nm
(XH018, XS018)
350nm
(XH035, XA035)
250nm
500nm
(GX, FX)
Educational &
University
kits
MOSIS SCMOS FreePDK45
FreePDK15
500-180nm 45nm-15nm
• To check availability of other rule sets
please contact POLYTEDA directly
To get hand-on experience
Order a trial desktop version of PowerDRC/LVS online at:
www.polyteda.com/contact-us/submitrequest
Or try for free the innovative PVCLOUD product (SaaS) at:
www.polyteda-cloud.com
PowerDRC/LVS 2.5 is officially available from POLYTEDA since July 18, 2019
21
Licensing
o PowerDRC/LVS is licensed on per-CPU basis separately for DRC and LVS
o PowerRDE GUI cockpit, filler layers generation, XOR and QuickDiff operations, OPC
mask generation, and parasitic extraction require their own license each
o Licensing employs FlexLM license manager
o Licenses are bound either to hostID (MAC-address), or disk serial number, or dongle
flexID
o Licenses are valid for all minor version updates, i.e. license for 2.5 is valid for 2.5.1 but
not for 2.6
o Usual license durations: 3 months, 6 months, 1 year, 3 years
o Short-term licenses may be granted for trial or educational purposes
22
Support policy
o POLYTEDA is ready to provide offline (email) technical support based on
additional Support and Maintenance Agreement (available)
o In urgent cases a hot fix version may be sent to the customer as soon as
the issue is solved
o Migration from the most of competitive rule sets is a matter of days
23
Physical Verification services
o Custom rule deck development
o Contract sign-off checking of ICs
o Physical Verification as SaaS (via PVCLOUD)
o Supplementary tailored solutions
24

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POLYTEDA PowerDRC/LVS overview

  • 1. October 2019 PowerDRC / LVS Advanced solution for physical verification of ICs
  • 2. PV background2 o Physical Verification (PV) is a step in microchip design. The layout of a new device is checked to find and fix errors before actual manufacturing o The check is done by special EDA software - Design Rule Check (DRC) tool o An error missing at this stage leads to creating malfunctioning microchip and costs multi-million dollar losses for semiconductor manufacturers o Another major factor is time. PV is one of the longest stages in the design process. It may take several days for a DRC tool to make just one iteration on modern super large microchips.
  • 3. Corporate background 3 Founded in 2009 to develop the fastest & most accurate DRC technology Privately held by KM Core (www.kmcore.com) In 2015 launched POLYTEDA CLOUD spin-off to provide PowerDRC/LVS operation in a cloud environment using innovative SaaS business model (PVCLOUD) World-wide presence: o Headquarters, R&D and technical support team in Kiev, Ukraine o Sales & Marketing provided by TEKSTART LLC (US, Taiwan, Israel, Japan), Cadre Design System (India), Cogenda (China)
  • 4. Our mission4 The main idea of PowerDRC/LVS is to speed up the process of block-level and sign-off physical verification by using One-Shot™ processing that delivers maximum hw efficiency (CPU/RAM/disk) per one rule check
  • 5. PowerDRC/LVS - advanced PV toolset5 DRC * - design rules checking in layout LVS – layout vs schematic verification RCX – parasitic extraction NVN – schematic vs schematic netlists comparison ERC – custom electrical rules checking (depends on foundry requirements) XOR – full layer-by-layer comparison between two layouts QuickDiff – diffing of layout versions to ensure ECO (engineering change order) Filler and mask layers generation (including text-based OPC) (*) - PowerDRC supports antenna rules, density reports, padring, latches and other special rules checking
  • 6. PowerRDE – graphical debug capabilities6 Graphical visualization of DRC violations or XOR discrepancies LVS cross-probing with schematic Highlighting of LVS extraction errors: open nets, multilabeled nets, floating labels, malformed devices Highlighting of parasitic devices Highlighting of shorted nets via PowerLVS Short-Finder utility
  • 7. 7 Core technology Window Scanning Unleashing One-shot Processing Unique, encapsulation of rules, layers & operations  Combines multiple rules/layers checks  Small and efficient memory footprint  Processing by strips for multi-CPU  Hierarchical processing of cell arrays and macro cells  Processing speed is ~8-9 million transistors per hour per 1 CPU core
  • 8. PowerDRC 8 Silicon-proven: almost all process nodes above 40nm inclusively Effective at 32nm and 28nm Fastest and most accurate natively flat DRC engine on the market Predictable performance and behavior Multi-CPU and hierarchical operations for linear performance gain
  • 9. Parallel processing 9 PowerDRC benefits from parallel processing of: Independent groups of rules (blocks) Independent parts of layout (strips) Blocks + strips combined together Parallel tasks may be run in multi-CPU mode on: A single host PVCLOUD service (Amazon AWS platform) Custom private cloud platform Scalability proven with up to 128 CPUs
  • 10. PowerLVS 10 Supports 7 effective comparison algorithms applied automatically depending on the type of encountered blocks to ensure accuracy at the highest level of performance Silicon-proven: almost all process nodes above 40nm inclusively Predictable performance and behavior Supports extraction of array instances to get up to 10x performance increase Provides Multi-label, Floating-label, Hier cells and Open nets reports Graphical debug is provided by PowerRDE and Short Finder utility
  • 11. PowerRCX – unique approach 11 PowerRCX provides extraction of parasitic devices with sufficiently high accuracy without need for preliminary tuning of parameters with an 3rd-party solver. Supports extraction in R, C and RC modes Supports extraction of overlap (area), line-to-line coupling and fringe capacitances Silicon-proven: 250nm, 180nm, 150nm, 130nm Accuracy matched against industry golden tools Output SPICE netlist compatible Graphical debug is provided by PowerRDE
  • 12. Fab1 test 1 12 11300 3595 1625 1111 839 805 0 2000 4000 6000 8000 10000 12000 1 CPU Flat mode 8 CPU Flat mode 16 CPUs Flat mode 32 CPUs Flat mode 32 CPUs Hier mode 64 CPUs Flat mode 1 CPU Flat mode 8 CPU Flat mode 16 CPUs Flat mode 32 CPUs Flat mode 32 CPUs Hier mode 64 CPUs Flat mode Sec 11300 3595 1625 1111 839 805 Chip A Test name CHIP A GDS size 660 MB Area ~45 sq. mm Specifics Standard logic, 6 metals Process node 180 nm Hardware configuration: 4 x Intel Xeon E5-2686 2.3GHz (64 CPU cores) , RAM: 128GB HDD: 10GB SAS+ 150GB Software configuration: CentOS 7 64 bit, PowerDRC/LVS version: 2.5.0
  • 13. Fab1 test 2 13 720 214 126 98 62 0 100 200 300 400 500 600 700 800 1 CPU Flat mode 8 CPUs Flat mode 16 CPUs Flat mode 32 CPUs Flat mode 64 CPUs Flat mode 1 CPU Flat mode 8 CPUs Flat mode 16 CPUs Flat mode 32 CPUs Flat mode 64 CPUs Flat mode Sec 720 214 126 98 62 Chip B Test name CHIP B GDS size 160 MB Area ~5 sq. mm Specifics Power management, 4 metals Process node 180 nm Hardware configuration: 4 x Intel Xeon E5-2686 2.3GHz (64 CPU cores) , RAM: 128GB, HDD: 10GB SAS+ 150GB Software configuration: CentOS 7 64 bit, PowerDRC/LVS version: 2.5.0
  • 14. Fab2 test1 14 810 146 88 29 0 100 200 300 400 500 600 700 800 900 1 CPU Flat mode 8 CPU Flat mode 16 CPUs Flat mode 32 CPUs Flat mode 1 CPU Flat mode 8 CPU Flat mode 16 CPUs Flat mode 32 CPUs Flat mode Sec 810 146 88 29 Chip B Test name CHIP B GDS size 15 MB, ~4 mln devices Area ~20 sq. mm Specifics 3xDRAM+3xBISTs+padring, 3 metal Process node 250 nm Hardware configuration: 4 x Intel Xeon E5-2686 2.3GHz (64 CPU cores), RAM: 128GB, HDD: 10GB SAS+ 150GB Software configuration: CentOS 7 64 bit, PowerDRC/LVS version: 2.5.0
  • 15. PowerLVS performance 15 Design specifics Extraction Comparison Total LVS time 40nm LP: analog blocks, logic gates and memory arrays, ~ 500 million physical gates 14 h 12 h 26 h 250nm : baseband + pads, ~ 500K devices 17 min 11 min ~0.5 h 4nm custom: LCD 1440x1080 -analog blocks, multi-layer memory arrays, ~ 50 million devices 3.5 h 1 min 3h 31min Hardware configuration: Intel Xeon E5-2686 2.3GHz (available logical CPU cores: 1), RAM: 128GB, HDD: 10GB SAS+ 150GB Software configuration: CentOS 7 64 bit, PowerDRC/LVS version: 2.5.0
  • 16. Unique features Advantages from using efficient FLAT engine natively Extremely efficient usage of hardware resources (RAM, cache, CPU load) Predictable performance 16
  • 17. Run and Debug Environment (PowerRDE) 17 Allows user to: Adjust DRC and LVS run parameters Save/read run configuration Run PowerDRC/LVS View run progress Review results Debug violations, etc.
  • 18. PowerDRC/LVS integration 18 PowerDRC/LVS has interoperability with: Cadence Virtuoso – CDBA and OA NI-AWR Analog Office - native KLayout – native Symica DE – native and OA ADS Keysight – native and OA TexEDA LayTOOLs – native Juspertor LayoutEditor – native and OA
  • 19. Supported foundry runsets 20 Sign-Off 40nm (G, LP) 65nm (LL, LP, SP) 180nm(G, LL) 180nm TS18 (SL, PM, RF, IS) 250nm (SGB25V, SGH24H4) 130nm (SG13S/G2) 180nm (XH018, XS018) 350nm (XH035, XA035) 250nm 500nm (GX, FX) Educational & University kits MOSIS SCMOS FreePDK45 FreePDK15 500-180nm 45nm-15nm • To check availability of other rule sets please contact POLYTEDA directly
  • 20. To get hand-on experience Order a trial desktop version of PowerDRC/LVS online at: www.polyteda.com/contact-us/submitrequest Or try for free the innovative PVCLOUD product (SaaS) at: www.polyteda-cloud.com PowerDRC/LVS 2.5 is officially available from POLYTEDA since July 18, 2019 21
  • 21. Licensing o PowerDRC/LVS is licensed on per-CPU basis separately for DRC and LVS o PowerRDE GUI cockpit, filler layers generation, XOR and QuickDiff operations, OPC mask generation, and parasitic extraction require their own license each o Licensing employs FlexLM license manager o Licenses are bound either to hostID (MAC-address), or disk serial number, or dongle flexID o Licenses are valid for all minor version updates, i.e. license for 2.5 is valid for 2.5.1 but not for 2.6 o Usual license durations: 3 months, 6 months, 1 year, 3 years o Short-term licenses may be granted for trial or educational purposes 22
  • 22. Support policy o POLYTEDA is ready to provide offline (email) technical support based on additional Support and Maintenance Agreement (available) o In urgent cases a hot fix version may be sent to the customer as soon as the issue is solved o Migration from the most of competitive rule sets is a matter of days 23
  • 23. Physical Verification services o Custom rule deck development o Contract sign-off checking of ICs o Physical Verification as SaaS (via PVCLOUD) o Supplementary tailored solutions 24

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