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1. ARM
 The ARM processor core is a key component of many successful
32-bit embedded systems.
 RISC (reduced instruction set computer) design philosophy was
adapted by ARM to create a flexible embedded processor.
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2. SYNOPSIS
 ROLE OF ARM
 WHY ARM?
 RISC
 RISC VS CISC
 ARM FAMILIES
 ARM REGISTERS
 THUMB
 EXCEPTION
 ARCHITECTURE OF ARM
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3. ROLE OF ARM CO.
 ARM HOLDINGS is a technology company situated in
Cambridge,England,UK.
 The Company is best known for its processors,and it also designs
software development tools such as KEIL,REALVIEW.
 ARM do not make IC’s.
 Examples:LPC2148 from NXP,AT91RM9200 from ATMEL
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4. WHY ARM PROCESSOR ARE USED?
 Arm Processor can be used in any domain.
 Because of their reduced instruction set, they require fewer transistors,
which enables a smaller die size for the integrated circuitry (IC).
 ARM processor reduces complexity
 Easy to simulate
 Low power consumption makes it suitable for miniaturised devices.
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5. RISC
 RISC is a design philosophy aimed at delivering simple but powerful
instructions that execute within a single cycle at a high clock speed.
 The RISC philosophy concentrates on reducing the complexity of
instructions performed by the hardware because it is easier to provide
greater flexibility and intelligence in software rather than hardware.
 The RISC philosophy is implemented with four major design rules:
o Instructions
o Pipelines
o Registers
o Load store architecture
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6. COMPILER
processor processor
COMPILER
Greater
Complexity
Greater
Complexity
Code
Generation
Code
Generation
CISC vs. RISC
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7. ARM NOMENCLATURE:
ARM{x}{y}{z}{T}{D}{M}{I}{E}{J}{F}{-S}
x—family
y—memory management/protection unit
z—cache
T—Thumb 16-bit decoder
D—JTAG debug
M—fast multiplier
I—Embedded ICE macrocell
E—enhanced instructions (assumes TDMI)
J— Jazelle
F—vector floating-point unit
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8. ARM VERSIONS
 ARM7TDMI
 STRONG ARM
 ARM9
 ARM9TDMI,ARM9E
 ARM 10E
 ARM11
 Cortex-A for application process for high end running >1Ghz
 Cortex-R for real time process for mid range 400-600 Mhz
 Cortex-M for microcontroller for lower range <200 Mhz
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9. 9
ARM
FAMILY
YEAR OF
RELEASE
ARCHITECTURE PIPELINE FREQUENCY MULTIPLIER
ARM 7 1995 VON NEUMANN 3 STAGE 80MHZ 8X32
ARM 9 1997 HARVARD 5 STAGE 150MHZ 8X32
ARM 10 1999 HARVARD 6 STAGE 260MHZ 16X32
ARM 11 2003 HARVARD 8 STAGE 335MHZ 16X32

10. ARM PROCESSOR FAMILIES
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11. ARM APPLICATIONS
 CORTEX A SERIES APPLICATIONS:
• Smartphones
• Digital TV
• Servers and networking
 CORTEX R SERIES APPLICATIONS:
 Automotive Braking systems
 Powertrain solutions
 Mass storage controller
 CORTEX M SERIES APPLICATIONS:
 Micro controllers
 Mixed signal devices
 Smart sensors
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12. THUMB
 The Thumb is subset of the ARM instruction set.
 Thumb instructions are half the size of ARM instructions (16 bits
compared with 32 bits).
 However, the Thumb instruction set does have some limitations:
 Thumb code usually uses more instructions , making ARM code best for
maximizing performance of time-critical code.
 ARM state and some associated ARM instructions are required for
exception handling.
 The Thumb instruction set is always used in conjunction with a version
of the ARM instruction set.
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13. EXCEPTION
 Exceptions are generated by internal and external sources to cause the
processor to handle an event , such as an externally generated
interrupt or an attempt to execute an Undefined instruction.
 Exceptions processing modes:
Exception Mode Purpose
Fast Interrupt Request FIQ Fast Interrupt Handling
Interrupt Request IRQ Normal Interrupt Handling
SWI and RESET SVC Protected Mode for OS
Prefetch and Data Abort ABT Memory Protection Handling
Undefined Instructions UND SW emulation of HW
coprocessing

14. Exception Priorities
 RESET
 DATA ABORT
 FIQ
 IRQ
 PREFETCH ABORT
 SWI ,UNDEFINED INSTRUCTION
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HIGH
LOW

15. ARM REGISTERS
 ARM has 31 general-purpose 32-bit registers.
 At any one time, 16 of these registers are visible.
 The other registers are used to speed up exception processing.
Three of the 16 visible registers have special roles:
 Stack pointer Software normally uses R13 as a Stack Pointer (SP).
 Link register Register 14 is the Link Register (LR).
 Program counter Register 15 is the Program Counter (PC).
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16. GENERAL PURPOSE REGISTERS
 The general-purpose registers R0 to R15 can be split into three
groups.
 These groups differ in the way they are banked and in their special-
purpose uses:
 The unbanked registers, R0 to R7
 The banked registers, R8 to R14
 Register 15 is the program counter.
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17. Program status Registers
 The Current Program Status Register (CPSR) is accessible in all
processor modes.
 It contains condition code flags, interrupt disable bits, the current
processor mode, and other status and control information.
 Each exception mode also has a Saved Program Status Register
(SPSR), that is used to preserve the value of the CPSR when the
associated exception occurs.
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18. The format of the CPSR and the SPSRs
N Z C V Q RES J RESV GE[3:0] RESV
E A I F T M[4:0]
31 30 29 28 27 26 25 24 23 20 19 16 15
10 9 8 7 6 5 4 0
N = Negative result from ALU flag.
Z = Zero result from ALU flag.
C = ALU operation Carried out
V = ALU operation overflowed
* Interrupt Disable bits.
I = 1, disables the IRQ.
F = 1, disables the FIQ.
* T Bit (Architecture v4T only)
T = 0, Processor in ARM state
T = 1, Processor in Thumb state
Copies of the ALU status flags (latched if the
instruction has the "S" bit set).
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19. THE INSTRUCTION PIPELINE
 The ARM uses a pipeline in order to increase the speed of the
flow of instructions to the processor.
 Allows several operations to be undertaken simultaneously,
rather than serially.
FETCH
DECODE
EXECUTE
Instruction fetched from memory
Decoding of registers used in instruction
Register(s) read from Register Bank
Shift and ALU operation
Write register(s) back to Register Bank
PC
PC - 4
PC - 8
ARM
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20. ARM ARCHITECTURE
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21. ARM ARCHITECTURE FEATURES
 Simple addressing modes
 Uniform and fixed-length instruction fields
 A large uniform register file
 Control over both the Arithmetic Logic Unit (ALU) and shifter in
most data-processing instructions
 Load and Store Multiple instructions to maximize data throughput
 Conditional execution to maximize execution throughput.
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22. ARM bus
 AMBA:(Advanced Microcontroller Bus Architecture)
-Open standard.
-Many external
devices.
 Varieties of AMBA:
AMBA High-Performance Bus(AHB) in 2000A simple transaction on the AHB
consists of an address phase and a subsequent data phase
AMBA PeripheralsBus (APB).APB is designed for low bandwidth control
accesses.
AMBA AXI(2005)Advanced eXtensible Interface for even higher performance
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23. ARM PERIPHERALS
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