SlideShare a Scribd company logo
1 of 14
Kenyon Tsai
2016.06.22
An overview of PCI Express Physical Layer
Technology
ASMedia Confidential DocumentASMedia Confidential Document
Introduction
ASMedia Confidential DocumentASMedia Confidential Document
Introduction
 Lane count : x1, x2, x4, x8, x12, x16 and x32
 Rate :
Raw bit rate Link BW
PCIe 1.x 2.5 Gigabits/s 2 Gb/s
PCIe 2.x 5 Gigabits/s 4 Gb/s
PCIe 3.x 8 Gigabits/s ~8 Gb/s
PCIe 4 16 Gigabits/s ~16 Gb/s
ASMedia Confidential DocumentASMedia Confidential Document
PCIe Layering Overview
 There are three discrete logical layers
 Transaction Layer
 Data Link Layer
 Physical Layer
ASMedia Confidential DocumentASMedia Confidential Document
Physical Layer
 The Physical Layer is divided into two blocks
 Logical sub-blocks
 Electrical sub-blocks
Physical Layer
Logical sub-blocks
Electrical sub-blocks
ASMedia Confidential DocumentASMedia Confidential Document
8b/10b encoding
 Purpose of 8b/10b encoding
 To achieve DC-balance
 Provide enough state changes to allow reasonable clock recovery
ASMedia Confidential DocumentASMedia Confidential Document
Data Scrambling
 Purposes of scrambling
 For energy dispersal on the carrier
 Reducing inter-carrier signal interference
ASMedia Confidential DocumentASMedia Confidential Document
De-emphasis
 Definition of De-emphasis
ASMedia Confidential DocumentASMedia Confidential Document
De-emphasis
 Purposes of De-emphasis
 To compensate Inter-symbol interference
ASMedia Confidential DocumentASMedia Confidential Document
De-emphasis
 Purposes of De-emphasis
 To compensate Inter-symbol interference
ASMedia Confidential DocumentASMedia Confidential Document
Link training
 Training Does
 Link data rate negotiation
 Bit lock per Lane
 Lane polarity
 Symbol lock per Lane
 Lane ordering within a Link
 Link width negotiation
 Lane-to-Lane de-skew within a multi-Lane Link
ASMedia Confidential DocumentASMedia Confidential Document
Link training
 Link Training and Status State Machine (LTSSM) Descriptions
ASMedia Confidential DocumentASMedia Confidential Document
Link training - Detect
 To detect when a far end termination is present
ASMedia Confidential DocumentASMedia Confidential Document
Thanks

More Related Content

What's hot

Verification Strategy for PCI-Express
Verification Strategy for PCI-ExpressVerification Strategy for PCI-Express
Verification Strategy for PCI-ExpressDVClub
 
Difference between PCI PCI-X PCIe
Difference between PCI PCI-X PCIeDifference between PCI PCI-X PCIe
Difference between PCI PCI-X PCIeSUNODH GARLAPATI
 
PCI Express Verification using Reference Modeling
PCI Express Verification using Reference ModelingPCI Express Verification using Reference Modeling
PCI Express Verification using Reference ModelingDVClub
 
03_03_Implementing_PCIe_ATS_in_ARM-based_SoCs_Final
03_03_Implementing_PCIe_ATS_in_ARM-based_SoCs_Final03_03_Implementing_PCIe_ATS_in_ARM-based_SoCs_Final
03_03_Implementing_PCIe_ATS_in_ARM-based_SoCs_FinalGopi Krishnamurthy
 
44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick
44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick
44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick44CON
 
AMBA 3 APB Protocol
AMBA 3 APB ProtocolAMBA 3 APB Protocol
AMBA 3 APB ProtocolSwetha GSM
 
Amba axi 29 3_2015
Amba axi 29 3_2015Amba axi 29 3_2015
Amba axi 29 3_2015kiemnhatminh
 
AMBA 5 COHERENT HUB INTERFACE.pptx
AMBA 5 COHERENT HUB INTERFACE.pptxAMBA 5 COHERENT HUB INTERFACE.pptx
AMBA 5 COHERENT HUB INTERFACE.pptxSairam Chebrolu
 

What's hot (20)

Pci express modi
Pci express modiPci express modi
Pci express modi
 
PCI express
PCI expressPCI express
PCI express
 
Verification Strategy for PCI-Express
Verification Strategy for PCI-ExpressVerification Strategy for PCI-Express
Verification Strategy for PCI-Express
 
Pcie drivers basics
Pcie drivers basicsPcie drivers basics
Pcie drivers basics
 
Difference between PCI PCI-X PCIe
Difference between PCI PCI-X PCIeDifference between PCI PCI-X PCIe
Difference between PCI PCI-X PCIe
 
axi protocol
axi protocolaxi protocol
axi protocol
 
PCI Express Verification using Reference Modeling
PCI Express Verification using Reference ModelingPCI Express Verification using Reference Modeling
PCI Express Verification using Reference Modeling
 
Ambha axi
Ambha axiAmbha axi
Ambha axi
 
PCIe DL_layer_3.0.1 (1)
PCIe DL_layer_3.0.1 (1)PCIe DL_layer_3.0.1 (1)
PCIe DL_layer_3.0.1 (1)
 
03_03_Implementing_PCIe_ATS_in_ARM-based_SoCs_Final
03_03_Implementing_PCIe_ATS_in_ARM-based_SoCs_Final03_03_Implementing_PCIe_ATS_in_ARM-based_SoCs_Final
03_03_Implementing_PCIe_ATS_in_ARM-based_SoCs_Final
 
Axi protocol
Axi protocolAxi protocol
Axi protocol
 
44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick
44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick
44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick
 
CPU Verification
CPU VerificationCPU Verification
CPU Verification
 
AMBA Ahb 2.0
AMBA Ahb 2.0AMBA Ahb 2.0
AMBA Ahb 2.0
 
Axi
AxiAxi
Axi
 
AMBA 3 APB Protocol
AMBA 3 APB ProtocolAMBA 3 APB Protocol
AMBA 3 APB Protocol
 
Axi protocol
Axi protocolAxi protocol
Axi protocol
 
Axi
AxiAxi
Axi
 
Amba axi 29 3_2015
Amba axi 29 3_2015Amba axi 29 3_2015
Amba axi 29 3_2015
 
AMBA 5 COHERENT HUB INTERFACE.pptx
AMBA 5 COHERENT HUB INTERFACE.pptxAMBA 5 COHERENT HUB INTERFACE.pptx
AMBA 5 COHERENT HUB INTERFACE.pptx
 

Viewers also liked

Identifying PCIe 3.0 Dynamic Equalization Problems
Identifying PCIe 3.0 Dynamic Equalization ProblemsIdentifying PCIe 3.0 Dynamic Equalization Problems
Identifying PCIe 3.0 Dynamic Equalization Problemsteledynelecroy
 
Moving to PCI Express based SSD with NVM Express
Moving to PCI Express based SSD with NVM ExpressMoving to PCI Express based SSD with NVM Express
Moving to PCI Express based SSD with NVM ExpressOdinot Stanislas
 
Design of all digital phase locked loop (d pll) with fast acquisition time
Design of all digital phase locked loop (d pll) with fast acquisition timeDesign of all digital phase locked loop (d pll) with fast acquisition time
Design of all digital phase locked loop (d pll) with fast acquisition timeeSAT Journals
 
PCI Express* based Storage: Data Center NVM Express* Platform Topologies
PCI Express* based Storage: Data Center NVM Express* Platform TopologiesPCI Express* based Storage: Data Center NVM Express* Platform Topologies
PCI Express* based Storage: Data Center NVM Express* Platform TopologiesOdinot Stanislas
 
Formation pcie excel partie 1
Formation pcie excel partie 1Formation pcie excel partie 1
Formation pcie excel partie 1OneIDlille
 
Fcamp may2010-tech2-fpga high speed io trends-alteraTrends & Challenges in De...
Fcamp may2010-tech2-fpga high speed io trends-alteraTrends & Challenges in De...Fcamp may2010-tech2-fpga high speed io trends-alteraTrends & Challenges in De...
Fcamp may2010-tech2-fpga high speed io trends-alteraTrends & Challenges in De...FPGA Central
 
Hands-on Lab: How to Unleash Your Storage Performance by Using NVM Express™ B...
Hands-on Lab: How to Unleash Your Storage Performance by Using NVM Express™ B...Hands-on Lab: How to Unleash Your Storage Performance by Using NVM Express™ B...
Hands-on Lab: How to Unleash Your Storage Performance by Using NVM Express™ B...Odinot Stanislas
 
Scale-out Storage on Intel® Architecture Based Platforms: Characterizing and ...
Scale-out Storage on Intel® Architecture Based Platforms: Characterizing and ...Scale-out Storage on Intel® Architecture Based Platforms: Characterizing and ...
Scale-out Storage on Intel® Architecture Based Platforms: Characterizing and ...Odinot Stanislas
 
Userspace Linux I/O
Userspace Linux I/O Userspace Linux I/O
Userspace Linux I/O Garima Kapoor
 
Webinar: How NVMe Will Change Flash Storage
Webinar: How NVMe Will Change Flash StorageWebinar: How NVMe Will Change Flash Storage
Webinar: How NVMe Will Change Flash StorageStorage Switzerland
 
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case Study
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyTraditional vs. SoC FPGA Design Flow A Video Pipeline Case Study
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
 
Hardware accelerated virtio networking for nfv linux con
Hardware accelerated virtio networking for nfv linux conHardware accelerated virtio networking for nfv linux con
Hardware accelerated virtio networking for nfv linux consprdd
 
NVMe PCIe and TLC V-NAND It’s about Time
NVMe PCIe and TLC V-NAND It’s about TimeNVMe PCIe and TLC V-NAND It’s about Time
NVMe PCIe and TLC V-NAND It’s about TimeDell World
 
DPDK в виртуальном коммутаторе Open vSwitch / Александр Джуринский (Selectel)
DPDK в виртуальном коммутаторе Open vSwitch / Александр Джуринский (Selectel)DPDK в виртуальном коммутаторе Open vSwitch / Александр Джуринский (Selectel)
DPDK в виртуальном коммутаторе Open vSwitch / Александр Джуринский (Selectel)Ontico
 
Function Level Analysis of Linux NVMe Driver
Function Level Analysis of Linux NVMe DriverFunction Level Analysis of Linux NVMe Driver
Function Level Analysis of Linux NVMe Driver인구 강
 

Viewers also liked (18)

Identifying PCIe 3.0 Dynamic Equalization Problems
Identifying PCIe 3.0 Dynamic Equalization ProblemsIdentifying PCIe 3.0 Dynamic Equalization Problems
Identifying PCIe 3.0 Dynamic Equalization Problems
 
Moving to PCI Express based SSD with NVM Express
Moving to PCI Express based SSD with NVM ExpressMoving to PCI Express based SSD with NVM Express
Moving to PCI Express based SSD with NVM Express
 
Design of all digital phase locked loop (d pll) with fast acquisition time
Design of all digital phase locked loop (d pll) with fast acquisition timeDesign of all digital phase locked loop (d pll) with fast acquisition time
Design of all digital phase locked loop (d pll) with fast acquisition time
 
PCI Express* based Storage: Data Center NVM Express* Platform Topologies
PCI Express* based Storage: Data Center NVM Express* Platform TopologiesPCI Express* based Storage: Data Center NVM Express* Platform Topologies
PCI Express* based Storage: Data Center NVM Express* Platform Topologies
 
Formation pcie excel partie 1
Formation pcie excel partie 1Formation pcie excel partie 1
Formation pcie excel partie 1
 
An Effective Design and Verification Methodology for Digital PLL
An Effective Design and Verification Methodology for Digital PLLAn Effective Design and Verification Methodology for Digital PLL
An Effective Design and Verification Methodology for Digital PLL
 
89HT0832P 16-lane 8 Gbps PCIe 3.0 Retimer by IDT
89HT0832P 16-lane 8 Gbps PCIe 3.0 Retimer by IDT89HT0832P 16-lane 8 Gbps PCIe 3.0 Retimer by IDT
89HT0832P 16-lane 8 Gbps PCIe 3.0 Retimer by IDT
 
HP_NextGEN_Training_Q4_2015
HP_NextGEN_Training_Q4_2015HP_NextGEN_Training_Q4_2015
HP_NextGEN_Training_Q4_2015
 
Fcamp may2010-tech2-fpga high speed io trends-alteraTrends & Challenges in De...
Fcamp may2010-tech2-fpga high speed io trends-alteraTrends & Challenges in De...Fcamp may2010-tech2-fpga high speed io trends-alteraTrends & Challenges in De...
Fcamp may2010-tech2-fpga high speed io trends-alteraTrends & Challenges in De...
 
Hands-on Lab: How to Unleash Your Storage Performance by Using NVM Express™ B...
Hands-on Lab: How to Unleash Your Storage Performance by Using NVM Express™ B...Hands-on Lab: How to Unleash Your Storage Performance by Using NVM Express™ B...
Hands-on Lab: How to Unleash Your Storage Performance by Using NVM Express™ B...
 
Scale-out Storage on Intel® Architecture Based Platforms: Characterizing and ...
Scale-out Storage on Intel® Architecture Based Platforms: Characterizing and ...Scale-out Storage on Intel® Architecture Based Platforms: Characterizing and ...
Scale-out Storage on Intel® Architecture Based Platforms: Characterizing and ...
 
Userspace Linux I/O
Userspace Linux I/O Userspace Linux I/O
Userspace Linux I/O
 
Webinar: How NVMe Will Change Flash Storage
Webinar: How NVMe Will Change Flash StorageWebinar: How NVMe Will Change Flash Storage
Webinar: How NVMe Will Change Flash Storage
 
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case Study
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyTraditional vs. SoC FPGA Design Flow A Video Pipeline Case Study
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case Study
 
Hardware accelerated virtio networking for nfv linux con
Hardware accelerated virtio networking for nfv linux conHardware accelerated virtio networking for nfv linux con
Hardware accelerated virtio networking for nfv linux con
 
NVMe PCIe and TLC V-NAND It’s about Time
NVMe PCIe and TLC V-NAND It’s about TimeNVMe PCIe and TLC V-NAND It’s about Time
NVMe PCIe and TLC V-NAND It’s about Time
 
DPDK в виртуальном коммутаторе Open vSwitch / Александр Джуринский (Selectel)
DPDK в виртуальном коммутаторе Open vSwitch / Александр Джуринский (Selectel)DPDK в виртуальном коммутаторе Open vSwitch / Александр Джуринский (Selectel)
DPDK в виртуальном коммутаторе Open vSwitch / Александр Джуринский (Selectel)
 
Function Level Analysis of Linux NVMe Driver
Function Level Analysis of Linux NVMe DriverFunction Level Analysis of Linux NVMe Driver
Function Level Analysis of Linux NVMe Driver
 

Similar to PCIe

BUD17 Socionext SC2A11 ARM Server SoC
BUD17 Socionext SC2A11 ARM Server SoCBUD17 Socionext SC2A11 ARM Server SoC
BUD17 Socionext SC2A11 ARM Server SoCLinaro
 
PI2EQX4401/02 PCI Express ReDriver
PI2EQX4401/02 PCI Express ReDriverPI2EQX4401/02 PCI Express ReDriver
PI2EQX4401/02 PCI Express ReDriverPremier Farnell
 
Heterogeneous Computing : The Future of Systems
Heterogeneous Computing : The Future of SystemsHeterogeneous Computing : The Future of Systems
Heterogeneous Computing : The Future of SystemsAnand Haridass
 
Heterogeneous Integration with 3D Packaging
Heterogeneous Integration with 3D PackagingHeterogeneous Integration with 3D Packaging
Heterogeneous Integration with 3D PackagingAMD
 
PCIe BUS: A State-of-the-Art-Review
PCIe BUS: A State-of-the-Art-ReviewPCIe BUS: A State-of-the-Art-Review
PCIe BUS: A State-of-the-Art-ReviewIOSRJVSP
 
QsNetIII, An HPC Interconnect For Peta Scale Systems
QsNetIII, An HPC Interconnect For Peta Scale SystemsQsNetIII, An HPC Interconnect For Peta Scale Systems
QsNetIII, An HPC Interconnect For Peta Scale SystemsFederica Pisani
 
3D V-Cache
3D V-Cache 3D V-Cache
3D V-Cache AMD
 
Cisco Live! :: Cisco ASR 9000 Architecture :: BRKARC-2003 | Las Vegas 2017
Cisco Live! :: Cisco ASR 9000 Architecture :: BRKARC-2003 | Las Vegas 2017Cisco Live! :: Cisco ASR 9000 Architecture :: BRKARC-2003 | Las Vegas 2017
Cisco Live! :: Cisco ASR 9000 Architecture :: BRKARC-2003 | Las Vegas 2017Bruno Teixeira
 
LinuxCon2009: 10Gbit/s Bi-Directional Routing on standard hardware running Linux
LinuxCon2009: 10Gbit/s Bi-Directional Routing on standard hardware running LinuxLinuxCon2009: 10Gbit/s Bi-Directional Routing on standard hardware running Linux
LinuxCon2009: 10Gbit/s Bi-Directional Routing on standard hardware running Linuxbrouer
 
Cisco crs1
Cisco crs1Cisco crs1
Cisco crs1wjunjmt
 
NVMe Takes It All, SCSI Has To Fall
NVMe Takes It All, SCSI Has To FallNVMe Takes It All, SCSI Has To Fall
NVMe Takes It All, SCSI Has To Fallinside-BigData.com
 
Storage Geeks 101 - 2019
Storage Geeks 101 - 2019Storage Geeks 101 - 2019
Storage Geeks 101 - 2019Andrew McGee
 
Ceph Day New York 2014: Ceph, a physical perspective
Ceph Day New York 2014: Ceph, a physical perspective Ceph Day New York 2014: Ceph, a physical perspective
Ceph Day New York 2014: Ceph, a physical perspective Ceph Community
 
SDC20 ScaleFlux.pptx
SDC20 ScaleFlux.pptxSDC20 ScaleFlux.pptx
SDC20 ScaleFlux.pptxssuserabc741
 
Broadcom PCIe & CXL Switches OCP Final.pptx
Broadcom PCIe & CXL Switches OCP Final.pptxBroadcom PCIe & CXL Switches OCP Final.pptx
Broadcom PCIe & CXL Switches OCP Final.pptxMemory Fabric Forum
 
Supermicro X12 Performance Update
Supermicro X12 Performance UpdateSupermicro X12 Performance Update
Supermicro X12 Performance UpdateRebekah Rodriguez
 

Similar to PCIe (20)

BUD17 Socionext SC2A11 ARM Server SoC
BUD17 Socionext SC2A11 ARM Server SoCBUD17 Socionext SC2A11 ARM Server SoC
BUD17 Socionext SC2A11 ARM Server SoC
 
PI2EQX4401/02 PCI Express ReDriver
PI2EQX4401/02 PCI Express ReDriverPI2EQX4401/02 PCI Express ReDriver
PI2EQX4401/02 PCI Express ReDriver
 
Heterogeneous Computing : The Future of Systems
Heterogeneous Computing : The Future of SystemsHeterogeneous Computing : The Future of Systems
Heterogeneous Computing : The Future of Systems
 
Heterogeneous Integration with 3D Packaging
Heterogeneous Integration with 3D PackagingHeterogeneous Integration with 3D Packaging
Heterogeneous Integration with 3D Packaging
 
PCIe BUS: A State-of-the-Art-Review
PCIe BUS: A State-of-the-Art-ReviewPCIe BUS: A State-of-the-Art-Review
PCIe BUS: A State-of-the-Art-Review
 
QsNetIII, An HPC Interconnect For Peta Scale Systems
QsNetIII, An HPC Interconnect For Peta Scale SystemsQsNetIII, An HPC Interconnect For Peta Scale Systems
QsNetIII, An HPC Interconnect For Peta Scale Systems
 
3D V-Cache
3D V-Cache 3D V-Cache
3D V-Cache
 
Cisco Live! :: Cisco ASR 9000 Architecture :: BRKARC-2003 | Las Vegas 2017
Cisco Live! :: Cisco ASR 9000 Architecture :: BRKARC-2003 | Las Vegas 2017Cisco Live! :: Cisco ASR 9000 Architecture :: BRKARC-2003 | Las Vegas 2017
Cisco Live! :: Cisco ASR 9000 Architecture :: BRKARC-2003 | Las Vegas 2017
 
LinuxCon2009: 10Gbit/s Bi-Directional Routing on standard hardware running Linux
LinuxCon2009: 10Gbit/s Bi-Directional Routing on standard hardware running LinuxLinuxCon2009: 10Gbit/s Bi-Directional Routing on standard hardware running Linux
LinuxCon2009: 10Gbit/s Bi-Directional Routing on standard hardware running Linux
 
Cisco crs1
Cisco crs1Cisco crs1
Cisco crs1
 
TVS-X82T Series -ENG
TVS-X82T Series -ENGTVS-X82T Series -ENG
TVS-X82T Series -ENG
 
NVMe Takes It All, SCSI Has To Fall
NVMe Takes It All, SCSI Has To FallNVMe Takes It All, SCSI Has To Fall
NVMe Takes It All, SCSI Has To Fall
 
Storage Geeks 101 - 2019
Storage Geeks 101 - 2019Storage Geeks 101 - 2019
Storage Geeks 101 - 2019
 
Ceph Day New York 2014: Ceph, a physical perspective
Ceph Day New York 2014: Ceph, a physical perspective Ceph Day New York 2014: Ceph, a physical perspective
Ceph Day New York 2014: Ceph, a physical perspective
 
Networking hardware
Networking hardwareNetworking hardware
Networking hardware
 
Networking hardware (2)
Networking hardware (2)Networking hardware (2)
Networking hardware (2)
 
Networking hardware (2)
Networking hardware (2)Networking hardware (2)
Networking hardware (2)
 
SDC20 ScaleFlux.pptx
SDC20 ScaleFlux.pptxSDC20 ScaleFlux.pptx
SDC20 ScaleFlux.pptx
 
Broadcom PCIe & CXL Switches OCP Final.pptx
Broadcom PCIe & CXL Switches OCP Final.pptxBroadcom PCIe & CXL Switches OCP Final.pptx
Broadcom PCIe & CXL Switches OCP Final.pptx
 
Supermicro X12 Performance Update
Supermicro X12 Performance UpdateSupermicro X12 Performance Update
Supermicro X12 Performance Update
 

PCIe