1. DEEPAK ANAND RAVINDRAN *(GRADUATED May 2015)
750 Miller St Apt# 301,San Jose, CA 95110 Phone: (213) 910-4187 email:dravindr@usc.edu
Linkedin profile: https://www.linkedin.com/in/deepakanandravindran
OBJECTIVE
Seeking Full-timeposition in thefields of Digital ASIC RTL Design/Verificationand Computer Architecture. I am result-oriented and an
effective, dependable team player.
EDUCATION
University of Southern California, Los Angeles, CA May 2015
Master of Science, Electrical Engineering GPA: 3.40
Courses Taken: EE457: Computer Systems Organization,EE477L: MOS VLSI CircuitDesign,EE533: Network Processor Design and
Programming, EE577A: VLSI System Design, EE560: Digital System Design - Tools and Techniques, EE577B: VLSI System Design,
EE658: Diagnosisand Design of ReliableDigital Systems (DFT), EE557: Computer Systems Architecture
National Institute of Technology, Trichy,India May 2011
Bachelor of Technology, Electronics and Communication Engineering(ECE) GPA 8.23/10
WORK EXPERIENCE
Dolphin Technology Inc San Jose, CA, USA
Memory Circuit Design Engineer (Full-time Engineer) Mar 2016–Present
 Edited perl/stimscripts to generate HSpice Timing and Power simulationson circuitnetlists of of SRAM and ROM Memory IPs.
 Performed QA checks on instances generated by in-house SRAM/ROM compiler developed.- Debugged issues with generated
instances like LEF vs GDS Drc errors and leak power, dynamic read/write power of instances at different process corners
 Understood SRAM and ROM structures based on tsmc40nm, tsmc28nm bitcells
Broadcom Irvine,CA, USA
IC Product Engineer (Full-time Staff I Engineer) Sept 2015–Feb 2016
 Performed post Si chip validation and failureanalysisincludingpackaged chip stress/reliability testingand wafer probe, fa ilure
modes and debug, yield enhancement analysis and statistical analysisof test data results.
 Drove ATE testing as well as maintain projecttimelines for package quaification stresstests likeu/bHAST, Temp Cycle, THT,
HTSL and burn-in HTOL (livemonitoring) for packaged chips,includingidentifyingfailures/failuremodes and advisingnext
courseof debug action,and preparingpre/post stress shiftreports for customers. Also drove overseas(OSAT) splitwafers
probe.
 My role involved use of SPC/statisticsand tools likedataConductor/Optimal Testgraphical analysistools to do testdata
Cpk/yield analysis.
 Performed Ate retest on some of the failures and learned to operate Teradyne Ultraflex ATE on test floor.
 My role also sawme interactingwith different teams likePackageEngineering, Test Engineering, Design/Lab Bench Verification
engineers, Process/Foundry engineers and helped gain a panoramic viewof the complicated process that chip development is.
CDOT Alcatel-Lucent Research Center Chennai, India
Digital and Power Embedded Systems Hardware Design Engineer(Full-time Engineer) July 2011–July 2013
 Performed the schematics design,layoutreview with carefor signal integrity and EMI/EMC, component selection,BoM
creation,firmware board bring-up (through Trace32 and JTAG) and PCB testing/debugging of Digital and Power subsystems of
PCB for WCDMA and WiMAX mini Basestations.Madeuse of Bugzilla bugtrackingtool.
 Understood the operation and interfacingof various peripherals likeDDR2/DDR3, NAND/ NOR Flash,Ethernet PHY, PoE,
LDOs,DC-DC converters, ADC/DAC, RF frontend etc. with the ARM11 SoC processor.
 Acquired insights on popular inter-board interfaces likePCI,SPI,I2C, UART, MII etc. and lab equipment likedigital oscilloscope.
 The role required of me to interact with colleagues acrossteams/domains (likethe firmwareteam, mechanical productdesign
team and the component procurement team), and helped hone communication and people skills.
TECHNICAL SKILLS
Key Skills : Verilog,C, Perl,SystemC, VHDL, C++
Operating Systems : Windows,Unix/Linux,Mac
Packages : Synopsys Design Compiler, Cadence NCSsim/NC-Verilog, Synopsys TetraMAX ATPG, Synopsys
PrimeTime, HSpice,Cadence Encounter SoC Auto P&R, Modelsim, SimpleScalar simoutorder CPU
performance simulator,CadenceConformal LEC, Xilinx ISE/Chipscope,Cadence Virtuoso Schematics

2. Editor/Layout Suite, Iperf, Mentor Graphics DxDesigner,Cadence OrCAD Capture, Altera FPGA Quartus II,
Agile PLM, Trace32 JTAG. (Knowledge of LBIST/MBIST, DFT Scan chain,Boundary Scan JTAG)
ACADEMIC PROJECTS
1) DDR2 Memory Controller at 2.6ns clock Design, Synthesis and Auto P&R Oct 2014- Dec 2014
 Designed 2.6ns clock DDR2 Memory Controller ASIC from RTL to GDS2 - VerilogRTL, synthesis usingSynopsys DC,Auto Place-
and-Route usingCadence Encounter SoC.
 Timing was met usingPrimeTime STA and post-layoutsimulation performed on the GDS II.
 The design implemented initialization engineand processinglogic for issuingtimed control signalsfor scalar,block and
atomic(simpleALU ops) read/write operations,apartfrom refresh commands to the Denali IP Micron DDR2 Memory module.
2) D- Algorithm Combinational ATPG (C language) for compressed fault list Nov 2014- Dec 2014
 D Algorithm was realized in C languagefor combinational circuits with reconvergent fanouts.
 Program reads the netlistfrom circuitfiledescribed in ISCAS-85 format and a preprocessor routinegenerates compressed fault
listfor circuit.D ATPG routine is then called to generate test vectors for compressed faults,for faultsimulation.
3) Tomasulo processor MIPS execution rate performance optimization simulation Nov 2014- Dec 2014
 A 32-bitRISC ISA Tomasulo machine’s architecturewas simulated for MIPS instruction execution rate performance optimization
on ‘SimpleScalar simoutorder’simulator with a given transistor budget and area budget of 25mm2 (technology=32nm).
 Thus an ideal architecture(I/D cache size/organization,number of Int/FP ALUs, machinedispatch width,ROB size,dynamic
branch predictor etc.) was arrived with increasefroma base900MIPS to final 2550MIPS rateafter multipleiterations of
architecturetweaking.
4) RTL Design and Implementation of 32-bit CFC-based Tomasulo single-core processor in Xilinx Artix 7 FPGA July 2014 - Aug 2014
 Designed 32-bitTomasulo processor with a subsetof MIPS32 ISA havingIF stage with blockingcache,and 4-deep IFQ, 2-stage
Dispatch unitwith 8-deep BPB and 4-deep RAS,EX area with IssueUnitand integer, lw/sw, mult and div queues, 32-deep ROB,
48-deep PRF, 16-deep FRL, 8-loc SAB, 4-loc SB and a Copy Free Checkpoint consistingof a Retirement RAT and 8-checkpoint
buffers for storingbranch ROB, FRL tags for squash on branch mispredictions.
 Design was coded in VHDL, implemented in Xilinx FPGAand verified usinggiven testbenches and instruction streams.
5) Dual-Core Dual-Threaded 5-stage Pipeline based NetworkProcessor to implement custom SDN Switch Jan 2014 - May 2014
 Designed VerilogRTL for Dual-CoreDual-Threaded 64-bitNetwork Processor with fivestage in-order pipelinewith hardware
accelerators to realizea custom Controller-based Switch to prevent DOS attack through Honeypot application with additional
network security feature through Deep Packet Inspection.
 Perl translator used to generate machinecode from GCC MIPS 32 compiler for the processor’s MIPS32 ISAsubset. Design
implemented in Xilinx Virtex II based NetFPGA board and tested in liveexperimental network cluster to prove functionality.
6) Full custom Design and Layout with optimization for a 64-bit Multicycle CPU at 1.6ns Clock (180nm technology)
Apr 2014 - May 2014
 Designed schematic,DRC check and layoutwith LVS match of EX and MEM stages in full -customtransistor in 180 nm
technology, with Area, Delay and Power Optimization,for a 64-bitmulticycleCPU that included: - 4 bank 64-bitwide 1Kbit
single-portRead/Write SRAM, Datapath including:64-bitALU (with functional units of 64-bitOR, AND, XOR and Kogge-Stone
tree adder) and a 16-bitdivider.
 Utilized Area and Power optimization ideas likeclock gating,SRAM enable signal and data recirculatingmuxes,and Delay
optimization ideas likeuseof Dynamic CMOS logic,fasttree adder, pipeliningof SRAM circuitry.
 IF, ID stages of the CPU realized through Perl scriptwhileEX and MEM stages designed in layout.
ADDITIONAL INFORMATION
 Worked as DeputyManager of ‘Workshops Committee’ in a National Inter-collegetechnical festival, Pragyan 2010.
 Worked as Coordinator of ‘Public Relations’in a National Inter-collegecultural festival,Festember 2008.
 Member of CRY – CHILD RIGHTS AND YOU, NIT Chapter,Aug 2008-Apr 2011.
 Interests includeswimming, playingcricketand badminton, readingbooks and watchingmovies.