this is the synthesized hardware for different verrilog code

1. Synthesized circuit

2. Always block synthesize to combinational
logic when triggered by @(*)
• Last statement get synthesized when
assignment on same variable is done
inside single always block.

3. Multiple FF are synthesized when
triggered by posedge clock

4. Always block synthesize to combinational
logic when triggered by @(*)
• All statement get synthesized
separate H/W when assignment
on different variable is done
inside single always block.

5. Flip Flop with Asynchronous reset
• FF depends on the posedge of
signal rather then the name of
signal. Here I have used signal y
as a clock signal.
• FF with posedge of clock
depends on the active high
Asynchronous reset signal.

6. When one variable assignment
depends on another
• Wire hardware for continuous
assignment.
• Wire hardware inside
always block.
• Here the value of c
depends on a.

7. Assignment on a higher data width
optimized to according to the right hand
sight vector width
• Here dout is a 32
bit integer type but
it get synthesized
to 4 bit as the
width of of
depends on a.

8. Nonblocking statement inside a always
block triggering with @(*)
• The last statement get
synthesized on a single
variable assignment.
• Here the unconnected port
is left unconnected after
synthesized.

9. Nonblocking statement inside a always
block triggering with posedge clock
These assignment are non blocking so these are
schedule at the end of simulation cycle.
The three statements are schedule to execute at
the end of simulation cycle so that present
output of one FF is gong to the input of next
statement.
• Three FF get synthesized
with feedback from
previous FF.
• Multiple statement with
non blocking assignment.

10. Hardware of a string variable in verilog
• The string variable declared reg
type.
• The hardware get synthesized as
the number of FF depends upon
the vector width of the string
variable.

11. Hardware of a always block with posedge
of clock & blocking statement variable
• The hardware get synthesized into FF as
number of statement.
• These assignment is assigned at the same
time as the statement is evaluated.
• Therefore all the statement are executed
sequentially.
• the input to all FF is same as the first FF input
because it is assign by the previous statement
output.

12. Always with if and else statement is
connected to zero and one
• The hardware get optimized
to logic and gate rather then
MUX if else condition
statement is assign to 1’b0.
• The hardware
output is inverted
statement is
assign to 1’b1.

13. Assignment inside always block with @(* )
triggering and constant value
• Here the statement are non
blocking assignment.
• These assignment are
depends on the constant
value so these are
unconnected after synthesis.

14. Hardware for if else condition with
two input

15. Hardware for incomplete sensitivity list
If the sensitivity list is
incomplete then the
synthesis result may
be mismatched for the
large set of statement
after optimization.
The synthesis result
may be
mismatched with
the RTL Simulation
result.
But it not true for
small number of
statement.

16. Hardware for case statement

17. Hardware of mathematical operation
• If the assignment on a variable
is done by constant number
then there is no hardware for it.
There is just a wire connection
for it like add_int.

18. Hardware for addition of multiple data
without parenthesis
the hardware for addition is
simple adder block.
without having the parenthesis it
generate adder block one by one
addition.

19. Hardware for addition of multiple data
with parenthesis
Here the two parenthesis are
used.
So it will add first two block set
and then finally it adding these
two output.
The benefit for this that we can
increase the speed of the
hardware to make the operation
concurrently.

20. Hardware for a counter circuit
hardware for a counter is 3 bit
FF.
The output combination of
two FF will go to the input of
next FF I/P as the reset signal.