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Introduction to architecture exploration
- 1. Introduction to Architecture Exploration WEBINAR Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
- 2. Logistics of the Webinar 2 To ask a question, click on Cloud Chat sign and type the question. Folks are standing by to answer your questions. There will also be a time at the end for Q&A
- 3. Introduction to Architecture Exploration WEBINAR Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
- 4. Agenda Introduction to Architecture Exploration- Terminologies, Flow and Challenges Solution Requirements Extent of architecture exploration Explanation of the Flow using an Infotainment Example
- 5. Architecture Exploration flow Diagram Product Concept, Optimized Architecture, Development and Support Track 30 aircrafts per minute IoT or 5G device Handle 3 cameras, 4 Lidars & 5 Radars 95% cache hit-ratio Gateways to handle WiFi, BLE and TSN Product Requirements Output Optimized Architecture CPU_1 CPU_2 Cache RAM B U S Rough/Existing Architecture Semiconductor Systems and Software Assemble Models Conduct Trade-offs Architecture Optimization Functional Analysis Simulation Environment Mirabilis Design Inc. 5 Early SW Development Field Testing Integration Tests Documentation
- 6. System Architecture Exploration Scheduling/Arbitration proportional shareWFQ staticdynamic fixed priority EDF TDMA FCFS Communication Templates Architecture # 1 Architecture # 2 Computation Templates DSP AI GPU DRAM CPU FPGA m E DSP TDMA Priority EDF WFQ RISC DSP LookUp Cipher AI DS P CPU GP U mE DD R static Which architecture is better suited for our application?
- 7. Architecture Exploration is Universal 5G, Defense, Aerospace, Automotive, Computing and Semiconductors
- 8. Requirements for Architecture Exploration Fabric and Memory IP and Subsystem System Architecture Exploration Design SW Design HW Performance and Power Optimization SW&HW Partitioning SW&HW Co-Simulation System-Level Emulation on FPGA SoC Integration SchedulingTask Graph RTOS and Resource Security Failure and Functional Analysis Input: Requirements and Concepts
- 9. Architecture Exploration Phases Model-based Systems Engineering Electronic System-Level Design Virtual Prototyping Early System Verification (Hybrid Prototyping) Aircraft, Ground Stations, Vehicles and Satellites Vehicle Network, V2V, and Wireless Connectivity Data center and Networking IP Design and Selection SoC, AI Board, Integrated and Distributed Systems Old software on new architecture Early software development environment Functional Safety System Model + FPGA System Model + Emulation System Model + Product Custom Processors, Switches and Control
- 10. Model-based System Design Networked Systems Data centers Mission-LevelVehicle Networking
- 11. Electronic System-Level Design IP or Block-level Semiconductors Processor SoC/FPGA Integrated/Distributed Systems And Boards Networked Systems Data centers
- 12. Virtual Prototyping ARM MMU Memory LCD DDR Touch Screen WiFi Speaker Mic Cache VisualSIm Cycle Counter KEY OS/SW Develop Software on System model And Instruction Set Simulator Evaluate performance improvement and power saving from software upgrade Failure, Redundancy, security evaluation
- 13. Early System Verification 10/2/2020 MIRABILIS DESIGN INC. 13 Evaluate existing RTL or IP against system operations Design-under-Test- Emulator or real system
- 15. Diagram provided by Allion Infotainment Eco-System
- 16. Network-Level Exploration CAN Bus CAN Bus CAN BusWheel 1 Wheel 2 Wheel 3 Wheel 4 Break Pedal Proximit y Sensor Gyro Sensor Brake ECU Road sensor Engine CAN ECU CAN ECU CAN ECU N N N N NN NN NN N N Gateway N
- 17. System-Level Model View 10/2/2020 MIRABILIS DESIGN INC. 17 DRAM Display IO A M B A A X I B u s CPU GPU Display Ctrl CAN Packet Ethernet
- 18. System View
- 19. Hardware-Software View 10/2/2020 MIRABILIS DESIGN INC. 19 DRAM Display IO A M B A A X I B u s CPU GPU Display Ctrl P C I e Video Camera SRAM Packet System Overview ◦ Camera ： 30fps, VGA corresponds ◦ CPU ： ARM Cortex-A53 1.2GHz ◦ GPU ： 64Cores(8Warps×8PEs), 32Threads, 1GHz ◦ DisplayCtrl ： DisplayBuffer 293,888Byte ◦ SRAM ： SDR, 64MB, 1.0GHz ◦ DRAM ： DDR3, 64MB, 2.4GHz
- 20. Extended System Model Which Libraries? 1. Configure Parameters and data table setting. • Traffic • Expression • MasterDevice • Bus Arbitor/Bus • DMA • RAM • Processor • PCIe • AMBA AXI • Power Management 2. Create script code • GPU Warp/PE NXP i.MX6 / nVIDIA Drive PX Xilinx FPGA Kintex 8 Discrete DMA ARM A53 GPU Display Ctrl SRAM3 DRAM3 Video IN Parameters
- 21. Micro-View of System-Level Analysis of an AI Processor
- 22. System-Level Power Evaluation Instant Power represents the cumulative power of all the devices at every instance of clock cycle . . Average Power represents the average of power for each devices over time -> (Standby, Active, Wait, Idle, Refresh and Retention) Spikes indicates the number of devices are turned “on” and “off”
- 23. Power State Timing Diagram Here you can see, the change of states from active to standby
- 24. Failure Studies Hardware Failure: Loss of processing cores, limited storage, reduced or loss memory device or bus overload/incorrect signals. Software failure: Resource starvation, deadlocks, data overwrite. Network failure: Network Congestion, misconfiguration, link loss and network errors. RTOS failure :Unable to achieve real-time deadlines, malicious change in schedule table, and executes beyond time slots. Power Failure: Both reduced and full power failure. Slower processing speed, limited number of resources can be executing concurrently. Comprehensive testing of the entire system to generate diagnostics
- 25. To Learn More VIDEOS AND SUPPORT RESOURCES
- 26. Support Resources Application and support engineers at info@mirabilisdesign.com VisualSim Software download Training videos: ◦ Complete training: https://www.youtube.com/playlist?list=PLizKwf7N88at70EwhqvFq_zDaLkoQEKg1 ◦ Foundation Tutorial: https://www.youtube.com/watch?v=0e1LVYU26rc&list=PLizKwf7N88at70EwhqvFq_zDaLkoQEKg1&index=3 ◦ Flow Control and Network Modeling: https://www.youtube.com/watch?v=oH2C0_ET5qY&list=PLizKwf7N88at70EwhqvFq_zDaLkoQEKg1&index=4 ◦ Real time applications: https://www.youtube.com/watch?v=96ro8fpf2aQ&list=PLizKwf7N88at70EwhqvFq_zDaLkoQEKg1&index=5 ◦ Power modeling: https://www.youtube.com/watch?v=n4VudSX3Wjo&list=PLizKwf7N88at70EwhqvFq_zDaLkoQEKg1&index=6 ◦ Cache Tutorial: https://www.youtube.com/watch?v=gOzkYcpU3c4&list=PLizKwf7N88at70EwhqvFq_zDaLkoQEKg1&index=7
- 27. About Mirabilis Design and VisualSim COMPANY OVERVIEW
- 28. Company Milestones VisualSim Aerospace Simulator of the Year Hardware Modeling 2003 Company Incorporated 2005 Modeling Services 1st Customer 2008 Stochastic Modeling Innovation Award 2010 Integration API 10th customer 2011 Network modeling University program 20132015 2018 Best ESL at DAC 2nd at Arm TechCon Functional Safety 2019 VisualSim Automotive 250 products built Started Europe operations 2020 VisualSim Virtual Proto Started Asia Operations Mirabilis Design Inc. 28
- 29. Wide Range of Customer Successes Mirabilis Design Inc. 29
- 30. VisualSim software with libraries Training: Training and modelling support- user builds the components and models Services: Develop custom library- User assembles the models Develop custom libraries and models - User conducts parameter study Model-based Systems Engineering simplified and made easy-to-adopt Mirabilis Design Software and Solutions
- 31. Introduction to VisualSim Architect ◦ Architect processors, hardware systems, software and network ◦ Map algorithms on integrated and distributed systems ◦ Compute resource requirements for application task graphs ◦ Test compliance to standards and generation of diagnostics Timing and Throughput Power measurement, management and Battery Entire EE to Semiconductor Functional and Safety Analysis Libraries Hardware, Software and Network Graphical Modeling Functional, timing and power analysis to existing Model-based System Design
- 32. Largest Systems-Level Model Library Largest library of traffic, resources, hardware, software and analysis Traffic • Distribution • Sequence • Trace file • Instruction profile Reports • Timing and Buffer • Throughput/Util • Ave/peak power • Statistics Power • State power table • Power management • Energy harvesters • Battery • RegEx operators SoC Buses • AMBA and Corelink • AHB, AB, AXI, ACE, CHI, CMN600 • Network-on-Chip • TileLink System Bus • PCI/PCI-X/PCIe • Rapid IO • AFDX • OpenVPX • VME • SPI 3.0 • 1553B Processors • GPU, DSP, mP and mC • RISC-V • Nvidia- Drive-PX • PowerPC • X86- Intel and AMD • DSP- TI and ADI • MIPS, Tensilica, SH ARM • M-, R-, 7TDMI • A8, A53, A55, A72, A76, A77 Custom Creator • Script language • 600 RegEx fn • Task graph • Tracer • C/C++/Java • Python Support • Listener and Trace • Debuggers • Assertions Stochastic • FIFO/LIFO Queue • Time Queue • Quantity Queue • System Resource • Schedulers • Cyber Security RTOS • Template • ARINC 653 • AUTOSAR Memory • Memory Controller • DDR DRAM 2,3,4, 5 • LPDDR 2, 3, 4 • HBM, HMC • SDR, QDR, RDRAM Storage • Flash & NVMe • Storage Array • Disk and SATA • Fibre Channel • FireWire Networking • Ethernet & GiE • Audio-Video Bridging • 802.11 and Bluetooth • 5G • Spacewire • CAN-FD • TTEthernet • FlexRay • TSN & IEEE802.1Q FPGA • Xilinx- Zynq, Virtex, Kintex • Intel-Stratix, Arria • Microsemi- Smartfusion • Programmable logic template • Interface traffic generator Software • GEM5 • Software code integration • Instruction trace • Statistical software model • Task graph Interfaces • Virtual Channel • DMA • Crossbar • Serial Switch • Bridge RTL-like • Clock, Wire-Delay • Registers, Latches • Flip-flop • ALU and FSM • Mux, DeMux • Lookup table
- 33. Broadest exploration coverage Functional, cycle, latency, throughput Power, security, failure, safety Reusability ◦ Concept, marketing, communication, ◦ Validation and field testing Short time to project completion Reference designs Ease of use Breadth/depth of library coverage Across multiple application segments Early view of the full SoC or system VisualSim Delivers Priceless Value in System Design Mirabilis Design Inc. 33
- 34. Profit Upside using VisualSim - Quick Model Bring-UP and Meticulous Analysis Using Alternate Design Methodology Project Schedule Model Creation (6) Implementation (18) Analysis (1.5) Communication and Refinement (6) Implementation (15) Using VisualSim Model-Based Design Methodology Note: All times in months Communication and Refinement (4) Analysis (2.5) Model Creation (1) Average gain for 24- month project is 25%-30% Ensuring Highest Quality Product Accelerate Model development Mirabilis Design Inc. 34
- 35. Introduction to Architecture Epxloration WEBINAR THANK YOU Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
- 36. Analysis assumptions Multi-master conflict verification Latency for each master to access the DRAM Video mater speed Throughput of the GPU, Speed of the GPU Power estimation Analysis contents ① Video master speed • Upper limit spec analysis of video stream ② Software performance • Analyze software task execution performance(30fps) ③ GPU throughput(Warp execution performance) • Comparative analysis of Warp execution time by OpenCL/CUDA ④ Power estimation • Analyze GPU power consumption Analysis assumptions and Analysis contents Analysis points DRAM Display IO A M B A A X I B u s CPU GPU Display Ctrl P C I e Video Camera SRAM 2 1 3 4
- 37. Major Automotive Applications (1) Network planning ◦ End-to-end latency for a packet ◦ Configuration of the network, allocation of software tasks onto multi-core ECU hardware architecture ◦ Throughput on each network ◦ Assignment of sensors to network ◦ Local vs centralized sensor processing vs sensor fusion ◦ Buffer usage at Receiver and Transmitter Notes: ◦ Apply to OEM, Tier-1 suppliers and semiconductor vendors ◦ Providing input to Simulink engineers on the architecture constraints
- 38. Major Automotive Applications (2) Quality of Service ◦ Optimize software code sequence and scheduling algorithm ◦ RTOS performance tuning ◦ Software task distribution across multi-core and multi-ECU Functional safety ◦ Identify points of failure, detect system bottlenecks and deadlocks ◦ Feedback for early submission of certification data Image by Threatpost Data
- 41. First Mover Advantage Get in at the OEM or Tier One during specification ◦ Key IP Selection (Tensilica and memory controller) ◦ ASIC Vendor selection At Tier One or Semiconductor vendor- Onsite thanks to relationship at OEM or Tier One ◦ Add additional IP to the pool ◦ Verification tool 10/2/2020 MIRABILIS DESIGN INC. 41
- 42. Mutual Benefits of Partnership - Showcasing SoC Solution in a Live System Requirements CAN Bus CAN Bus CAN BusWheel 1 Wheel 2 Wheel 3 Wheel 4 Break Pedal Proximit y Sensor Gyro Sensor Brake ECU Road sensor Engine CAN ECU CAN ECU CAN ECU N N N N NN NN NN N N Gateway N Leverage Libraries to build up the full starting model; Replace with IP blocks later
- 43. Mutual Benefits of Partnership - From Architecture to Implementation Flow Track 30 aircrafts per minute IoT or 5G device Handle 3 cameras, 4 Lidars & 5 Radars 95% cache hit-ratio Gateways to handle WiFi, BLE and TSN Product Requirements Output Optimized Architecture CPU_1 CPU_2 Cache RAM B U S Rough/Existing Architecture Semiconductor Systems and Software Assemble Models Conduct Trade-offs Architecture Optimization VisualSim Environment Mirabilis Design Inc. 43 IPs (digital and analog) In architecture reference design Emulator (Palladium) and FPGA platform (Protium) In hybrid virtual prototype Joules Constraints from VisualSim power estimate results Etc. PCB tool (Alegro) Constraint file from timing and power Etc.
- 46. Automated Fault Injections of Pre- Defined Failures
- 47. ASIL A ASIL B ASIL C ASIL D Hardware Failure Network Failure Software Failure RTOS Failure • Slight Injury • Normally Controllable • High Probability of exposure • Examples Lag in display of rear-view camera • Severe Injury • Normally Controllable • High Probability of exposure • Examples Failure of collision avoidance tone • Fatal/Survive uncertain • Difficult to control • Medium Probability of exposure • Examples Anti-lock braking system wheel lock-up Out of control automatic transmission • Fatal/Survive uncertain • Difficult to control • High Probability of exposure • Examples Steering-control lock-up Airbag deployment while driving Correct data VS Incorrect Data model using VisualSimWhen one core fails • Resource fails • Resource unavailable • Bus interface is lost • Handshake is incorrect • Congestion on the network • Unintended message repetition • Message loss • Deadlocks • Stack overflow and underflow • Algorithm result change due to change in memory value, • Example: read before write • Timing deadline not met - Execution time VS slot time • Task management and interrupts Disable slot info
- 48. Case 1: Performance & Power Optimization SoC 10/2/2020 MIRABILIS DESIGN INC. 48
- 49. Case 2: Software Integration Tracing and Software Bring-up 10/2/2020 MIRABILIS DESIGN INC. 49
- 50. Case 1: Model-based Systems Engineering Automotive Brake Model 10/2/2020 MIRABILIS DESIGN INC. 50
- 51. Case 2: Performance & Power Optimization Board- Software-defined Radio 10/2/2020 MIRABILIS DESIGN INC. 51
- 52. Case 3: Virtual Prototyping Integration 10/2/2020 MIRABILIS DESIGN INC. 52
- 53. Distributed Development 10/2/2020 MIRABILIS DESIGN INC. CONFIDENTIAL WW IPware URL My_URL_list My Workspace ? 45% IP vendors System house software Document Link Download
- 54. System Architecture Exploration Scheduling/Arbitration proportional shareWFQ staticdynamic fixed priority EDF TDMA FCFS Communication Templates Architecture # 1 Architecture # 2 Computation Templates DSP AI GPU DRAM CPU FPGA m E DSP TDMA Priority EDF WFQ RISC DSP LookUp Cipher AI DS P CPU GP U mE DD R static Which architecture is better suited for our application?
- 55. VisualSim Design Flow Early architecture analysis Detailed design specification Debugging during development Test and Verification In-field analysis Validate requirements and early customer feedback Size, Allocate, Arbitration, IP selection and topology design Software and marketing development Provide scenarios and test benches for verification Input traffic traces to recreate the field problems End-to-end Design Flow Impact
- 56. VisualSim Technology and Abstraction Stochastic, Queuing Flow-control, Scheduling Task graphs Cycle-accurate, Functional correctness and Transaction-level Power Timing, Functional Documentation Reference designs Failure generation Analog, Control, Digital, DSP, Protocol, Network
- 57. VisualSim Product Modeling IP Graphical User Interface Analysis Diagnostics Failure Generation Generators XML Database Simulation Tracker Multi-domain simulator
- 58. VisualSim Solution Model-based Systems Engineering Electronic System-Level Design Virtual Prototyping Early System Verification (Hybrid Prototyping) Aircraft, Ground Stations, Vehicles and Satellites Vehicle Network, V2V, and Wireless Connectivity Data center and Networking IP Design and Selection SoC, AI Board, Integrated and Distributed Systems Old software on new architecture Early software development environment Functional Safety System Model + FPGA System Model + Emulation System Model + Product Custom Processors, Switches and Control
- 59. Model-based System Design Networked Systems Data centers Mission-LevelVehicle Networking
- 60. Electronic System-Level Design IP or Block-level Semiconductors Processor SoC/FPGA Integrated/Distributed Systems And Boards Networked Systems Data centers
- 61. Virtual Prototyping ARM MMU Memory LCD DDR Touch Screen WiFi Speaker Mic Cache VisualSIm Cycle Counter KEY OS/SW Develop Software on System model And Instruction Set Simulator Evaluate performance improvement and power saving from software upgrade Failure, Redundancy, security evaluation
- 62. Early System Verification 10/2/2020 MIRABILIS DESIGN INC. 62 Evaluate existing RTL or IP against system operations Design-under-Test- Emulator or real system
- 63. Agenda System model and the requirements Types of models ◦ Abstraction levels for the software ◦ Abstraction level for the hardware ◦ Mapping between the hardware and software models ◦ Executing Software code on ISS and FPGA
- 64. Parts of a System Anything in Electronics ◦ Network ◦ Protocols ◦ DSP ◦ Processor, memory, bus, cache and DMA ◦ Accelerators, AI pipeline ◦ Software task graph, trace file, instruction sequence or software code Support ◦ Power Table ◦ Statistics and Report generation ◦ Traffic, trace, trigger, interrupt Exploration ◦ Parameters
- 65. Electronics Master ◦ Processor, DMA, Master-Generic Non-Master ◦ Bus- Linear (AHB), Crossbar(AXI), Switch and Network-on-chip(CMN600) ◦ Memory (SRAM, DRAM, Flash) ◦ Slave- Generic Software ◦ Traffic, Workflow, Profile-driven, Trace-Driven, Generated profile
- 66. Types of Model- For Architecture Exploration Mission or Network level ◦ Flow model- xOn_xOff.xml ◦ Network- demo/networking folder or demo/automotive Full System including boards and boxes ◦ Embedded System- demo/System_Architecture/Video_Processing/Video_Processing_Model2.xml, demo/System_Architecture/software_Radar_System/Large_Radar_System.xml. Demo/Bus_Std/PCI_Rad/ PCI_RAD_Demo.xml ◦ Software:demo/software_devl/software_methodology/Software_tasks_w_Power.xml, demo/automotive/Autosar/AUTOSAR_Scheduler/Autosar_Model4a_noCCode.xml ◦ Evaluating software code- demo/automotive/Autosar/AUTOSAR_Scheduler/Autosar_Model4a.xml (Requires compile) SoC ◦ Hardware+Software- early exploration- Multi_Core_Soc_V43.xml ◦ Hardware+Software partitioning- Timing approximate- demo/partitioning/SoC/Power_Perf_Example.xml ◦ Hardware-software-cycle-accurate- CMN600_with_DDR5_DynamicRT.xml ◦ Individual component- Bus and Memory-demo/complex_system/Multi_AXI_to_Memory_Access.xml
- 68. Modeling Abstraction- Software-Level •Analysis Study message-passing schemes, scheduling and deadlines Software scaling, distribution and partitioning •Hardware Use one of many templates- single processor, multi-processor, network of processing systems Set the connectivity and hardware attributes via a Spreadsheet •Software Generate a statistical profile for the software code by target (Flow chart approach) Distribution-based traffic to emulate the task and message-passing Instruction trace from virtual platform (Software tuning)
- 69. Parallel Execution Scaling Task View Read Process Write Task Flow Frame View Frames Multi Core Application
- 70. Modeling Software Blocks Delays through the hardware platform UML or Flow Chart model of the software with profiles Generate instruction sequence ◦ Synthetic or profile-driven Link code execution with hardware model execution
- 71. Modeling Results •Software Tasks per Second (Min, Mean, StDev, Max) •Software Deadlines Exceeded per Second (Min, Mean, StDev, Max) •System Response Time vs. (Simulation Time, Histogram) •System Throughput vs. (Simulation Time, Histogram) •Hardware Efficiency (Utilization Summary)
- 73. Introducing Virtual Prototyping Software-based engineering discipline which involves ◦ Modeling a system ◦ Simulating and visualizing its behavior under real-world operating conditions ◦ Refining its design through an iterative process To be truly effective, virtual prototyping must include ◦ Task graph analysis ◦ Mapping of behavior to architecture ◦ Running software on an ISS ◦ Generating timing, power and behavior correctness
- 74. VisualSim Virtual Prototyping Solution Current solution ◦ Software is defined as a task graph, traffic, trace file and profile-based task generator ◦ Execute software on a device, FPGA or emulator New solution ◦ Using GEM5 to create a virtual prototype
- 76. Virtual Prototyping using GEM5 GEM5 is an open-source simulation environment from University of Michigan Popular in both research and academics Used by many companies for their early software development requirements
- 77. Advantages & Disadvantages with GEM5 Advantages ◦ Large user community ◦ Support for ISS from ARM v8, Power, x86, RISC-V and GPU(AMD) Disadvantage ◦ Lack of support ◦ Accuracy has not been tested
- 78. VisualSim with GEM5 Goal ◦Execute software code on an emulated hardware system ◦Test the software against the full system ◦Current focus is performance and power of the full system ◦Future focus is correctness of action ◦ Triggered the right device or sent data to the right interface
- 79. VisualSim model of Multi-Core System Replace with GEM5
- 81. Processor Timing Diagram- Pipeline Grid line is 1 cycle. 3 instructions ADD, SUB, MUL Cycles: 2,3,4 Start Stage 1: Read Instr 1 Instr 2 Instr 3 Stage 1: Read Data1 Data 2 Data 3 Stage 3: Execute on INT1 Instr1 Instr 2 Instr 3 Instr1 Instr 2 Stage 4: Write Back 1st Word Prefetch Instr 1 Data 1 Instr 2 From Cache Instr 1 Data 1 Instr 2 Transfer on Bus Instr 1 Data 1 Instr 2 Instr 1 Data 1 Instr 2 Control on Bus from Cache Decode 1 cycle After Data & Instr
- 82. VisualSim Processor Abstraction No knowledge of the data values ◦ Only the size and the consumption of space in the registers, cache and memory Instructions ◦ Execute the delay in the Execution Units ◦ Ignores the functionality of the instruction such as move value from B to A OS and Libraries ◦ Access to external scheduler but not a Linux-type software
- 83. Advantages of the VisualSim Processor Software code is not required Easy and fast to setup Flexible experiments and trade-off ◦ Can be quickly configured using parameters Emulate scenarios that are not possible in real-life Task Generator provides the ability to generate profiles of software that does not exist Tracing at any point
- 84. Linking GEM5 to VisualSim GEM5 OS or System SW Platform Application (Web, Map, Youtube, etc) ARM Lib ARM/uP ISA MMU Memory LCD KEY Touch Screen WiFi Speaker Mic Cache VisualSim Cycle Counter FB
- 85. Representative Example on VisualSim MSM7201A Qualcomm ARM11@528MHz ARM926@274(modem) LCD Sharp 3.2” TFT HVGA (320 x 480) LCD Controller Touch Screen NAND Flash (256MB) + DDR SDRAM (128MB) Samsung MCP K5E2G1GACM Wi-Fi Transceiver 802.11b/g TI WL1251B Power AMP 802.11b/g TI WL1251FE Power Management Qualcomm PM7540 Battery 35H00106-01M 1150mAh Capacitive Touch Screen Controller Synaptics 1007A Key Board Hardware Platform on VisualSim
- 86. How this works VisualSim triggers the software to execute GEM5 executes for a time duration Output the addresses, service time and the time stamp GEM5 can be triggered on a fixed schedule like real-time software or can be triggered after the operation is completed in VisualSim GEM5 ISS VisualSim VisualSim Trigger @ CLK
- 87. Debug Software in System Context
- 88. Integrate Debugging and System Analysis
- 89. Enhancements GEM5 ◦ Multi-core with different software on each core ◦ Add RISC-V and GPU models ◦ Trigger software instances as opposed to full program ◦ Add support for more debuggers Provide services to develop new ISS Integrate ARM Fast Models SystemC package to add processors like CEVA and Tensilica ◦ Using existing SystemC integrate
- 90. VIRTUAL PROTOTYPING WITH VISUALSIM