1. MIMO Full-Duplex FPGA Testbed Development for Hardware Verification
of Self-Interference Cancellation Prototype
Introduction
Objective
Digital Down Converter Design
Future Work Conclusion References
Broadband
Communications
Research Lab
Average Power Calculator
`
Farnood Faraji, Robert Morawski, Prof. Tho Le-Ngoc
Electrical and Computer Engineering Department, McGill University
• Directly Down converts wideband 20MHz RF signal
from 2.08896GHz (or 2.27GHz) to Baseband.
• Decimates the signal from the effective 2.4576GHz
to 30.72MHz.
Architecture: wideband parallel design based on
Polyphase filter. 16 parallel, 1/fsa delayed, 12bit ADC
channel outputs.
BCRL Other
Slice Registers 7% 3%
Slice LUTs 12% 5%
LUT-FF pairs 70% 40%
bonded IOBs 15% 15%
RAM/FIFO 16% 22%
DSP48E1s 57% 23%
• Average Power Calculator was designed based on an accumulator for
calculating the Average Power.
Other Options: FIR filter, IIR filter, Sliding-Window Accumulator.
Advantage: Consumes less Memory resources than the other options.
Disadvantage: Averaging Window is not sliding unlike other options.
LTE TDD burst size is 1.2ms, accumulator type power meter update rate is 133μs or
25μs for 4096 or 512 window size, which normally could be slow. However, in our
case, Matlab to/from FPGA data request/transfer period of 90ms would be the
limiting factor in power monitoring/S1 canceller tuning speed.
1. T. Liu, S. Tian, Z. Wang, and L. Guo, "An Efficient Parallel Architecture for Wideband Digital Down
Conversion," Computational Information Systems, vol. 9:18, no. 1553–9105, pp. 7315–7324, Sep. 2013.
2. A. Masmoudi, "Self-Interference Cancellation for Full-Duplex Wireless Communication Systems," PHD,
McGill University, Montreal, Canada, 2016.
3. Bibliography: [1] A. V. Oppenheim, R. W. Schafer, and J. R. Buck, Discrete-Time Signal Processing, M.
Horton, Ed., 2nd ed. Upper Saddle River, New Jersey 07458: Prentice Hall, Inc.
High Data Rate Digital Down Converter & Resources Efficient Residual Self-Interference Average Power Sensor
+
+
RF
ADC
FMC108
16
Channels
Output
Eff fsa:
2.4576
GHz
E0(n)
E0(n)
E1(n)
E15(n)
E15(n)
E1(n)
x0(n)
x1(n)
x15(n)
:
:
:
:
:
:
Polyphase
FIR filters
:
:
NCO Module
2.08896 GHz or 2.27 GHz
NCO0
{Q I}
NCO1
{Q I}
NCO15
{Q I}
……
AveragePowerMeter
I
Q
Phase shifted and
Decimated NCO
NCOi = NCO(nD+i)
Interleaving
ADC Images
RF input
signal in 2nd
Nyq. Zone
Signal
Image in 1st
Nyq. Zone
fs/2 fs
Type SNR IMD3 ACPR SFDR
BCRL 66dBfs 65dBc 58dB 84dBc
Other 65dBfs 64dBc 56dB 76dBc
(ADC) 46(48) 64(64) 54 60(60)
Frame Size Deviation (dB)
4096 0.0074
2048 0.0150
1024 0.0473
512 0.0777
64 tone test signal in baseband,
18MHz bandwidth
Instant
Power
Accumulator Register
Counter ++
Signal
from
DDC
Q
I
Matlab
PSOEnables or resets
the Accumulator Contains the
most updated
value
DDC Performance:
Typical DDC design:
Parallel DDC design
DDC Results: ADC Output
DDC Output
Power Meter Design
Power Meter Performance: Different Averaging Windows:
z-n
Accumulator
-
+
+
data
Alternatives:
1. Digital Down converter is preferred over Analog Down conversion because it can generate more accurate
mixer output with exactly 90 degrees phase shift, thus no performance degradation due to I/Q in-balance.
2. Present BCRL DDC FPGA design meets all the timing, functional and linear performance requirements, but
it may need improvement in efficient use of FPGA resources.
3. Power Sensor is accurate to < 1dB error over a range of 60 dB which is sufficient for desired cancellation
tuning range application. Typical S1 cancellation tuning range would be 45 dB.
1. Modify DDC to have a programmable LO frequency to support 1.7GHz to
2.7GHz LTE 20MHz band operation (higher complexity expected).
2. Expand current FDD LTE Power Sensor design for operation with Time-Division
Duplex LTE signals (add burst power detector).
3. Implement DUC (Digital Up Converter).
4. Implement new DSP section of Stage 2 and 3 of Self-Interference cancellation.
Larger window size will give less
variation, but slower update rate.
0.1dB might be sufficient for S1
canceller tuning.
Sliding
Window
Accumulator FIR filter
Alternative techniques
require Data Delay register
with the length of window
(z-n) and could consume
~30% more resources.
12
16
5
Decimation by
5 and filteringLNA
28
40
32
32
40
32
32
48 48 32
2.08896GHz
64 tone test signal
18MHz BW
Challenges:
• RF ADC samples the input signal at 2.4576GSPS; however, DSP
blocks on FPGA cannot operate at such high sampling rate, thus
the signal must be first down-converted and down-sampled to
~150MSPS (without any loss in captured signal quality) for further
processing in today’s FPGA technology.
• Analog/RF Down Converter before ADC introduces I/Q unbalance,
thus it is replaced by Digital Down Converter, and DDC needs to
have a programmable LO frequency since the receiver needs to
be tuned to different frequency bands.
• Residual SI signal Power Sensor approach should be fast, reliable
and resource efficient.
Goals:
• Implement configurable Direct RF wideband DDC FPGA prototype
which down converts 2.27GHz 20MHz BW RF sampled signal to
base band.
• Design a Power Sensor core which can calculate the average power
of the residual SI signal on a configurable averaging window and
make it accessible for Matlab PSO.
0
5
10
15
20
25
-100
-80
-60
-40
-20
0
20
-100 -80 -60 -40 -20 0 20
Errors(dB)
MeasuredPower(dBm)
Input Power (dBm)
Average Power Measurement for 4096 frame size (32bit version)
fixed FPGA Expected Real error measurement error 16bit error
Consumes 303
(out of 47,901)
less LUT-FF
Help us to have a
configurable window
• The purpose of this research is to implement Full-Duplex 2x2
MIMO communication for the 5G mobile standard.
• Full-Duplex (FD) communication is the transmission and
reception of radio signal simultaneously on the same frequency
band.
Advantage:
• This increases data throughput
and spectral efficiency.
Challenge:
• Simultaneous transmission and
reception results in strong self –
interference.
• RF Self-Interference Cancellation
enables simultaneous reception
of a very weak signal while
transmitting a very strong signal
from the same base station.