1. Gene Cernilli
1713 Yateley Lane • Apex, NC 27502
M:919-302-5304 • H:919-363-8190
gcernilli@gmail.com • http://www.linkedin.com/in/cernilli
1
Summary
Senior Engineering professional, skilled in the design and development of leading edge telecom and
military electronics systems. Analytical self-starter with broad experience and proven record of
bringing profitable products to market on time and within budget. Core competencies include:
● Embedded μController PCB Design & Layout
● High Speed Digital PCB Design & Layout
● Switching Power Supply Design & Layout
● FPGA & ASIC Design
● ASIC Verification Front End
● Trouble-Shooting and Debug
● Project Engineering
● Systems Engineering
● Requirements Development & Analysis
● Specifications and Test Procedures
● Reliability Analysis
● Customer Interface
● Software Development Support
● Compliance and Quality Support
● Manufacturing Introduction
● Legacy Product Support
● Secret Clearance, Inactive
Education
Bachelor of Engineering, Concentration in Telecommunications
1983, Stevens Institute of Technology, Hoboken, New Jersey
Technical Skills
DDR • PCI • GMII • 10/100/1000Base-T • YUV422 • MIPS • ARM9 • POWER-PC • Xilinx & Altera
FPGAs • Ethernet Switch & PHY ICs • UART • NOR & NAND Flash • I2C • SPI • USB. Ethernet/IP
Layers 1-3 • Concept • Allegro • Altium • Quartus II • Vivado • Synopsis • Tektronix, LeCroy & Agilent
Test Equipment • EJTAG debuggers • Microsoft Office • Verilog • C • Perl • HTML • UNIX scripting
Selected Accomplishments
 Embedded processor design subject matter expert on Alcatel’s 1603/12/48 SONET ADM for 7
years. Kept pace with processor, memory and peripheral technologies. Worked with software and
systems groups on processor upgrades. Designed or oversaw all controller designs. Consulted on
an all embedded interface designs. Successfully guided project through three processor upgrades
allowing system to meet enhancement requirements.
 Designed, developed and released the following PCBs: Video Encoder, Sonar Telemetry, IP to
ATM Interface, Ethernet to GPON Interface, and Ethernet to SONET Interface. Designs met
requirements, schedules and budgets, products were either profitably deployed or successfully
demonstrated.
 Released to production three generations of Optical Line Terminations (ONT) for Alcatel-
Lucent’s 7342 GPON FTTU. Designed, developed and lead team. Projects were on time and
within budget.
 Developed Perl test code for that converted Ethernet/UDP packet data into time-series
waveforms from multi-channel sonar receiver. Code performed FFTs, analyzed noise floor,
dynamic range, coherent noise, harmonic distortion, and measured phase and amplitude.
 Developed Perl calibration code for Raman spectrometer. Used splining techniques and
polynomial regression to approximate recorded reference spectrum and generate calibration
polynomial.
 Instantiated ASIC RTL for server processors on in-house, Xilinx XC7V2000T and Ultrascale
based emulation platforms used in hardware and software verification testing.
 Architected and implemented Verilog design of OC48 and OC12 line, section and path transmit
overhead functions of OC48 and OC12 ASICs.

2. Gene Cernilli
1713 Yateley Lane • Apex, NC 27502
M:919-302-5304 • H:919-363-8190
gcernilli@gmail.com • http://www.linkedin.com/in/cernilli
2
Professional Experience
Viavi Solutions, Morrisville North Carolina Mar 2016—Aug 2016
Hardware Development Engineer, Contract
Oversaw prototype development of thermal enclosure for 2 smart-phones. Product was to be used in
wireless network testing. Compiled requirements with input from mechanical engineering, software,
marketing and project management. Wrote design specifications, coordinated EMC/Safety testing.
Ordered parts. Built and thermal tested prototypes. Development met schedule and was successfully
demonstrated to customer.
Qualcomm, Raleigh, North Carolina Dec 2014—Sep 2015
Emulation Engineer, Contract
Instantiated ASIC RTL for server processors on in-house, Xilinx XC7V2000T and Ultrascale based
emulation platforms used in hardware and software verification testing. Adapted RTL for FPGA
environment. Ran synthesis with Synopsis Synplify, and place and route with Xilinx Vivado. Generated
PLL IP and ran static timing analysis in Vivado. Generated tcl timing and placement constraints.
Generated Xilinx binaries for use in verification test. Ran regression tests on overall platform. Probed
and debugged individual subsystems in lab as needed. Effort involved as many as 10 to ~100 Vertex 7
or Ultrascale FPGAs, working with 10 engineers with similar assignments. Emulation and verification
testing allowed for bug discovery and repair prior to initial tape-out, shortening overall development
time.
Optic Angle, Morrisville, North Carolina Oct 2014—Nov 2014
Design Engineer, Contract
Designed and implemented Analog Devices AD7390 10-bit video encoder-based medical video device.
Chose video format and camera/encoder interface, selected components, drew schematics and laid out
board using Altium Designer. Camera exceeded design requirements and was demonstrated to
investors 2 months ahead of scheduled.
Ultra Electronics, 3 Phoenix, Wake Forest, North Carolina Mar 2012—Sep 2014
Lead Systems Engineer
System engineer and technical lead for multi-channel sonar front-end and telemetry. Interfaced with
customer, reported at customer led design reviews, analyzed and adjusted customer requirements,
specified system architecture, lead cross-functional development team, planned staffing and schedule,
ran peer design reviews, interfaced with project management and contract manufacturing, wrote test
code , and wrote and performed factory acceptance and performance verification test procedures.
Product was successfully tested to have met all requirements, and was delivered on time to customer
for system prototype development. Required secret clearance.
Mustard Tree Instruments, Durham, North Carolina Feb 2011—Feb 2012
Senior Engineer
Architected and implemented control and power designs of Raman Spectrometer using ARM9 based
Gumstix Overo/Tobi, TI TPS23754 POE+ controller, ON Semiconductor AMIS-30623 Stepper Motor
Driver, and discrete NPN and NFET circuitry. Chose design tools. Created component libraries for
layout and schematic capture. Designed and laid out circuit cards. Designed and used industry
standard formats for release documentation package. Chose and interfaced with ISO9000 certified
contract manufacturer. Tested and debugged resulting circuit cards. Product was successfully
prototyped and shown to customers.

3. Gene Cernilli
1713 Yateley Lane • Apex, NC 27502
M:919-302-5304 • H:919-363-8190
gcernilli@gmail.com • http://www.linkedin.com/in/cernilli
3
Professional Experience
Aviat Network, Morrisville, North Carolina Feb 2010—Feb 2011
Senior Engineer
Worked with team members on design, development and release of two Marvell Bobcat based Ethernet
Switch cards. Tested ARM9 Microprocessor, including DDR2 and NAND FLASH. Tested Ethernet
routing through switch at PCB level. Designed and implemented LTC3850 based switching power
supplies. Projects met budget and were on schedule.
Alcatel-Lucent, Raleigh, North Carolina 1992—2009
Staff Engineer
 Designed, developed and released the following PCBs: Video Encoder, Sonar Telemetry, IP to
ATM Interface, Ethernet to GPON Interface, and Ethernet to SONET Interface, Microprocessor
Controller for SONET ADM.
 Technical lead in design and development of system controllers, line cards and Optical Network
Terminations. These projects were released and deployed on time, meeting customer
requirements in first-to-market SONET and GPON products.
 Architected and implemented Verilog design of OC48 and OC12 line, section and path transmit
overhead functions of OC48 and OC12 ASICs.
 Performed static timing analysis of a 4xDS3 ASIC, with over 300 clock domains, using IBM’s
Einstimer static violations. Successfully released and deployed product.
 Developed and maintained design data webpage, allowing for in-house access to hardware
documentation. Data was thereby quickly obtainable, resulting in a streamlined hardware
development process.
Professional Development
 2009, Capability Maturity Model Integrated (CMMI) v1.2, and Standard CMMI Appraisal Method
for Process Improvement (SCAMPI) v1.2 training.
 Discussion Panelist: The Intranet - How it's used Today for Collaborative Design and Project
Management. 1998 International Verilog HDL Conference and VHDL International Users Forum,
Santa Clara CA, March 19, 1998.
 Member IEEE