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Using FPGA in Embedded Devices
Andriy Smolskyy
Consultant, Engineering
29.03.2017

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What is FPGA?

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• Transistor-Transistor Logic - TTL
• Programmable Array Logic - PAL
• Programmable Logic Device – PLD
• Complex PLD – CPLD
• FPGA
• ASIC
History of Programmable Logic

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Digital Design with TTL Logic
Truth table

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Digital Design with TTL Logic
Truth table Karnaugh map

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Digital Design with TTL Logic
Truth table Karnaugh map
Logic
expression

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Digital Design with TTL Logic
Truth table Karnaugh map
Logic
expression
Final implementation

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• Logic gates and registers are fixed
• Programmable sum of products array and
output control
Programmable Array Logic (PAL)
Implementation
Advantages
• Fewer devices required
• Lower cost
• Power savings
• Simpler to test and debug
• Design security (prevent reverse engineering)
• In-system reprogrammability! (in some
cases)

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From PAL to Programmable Logic Device (PLD)
• Arrange multiple PAL arrays in a single
device

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• Combine multiple PLDs in single device with
programmable interconnect and I/O
From PLD to Complex PLD (CPLD)
Implementation
Advantages
• Ample amounts of logic and advanced
configurable I/Os
• Programmable routing
• Instant on
• Non-volatile configuration
• Reprogrammable

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Interconnection Problem: Routing Takes Too Much
SpaceGlobal Routing Row & Column Routing

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• LUT inputs are mux select lines
• FPGA LABs made up of logic elements (LEs) instead
of product terms and macrocells
• Solves the Interconnection Problem
FPGA LUT and LAB

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• LABs arranged in an array
• Programmable interconnect
• Interconnect may span all or part of the array
Field Programmable Gate Array (FPGA)
Implementation
Advantages
• Easier to create complex functions through
LE cascading
• Integration of ready functions and IP blocks:
PLLs, memory, arithmetic
• High density, high performance
• Fast programming

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• Pros:
- Fast time to Market: easy to develop a new device
with specific logic or interfaces
- Easy to upgrade device logic, fix bugs in hardware
- Specific devices: reconfigurable DSP, digital filters
• Cons:
- Need to be programmed at power on
- It is hard to achieve 100% device utilization
FPGA vs ASIC
• Pros:
- Higher performance: consume less power and
can operate faster on higher speed
- Cheaper in mass production
- No configuration at power-on required
- Smaller chip size
• Cons:
- Additional expenses in design preparation
- Impossible to fix hardware bugs
FPGA ASIC

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Software and hardware development aspects

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System on Chip (SoC) + FPGA

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• In general FPGA generated controllers are similar to Microcontrollers’
peripheral devices
• FPGA requires programming of each start, controllers might be not
ready at the system start
• Take care with DMA, MMU, virtual memory and caching operations
• In some designs FPGA can control CPU peripheral devices
Software and hardware development aspects

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• Verilog
• VDHL
• Visual development
FPGA design development

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• Core IP
- SDRAM Controllers
- Ethernet PHY, Custom Transceiver
PHY
- PCIe PHY
- SDi, Display Port
• Megafunctions
- PLL
- I/O
- Custom logic blocks
FPGA design development

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High speed data processing: OpenCL
in FPGA

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A simple CPU

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Load immediate value into register

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Load memory value into register

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Store register value into memory

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Add two registers, store result in register

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A simple program
Mem[100] += 42 * Mem[101]
CPU instructions:
R0  Load Mem[100]
R1  Load Mem[101]
R2  Load #42
R2  Mul R1, R2
R0  Add R2, R0
Store R0  Mem[100]

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Single CPU activity, step by step
Time

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Unroll the CPU hardware…
Space

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… and specialize by position
1. Instructions are fixed. Remove “Fetch”

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… and specialize
1. Instructions are fixed. Remove “Fetch”
2. Remove unused ALU operations

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… and specialize
1. Instructions are fixed. Remove “Fetch”
2. Remove unused ALU operations
3. Remove unused Load / Store

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… and specialize
1. Instructions are fixed. Remove “Fetch”
2. Remove unused ALU operations
3. Remove unused Load / Store
4. Wire up registers properly. And propagate
state.

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… and specialize
1. Instructions are fixed. Remove “Fetch”
2. Remove unused ALU operations
3. Remove unused Load / Store
4. Wire up registers properly. And propagate
state
5. Remove dead data

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… and specialize
1. Instructions are fixed. Remove “Fetch”
2. Remove unused ALU operations
3. Remove unused Load / Store
4. Wire up registers properly. And propagate
state
5. Remove dead data
6. Reschedule!

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FPGA datapath = Your algorithm, in silicon
• Build exactly what you need:
- Operations
- Data widths
- Memory size, configuration
• Efficiency:
- Throughput
- Latency
- Power

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OpenCL  FPGA
• Host + Accelerator Programming Model
• Sequential Host program on microprocessor
• Function offload onto a highly parallel
accelerator device
main() {
read_data( … );
maninpulate( … );
clEnqueueWriteBuffer( … );
clEnqueueNDRange(…,sum,…);
clEnqueueReadBuffer( … );
display_result( … );
}
__kernel void
sum(__global float *a,
__global float *b,
__global float *y)
{
int gid = get_global_id(0);
y[gid] = a[gid] + b[gid];
}
Host Code
FPGA Design
User Application
Algorithm

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Loop Pipelining
• Analyze any dependencies between
iterations
• Schedule these operations
• Launch the next iteration as soon as
possible
float array[M];
for (int i=0; i < n*numSets; i++)
{
for (int j=0; j < M-1; j++)
array[j] = array[j+1];
array[M-1] = a[i];
for (int j=0; j < M; j++)
answer[i] += array[j] * coefs[j];
}
At this point, we can
launch the next iteration

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Loop Pipelining Example
With Loop PipeliningNo Loop Pipelining
Looks almost like parallel
thread execution

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Digital Filter
z-1
z-1
z-1
z-1
z-1
z-1
z-1
X X X X X X X X
C0 C1 C2 C3 C4 C5 C6 C7
x(n)
+
y(n)

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• Q&A
FPGA in Embedded Devices

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Thank you
Andriy Smolskyy
Consultant, Engineering
andriy.smolskyy@globallogic.com
+380-67-701-8637