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Backplane hsd meeting_may_8th_2012_sharable
1. Welcome for HSD Success in the
Multigigabit/s Era
Dr. Hany Fahmy, Master High-Speed-Digital Application Expert
Agilent EEsof EDA
April 25th , 2012
1
2. High-Quality Assurance of Success
• EEsof rides the wave of HSD by wearing the shoes of the HSD
Designers
• Don’t provide “JUST-TOOLS” but Provide “DESIGN-WORKFLOW”
• Understands the “Pain” our Customers in designing Multigigabit
Technology
• Strive to Adapt the needs of our Customers through “Continuous
Improvement” of our Design-Flow
Confidentiality Label
2 May 8, 2012
3. Design and Analysis of ATCA 14-Slot Dual
Star 10G ETHERNET Backplane
10GBps per lane (10x10 100GBps)
Towards 25GBps per lane (4x25 100GBps)
Confidentiality Label
3 May 8, 2012
4. Agenda
1) Simulation Setup for the Blade
2) I/O driver Setup
3) Blade-2-Blade Investigation
4) Simulation Setup for the Backplane
5) Blade-2-Backplane-2-Blade Investigation
6) Backplane Via Structure Sensitivity Analysis and Optimization
7) Conclusion
08.05.2012
4
6. Building blocks of the Blade
IC Package: coupled model w BGA Balls
08.05.2012
6
7. Stackup Parameters for the Blade
RD name: Sam Cheng #1254
Manufacturer: 博智
Model Name: MIC-5332
PCB Thickness: 2.4 mm ± 10 %
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La ye r Thickne ss 需要微調各疊
Na me Ma te ria l Cons ta nt
Num. (mil) 層厚度
(Er)
Solde rMa sk --- --- 0.7 4.2
1 TOP Plated Copper Foil 0.5 oz 1.6
Prepreg 1080 2.8 4.1
2 L2_GND Copper foil 0.5oz 0.6
Core Core 4 4
3 L3 Copper foil 0.5oz 0.6
Prepreg Prepreg 10 4.3
4 L4_GND Copper foil 0.5oz 0.6
Core Core 4 4
5 L5 Copper foil 0.5oz 0.6
Prepreg Prepreg 10 4.3
6 L6_PW R Copper foil 1.0oz 1.2
Core Core 4 4
7 L7 Copper foil 1.0oz 1.2
※ Prepreg Prepreg 10 4.3
8 L8 Copper foil 1.0oz 1.2
Core Core 4 4
9 L9_PW R/GND Copper foil 1.0oz 1.2
Prepreg Prepreg 10 4.3
10 L10 Copper foil 0.5oz 0.6
Core Core 4 4
11 L11_GND Copper foil 0.5oz 0.6
Prepreg Prepreg 10 4.3
12 L12 Copper foil 0.5oz 0.6
Core Core 4 4
13 L13_GND Copper foil 0.5oz 0.6
Prepreg 1080 2.8 4.1
14 BOT Plated Copper Foil 0.5 oz 1.6
Solde rMa sk --- --- 0.7
Board Thickness (mil) 92.4
Total Thickness (mil) 93.8 (
Total Thickness (mm) 2.383 (
Confidentiality Label
7 May 8, 2012
8. STUDYING THE TARGET
IMPEDANCE ROUTING OF THE
BLADE
Confidentiality Label
8 May 8, 2012
9. BACKPLANE DESIGN WORKFLOW
STACKUP DEVELOPMENT
STACKUP
2D MOM
DEVELOPMENT
PCB MATERIAL
PROPERTIES MET
IMPEDANCE
TARGET?
Confidentiality Label
9 May 8, 2012
10. Realizing the Stackup in Multi-layer Library in ADS
Deck: Impedance_compliance_tests-1
Confidentiality Label
10 May 8, 2012
19. TDR Analysis of the Blade-VIA
The Via drops down the impedance to 82-ohms by 18-ohms
Confidentiality Label
19 May 8, 2012
20. DEMO FOR THE BLADE-VIA MODELING IN MOM
Confidentiality Label
20 May 8, 2012
21. Building blocks of the Blade
Bottom layer or Inner-layer routing
Break-in connector-pad: 975-mils
Mismatch-TL: 50-mils
Cap-2-ZD Connector-pad TL
on
Bottom or Inner layers: 1250-
mils
08.05.2012 21
22. Building blocks of the Blade
Bottom-2-Top or
Inner-2-Top ZD Connector PIN-FIELD
BOTTOM-2-TOP VIA FOR INNER-2-TOP VIA FOR
CONNECTOR CONNECTOR
08.05.2012 22
23. DEMO FOR THE BLADE DECK CONSTRUCTION
Confidentiality Label
23 May 8, 2012
24. Agenda
1) Simulation Setup for the Blade
2) I/O driver Setup
3) Blade-2-Blade Investigation
4) Simulation Setup for the Backplane
5) Blade-2-Backplane-2-Blade Investigation
6) Backplane Via Structure Sensitivity Analysis and Optimization
7) Conclusion
08.05.2012
24
25. I/O driver Setup
Target Rate is 6.25GB/s
Rise-time=30ps & 20ps
Ron 100-ohms & 90-ohms
De-Emphasis is 5dB with
Tap-interval of 0.4 UI & 0.5 UI Test-load
Jitter = 0.01 UI
08.05.2012
25
38. Compare (85Ω-12%) to (100Ω-10%)
WITH THE BLADE VIAS
85W TO 100W
Eye-heigth:280mV to 516mV
08.05.2012
Eye-width: 100ps to 125ps
38
Jitter-PP: 56ps to 32ps
39. Recommendations for Blade Routing
Target impedance of 100-ohms is better than 85-ohms:
• Width increase by ~ 25ps
• Height increase by 240mV
• Jitter PP reduces by ~ 25ps
Via Transition Modeling is VERY CRITICAL
08.05.2012
39
40. Recommendations for Blade Routing, Contd.
Via Structure should be optimized
• To target impedance (minimum impedance drop for TDR analysis)
• And include Backdrillling
AC Coupling caps should be optimized (e. g. cutout underneath
for better impedance matching)
Avoid routing near cutouts at connector pin field region
08.05.2012 40
41. Agenda
1) Simulation Setup for the Blade
2) I/O driver Setup
3) Blade-2-Blade Investigation
4) Simulation Setup for the Backplane
5) Blade-2-Backplane-2-Blade Investigation
6) Backplane Via Structure Sensitivity Analysis and Optimization
7) Conclusion
08.05.2012
41
58. Do we still have 5/7/5 optimum routing
of BP-channel with Via-BP with
Supplement-GND plane?
Sweeping width from 3.5-mils to 5.5-mils
Sweeping Spacing from 5-mils to 11-mils
08.05.2012
58
59. DEMO BACKPLANE CHANNEL CONSTRUCTION
Deck: BP_Channel
Confidentiality Label
59 May 8, 2012
60. Conclusion
5/7/5 routing is the optimum routing (sweeping over HVM)
Shifting the Stackup so that the signal-launch is 6-mils away
from the Bottom Ref-GND plane is critical to control the
impedance of the launch
Adding Supplement-GND plane away from the signal-Launch
by 10-mils improve the Via-BP by ~ 4dB and the whole BP-
channel by 6dB @ 10GHz.
08.05.2012
60
61. Agenda
1) Simulation Setup for the Blade
2) I/O driver Setup
3) Blade-2-Blade Investigation
4) Simulation Setup for the Backplane
5) Blade-2-Backplane-2-Blade Investigation
6) Backplane Via Structure Sensitivity Analysis and Optimization
7) Conclusion
08.05.2012
61
62. Design Focus
• 3D Analysis of the Via-BP as Most-critical Element (minimized
impedance drop to 20-ohms)
• IL & RL Comparison of new-BP Design Compared to
measurements for old-BP
• TDR Analysis of the BP with Connector
• IEEE 802.3ba 2010 Compliance tests of the new BP
• Tx/Rx Equalization Optimization for successful operation at
6.25GBps & 10GBps
• Final Conclusion
62
64. New Stackup with New Material
Core & Pre-preg are 6-mils
Dk = 3.65 @ 10GHz
Loss-Tan = 0.0095 @ 10GHz
64
65. Impedance Compliance for the BP
5/7/5 routing (95-ohms Diff & 54 SE)
Disclaimer: recommend that PCB house build a test-coupon & TDR/TDT the
impedance of the test-sample along with S-parameter Data
65
66. How close MOM Estimate to Polar Estimate for
Impedance Calculation?
54.6 MOM vs. 52.3 Polar 97.6 MOM vs. 95.5 Polar
2-ohms difference in Estimate
Confidentiality Label
66 May 8, 2012
69. Diff IL for the Via-BP up to 15GHz
Dip at ‘m2’ 14GHz
69
70. Diff RL for the Via-BP up to 15GHz
10GHz < Max reflection < 15GHz
70
71. What is the drop-down-Diff-impedance of the Via-
BP?
The via-BP drops the impedance down to 80-ohms
Approximately, it drops the impedance by 20-ohms
71
74. Comparison with measurements
“L13/14/15/16” compared to Simulated IL
(with the connector)
The simulated improvement depends on the Model quality used.
Better correlation to Measurements is obtained with Post-layout
Simulations
+6dB Improvement at 10GHz for the new BP Design
compared to measurements
74
86. BACKPLANE DESIGN WORKFLOW
Meeting the IEEE 802.3ba Target
VIA PARAMETERS 3D MOM
BP TL ROUTING
PCB MATERIAL
PROPERTIES MET BP
& STACKUP COMPLIANCE?
2D MOM
MULTI-LAYER
LIBRARY
Confidentiality Label
86 May 8, 2012
101. DEMO SETTING THE TX FIR EQUALIZATION
PARAMETERS
Confidentiality Label
101 May 8, 2012
102. Conclusion
• Via-BP was shown to dominate the performance of the BP
especially > 5GBps (new-Via-BP causes ONLY 20-ohms to 25-
ohms drop in impedance with TDR analysis)
• New Material + stackup + via-BP +6dB improvement in IL @
10GHz for worst-BP-channel (longest with longest stub) passes
all Compliance tests IEEE 802.3ba 2010
• Tx FIR & Rx DFE Equalization helps open the eye for higher data
rates of 6.25GBps and above
• successful FIR settings of Tx & DFE settings of Rx was shown @
6.25GBps & 10GBps
102
104. In Statistical Channel simulation mode, can we use
RX adaptive DFE in simulation and output DFE
taps?
For example, Broadcomm warplite_kr rx AMI
model, there is no Getwave function, but it include
DFE and there is no problem to run DFE channel
simulation. Altera S4/S5 AMI model, under
Statistical channel simulation, it is also OK to
include DFE model.
Confidentiality Label
104 May 8, 2012
105. Model’s Init_Returns_Impulse flag
Two Kinds of Tx/Rx Plus is:
False (“Can’t be True (“LTI model
a “Hybrid” modeled as LTI”) via impulse
response”)
Model’s False (“Model is Empty model: not Typical case for
GetWave_Exists pure LTI”) allowed Tx and simple
flag is: Rx’s (fixed Eq.
and no CDR)
True (“NLTV Typical case for Buyer beware:
model via Rx (Adaptive Eq., LTI approximation
waveform CDR) of NLTV device if
modification”) used in stat mode
105
106. Tx model’s Init_Returns_Impulse
flag is:
Channel Simulator: False (“Tx True (“Tx can be
Statistical Mode cannot be modeled as LTI
modeled as using
LTI”) AMI_Init()”)
Rx model’s False (“Rx
Init_Returns_Impulse cannot be
flag is: modeled as LTI”)
True (“Rx can be “Case 1”
modeled as LTI
using AMI_Init()”)
106
107. Tx model’s GetWave_Exists flag is:
False (“Tx has True (“Tx
Channel Simulator:
no NLTV models NLTV by
Bit-by-bit mode character”) modifying
waveform”)
Rx model’s False (“Rx has “Case 2” “Case 5”
GetWave_Exists no NLTV (Practically never
flag is: character”) used)
True (“Rx “Case 3” (Most “Case 4”
models NLTV by common case)
modifying
waveform”)
107
108. Five Cases
Mode Bit pattern? Tx Analog & Rx
Channel
1 Statistical None: stochastic LTI LTI LTI
properties of
infinite bit pattern
2 Bit-by-bit Any finite bit LTI LTI* LTI
pattern
3 Bit-by-bit Any finite bit LTI LTI* NLTV
pattern
4 Bit-by-bit Any finite bit NLTV LTI* NLTV
pattern
5 Bit-by-bit Any finite bit NLTV LTI LTI
pattern
*ADS can handle NLTV mid-channel repeaters
using a proprietary extension
108
109. Pre-Work for Thru Channel: All 5 Cases
1. Analog and
channel impulse
response
2. “Smart” convolve
with Tx
3. “Smart” convolve
with Rx
109
110. Case 1: Statistical Mode
Tx and Rx modeled by their impulse responses
Eye pattern diagram (density, BER contours, bathtubs)
calculated directly from pre-work:
…using statistical methods that include jitter and crosstalk
handling
110
111. Case 3: Bit-by-bit Mode: Tx modeled by impulse
response, Rx modeled by waveform modification
1. Bit pattern:
2. Convolve with composite analog/channel/Tx impulse:
3. Modify waveform using Rx model algorithm:
4. Eye pattern diagram from Rx output waveform
• Details of jitter handling in next slide…
111
112. Two Methods of Handling Rx Jitter
1) When clock ticks are available:
bit-by-bit and clock ticks available from Rx
GetWave
…waveform segments between [tick, tick+UI]
are used to construct the eye to capture Rx
sample time jitter. Eye is centered at tick+UI/2.
eye center @ tick+UI/2
tick 1 tick 3
UI
UI
UI
tick 2
2) When clock ticks are not available, Rx_Clock_PDF is convolved with
eye pattern diagram:
• Statistical mode
• Bit-by-bit mode but no clock ticks
112
