Personal Information
Entreprise/Lieu de travail
Cambridge, Massachusetts United States
Profession
Sr. Engineering Manager, IEEE Fellow
Secteur d’activité
Electronics / Computer Hardware
Site Web
hsienhsinlee.github.io/
À propos
My 25-year working experiences span across a wide range in computing architecture, applications, and IC design including CPU architecture, parallel computing, code optimization, low-power, security hardware, datacenter computing, systems for machine learning, 3D ICs, back-end physical design, and EDA tools.
Mots-clés
computer architecture
logic design
dram
sram
logic synthesis
memory hierarchy
caches
risc
program execution
state machine
fsm
sequential logic
finite state machine
combinational logic
logic minimization
cmos
nor
nand
inverter
coherence
cmp
disk
prefetch
p6
microarchitecture
vliw
epic
cisc
program control
data path
microcode
control flow
instruction execution
program counter
mips
instruction set architecture
isa
rom
bit cells
memory
registers
toggle celled
counter
flip-flops
register
shifter
multiplier
barrel shifter
subtractor
adder
parity checker
comparator
gate
encoder
decoder
timing diagram
mux
multiplexor
mixed logic
quinn-mccluskey algorithm
karaugh map
k-map
canonical function
sop
pos
demorgan law
boolean algebra
xor
logic gates
switch
and
switches
hex
number conversion
binary
computer engineering
explicit parallel instruction computing
data speculation
static scheduling
directory-based cohference
snooping coherence
multiprocessor
snoop protocol
directory based protocol
parallel architecture
smp
chip multiprocessor
symmetric multiprocessor
chip multiprocessors
many core
multicore
pentium 4
pentium pro
raid
memory architecture
netburst
rob
rat
register renaming
reorder buffer
cdc6600
scoreboard
tomasulo algorithm
ibm360/91
instruction fetch unit
processor
branch predictors
speculation
performance
ilp
instruction level parallelism
Tout plus
Présentations
(37)J’aime
(3)Physical design
Mantra VLSI
•
il y a 9 ans
Lec5 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Branch Predictor
Hsien-Hsin Sean Lee, Ph.D.
•
il y a 8 ans
Lec18 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Instruction Set Architecture
Hsien-Hsin Sean Lee, Ph.D.
•
il y a 8 ans
Personal Information
Entreprise/Lieu de travail
Cambridge, Massachusetts United States
Profession
Sr. Engineering Manager, IEEE Fellow
Secteur d’activité
Electronics / Computer Hardware
Site Web
hsienhsinlee.github.io/
À propos
My 25-year working experiences span across a wide range in computing architecture, applications, and IC design including CPU architecture, parallel computing, code optimization, low-power, security hardware, datacenter computing, systems for machine learning, 3D ICs, back-end physical design, and EDA tools.
Mots-clés
computer architecture
logic design
dram
sram
logic synthesis
memory hierarchy
caches
risc
program execution
state machine
fsm
sequential logic
finite state machine
combinational logic
logic minimization
cmos
nor
nand
inverter
coherence
cmp
disk
prefetch
p6
microarchitecture
vliw
epic
cisc
program control
data path
microcode
control flow
instruction execution
program counter
mips
instruction set architecture
isa
rom
bit cells
memory
registers
toggle celled
counter
flip-flops
register
shifter
multiplier
barrel shifter
subtractor
adder
parity checker
comparator
gate
encoder
decoder
timing diagram
mux
multiplexor
mixed logic
quinn-mccluskey algorithm
karaugh map
k-map
canonical function
sop
pos
demorgan law
boolean algebra
xor
logic gates
switch
and
switches
hex
number conversion
binary
computer engineering
explicit parallel instruction computing
data speculation
static scheduling
directory-based cohference
snooping coherence
multiprocessor
snoop protocol
directory based protocol
parallel architecture
smp
chip multiprocessor
symmetric multiprocessor
chip multiprocessors
many core
multicore
pentium 4
pentium pro
raid
memory architecture
netburst
rob
rat
register renaming
reorder buffer
cdc6600
scoreboard
tomasulo algorithm
ibm360/91
instruction fetch unit
processor
branch predictors
speculation
performance
ilp
instruction level parallelism
Tout plus