Implementing minimum energy-point systems with adaptive logic

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Implementing Minimum-Energy-Point Systems with
Adaptive Logic
Abstract:
Timing-error-detection (TED)-based systems have been shown to reduce power consumption or
increase yield due to reduced margins. This paper shows that the increased adaptability can be a
great advantage in the system design in addition to the well-known mitigated susceptibility to
ambient and internal variations. Specifically, the design tolerances of the power management are
relaxed to enable even greater system-level energy savings than what can be achieved in the
logic alone. In addition, the system is simultaneously able to operate near the minimum error
point. Here, the power management is a simplified dc–dc converter and the TED is based on time
borrowing. The target application is a single-chip system on chip without external discrete
components; thus, switched capacitors are used for the dc–dc. The proposed architecture of this
paper analysis the logic size, area and power consumption using Xilinx 14.2.
Enhancement of the project:
Existing System:
Furthermore, the energy consumption of transmitting a bit across a given distance does not scale
with Moore’s law as advantageously as the digital processing within a ubiquitous wireless node.
Therefore, the energy cost of wireless transmission will proportionally grow when compared
with digital processing. Increasing the energy efficiency thus requires increasing the amount of
intranode processing to minimize the wireless transmission of data. The processor and the digital
signal processor will thus become one of the, if not the, most important parts to be optimized.
This will be compounded by the increasing functionalities within the node (video compression
and analysis, machine learning, etc.). Ideally, the logic of IoT devices would operate at their
minimum energy point (MEP).

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However, the MEP lies in or near the subthreshold region for many technologies and increased
susceptibility to variance in this region will rapidly reverse the advantage of operating at the
theoretical MEP. Almost equally important will be the role of the power management. For IoT
applications with a small form factor, the goal is to use as few discrete components in the device
as possible. In addition, discrete components also add to the cost of the device. For the part of the
power management, this requirement is best achieved with on-chip switchedcapacitor (SC)
regulators. However, the SC regulators have be designed with sufficiently high efficiency, small
area, and low-voltage ripple.
Disadvantages:
 EDP is high
 Power consumption is high
Proposed System:
Minimum Energy Point
For digital static CMOS logic, when the performance constraints allow, the straightforward
solution to energy frugality is to lower the operating voltage, all the way to the MEP. The MEP
has been proven to exist around 0.2–0.4 V depending on various factors. For process nodes down
to 45 nm, this is in the subthreshold operation region and for smaller process nodes, in the near-
threshold region.
Timing Margins
Although there are many different ways to add design margin in a system, the most
straightforward is to design the system for a lower clock speed, i.e., timing margin. To
completely remove timing margins, the system needs to determine its own operating speed,
thereby operating asynchronously. However, robust computer-automated design (CAD) flows do
not exist for asynchronous logic. Due to the missing CAD and also a difficult verification
process, asynchronous logic has been mostly relegated to the literature.
DESIGNING A MINIMUM-ENERGY-POINT SYSTEM AROUND ADAPTIVE LOGIC

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The MEP denotes the operating point where the energy per operation is minimized. The energy
per cycle is composed of switching and leakage energy. Theoretically, the MEP for static CMOS
logic depends on the CMOS process, the threshold voltage of the process, and activity factor (α)
of the logic.
Timing-Error Prevention:
In our system, we combine TED with time borrowing (TB). When system is timed for zero TB at
normal operation, fractionally late signals can be tolerated without errors occurring in the
system. However, TB sets timing requirements on the stage subsequent from the stage, namely,
the cumulative delay of the two stages cannot exceed the TB window, and therefore TB requires
careful design time planning. Combining TED with TB into TEP conceives a system that can
tolerate late coming signals, but which does not require special arrangements with regard to stage
lengths. The method works as follows: When a late signal arrives, TB occurs normally. TB
events are detected with EDS latches. With TEP, the maximum amount of borrowed time is the
latch transparent time. Thus, recovery is necessary to prevent borrowed time to accumulate
beyond this limit.
Simplified Power Management for Adaptive Logic
For battery-operated systems, the battery voltage VBatt decreases as the battery discharges.
Traditional regulation aims to keep the VDD constant over this battery discharge voltage range.
To maintain high efficiency and ensure a fixed operating voltage, two methods are typically
used: 1) multiple topologies to support a changing VBatt, as shown in Fig. 1(a), or 2) tight
closed-loop regulation at the output.

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Fig. 1. (a) SC dc–dc converter with i topologies and a digital load ROUT. Traditional systems regulate to a fixed
VDD, using a constant reference voltage (Vref) within the feedback circuitry. (b) As the number of topologies
increase (i.e., from i = 1 to 2), the average efficiency over VBatt is reduced. This effect is more prominent in ULP
applications due to the larger impact of control circuitry losses.
Adaptive Load and Dickson Converter System
The simulated system shown in Fig. 2 consists of a 3:1 Dickson dc–dc converter with an
adaptive TEP load in 28-nm FDSOI. The TEP load includes a dual-phase latch pipeline with five
stages, time borrow detection circuitry, and adaptive clock generator.

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Fig. 6. Ultralow voltage adaptive test system. Left: the dc–dc converter circuit. Right: the TEP adaptive
load.
Advantages:
 EDP is reduced
 Reduce the power consumption
Software implementation:
 Modelsim
 Xilinx ISE

Implementing minimum energy-point systems with adaptive logic

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Implementing minimum energy-point systems with adaptive logic