1. Iffat Anjum (Roll : 16)
Tabassum Tahrin Trisha (Roll : 32)
Bashira Akter Anima (Roll : 48)
Tamanna Yasmin (Roll : 49)
1

2. WWhhyy VVLLSSII??
2
Very Large Scale Integration
 Integration is a technique that allows to build a system with
many more transistors allowing much more computing power
to be applied to solve a problem.
 Integration improves the design:
 lower parasitics = higher speed
 lower power
 physically smaller
 Integration reduces manufacturing cost-(almost) no manual
assembly.

3. WWhhaatt iiss FFPPGGAA??
3
Field Programmable Gate Array
 FPGA were introduced in 1985 by Xilinx.
 Very high logic capacity.
 Consists of an array of programmable logic blocks
surrounded by programmable interconnects.
 Can be configured by end-users to implement specific
applications.
 Capacity up to multi-millions logic gates and speed up to
500MHz.

4. Placement ooff FFPPGGAA iinn DDiiggiittaall LLooggiicc
HHiieerraarrcchhyy
4
Standard
Logic
Standard
Logic
Logic
AASSICIC
Full custom
Full custom
ICs
ICs
Cell-Based
Cell-Based
ICs
ICs
Gate
Arrays
Gate
Arrays
Programmable
Logic Devices
Programmable
Logic Devices
SPLDs CPLDs FPGAs FPICs

5. FFPPGGAA –– AA DDeettaaiilleedd LLooookk
 Based on the principle of functional completeness.
 In it, functionally complete elements (Logic Blocks) placed in
an interconnect framework.
 Interconnection framework comprises of wire segments and
switches.
 Circuits are partitioned to logic block size, mapped and
routed.
LE
LE
LE
Interconnect
network
LE
LE
LE
5

6. BBlloocckk DDiiaaggrraamm ooff aa FFPPGGAA
• The FPGA Consists of
• Logic Element(LE)
• I/O Block
• Programmable
• The FPGA Consists of
• Logic Element(LE)
• I/O Block
• Programmable
Interconnect
Interconnect
6

7. FFPPGGAA aarrcchhiitteeccttuurree
There are three primary
configurable elements in
FPGA :
 Configurable Logic Block(CLB)
- implement different
functions.
 Input/output Block(IOB)
- provides the interface
between external pins and
internal signal lines.
 Programmable Routing
Channel
-controls the connections
7
Routing
Channel

8. Configurable LLooggiicc BBlloocckk((CCLLBB))
8
 Implemented in n-input Lookup Table(LUT).
 A LUT is simply a memory element.
Look-Up Table
Equivalence
Look-Up Table
Equivalence

9. CCoonnffiigguurraabbllee LLooggiicc BBlloocckk((CCLLBB))
9
Simplified Xilinx
CLB
Simplified Xilinx
CLB

10. Configurable LLooggiicc BBlloocckk((CCLLBB))
10
11.. TThhee CCrroossss PPooiinntt bblloocckk::
 Transistors are
interconnected.
 Logic block is
implemented using
transistor pair tiles.

11. Configurable LLooggiicc BBlloocckk((CCLLBB))
11
2.. PPlleesssseeyy bblloocckk ::
 2-input NAND gate
forms basic building
block.
 Static RAM
programming
technology.

12. CCoonnffiigguurraabbllee LLooggiicc BBlloocckk((CCLLBB))
3. The Xilinx Logic Block:
 A SRAM function as a LUT.
 Address line of SRAM as input.
 Output of SRAM gives the logic
output.
12

13. Configurable LLooggiicc BBlloocckk((CCLLBB))
13
44.. AAcctteell llooggiicc bblloocckk ::
 An Actel logic block consists of multiple number of
multiplexers and logic gates.
 If inputs of a multiplexer are connected to a constant or to
a signal, it can be used to implement different logic
functions.

14. IInnppuutt//OOuuttppuutt BBlloocckk((IIOOBB))
14
Two types of IOBs are there
1)Dedicated for configuration of FPGA
2)User Configurable
IInnppuutt//OOuuttppuutt BBlloocckk
 An IOB includes input and output registers, control signals,
muxes and clock signals.
 Unused FPGA inputs should not be left floating.
 Single-ended and differential operational modes are typically
supported

15. IInnppuutt//OOuuttppuutt BBlloocckk((IIOOBB))
15
 The ring of I/O blocks is used to interface the FPGA device to
external components.
FPGA I/O
block.
FPGA I/O
block.

16. Programmable RRoouuttiinngg CChhaannnneell
 Routing Channel-metallic conductor used to make connection.
 Three types are there
 CLB Routing Channel : runs along each row and columns of
CLBs.
 IOB Routing Channel : forms CLB array & connects IOB
with CLB routing channels.
 Global Routing Channel : routes global signals (eg. Clock)
with minimum delay.
 Programmability in routing channels is obtained by using :
(a)connection box and,
(b)switch box
16

17. PPrrooggrraammmmaabbllee RRoouuttiinngg CChhaannnneell
  Connection Box:
connects channel wires
to the i/o pins of CLBs.
  Switch Box:
allow wires to switch
between vertical and
horizontal wires.
Switch
box
Connection
box
17

18. Programmable RRoouuttiinngg CChhaannnneell
Routing channels of CLBs` may be of three types :
 Single length lines span through one CLB & provide short
connections among CLBs.
 Double length line spans two CLBs, offers low routing
delay.
 Long lines run along entire length or width of the array .
 Interconnect Point in both switching and connection box is
implemented through 6 Pass Transistors.
18

19. Programmable IInntteerrccoonnnneeccttiioonn PPooiinntt
 Programmable interconnect points provide the routing
paths used to connect the inputs and outputs of IOBs and
CLBs into logic networks.
D Q
19

20. Programmable wwiirriinngg ppaatthhss
 Organized into channels.
 Many wires per channel.
 Connection between wire made at programmable
interconnection points.
 Must choose:
 Channels from source to destination.
 Wires within the channels
20

21. FPGA RRoouuttiinngg MMaattrriixx aanndd GGlloobbaall
SSiiggnnaallss 21
FFPPGGAA s sigignnaal lR Roouutitningg

22. CChhoooossiinngg aa ppaatthh
22
LE
LE

23. FFPPGGAA MMeemmoorryy
 Two primary types of memory within FPGAs.
 Distributed memory:
Takes advantage of the fact that LUT elements are
implementation of SRAM memory blocks.
 Block memory:
The implementation of dedicated SRAM memory blocks
within the FPGA
23

24. FFPPGGAA DDeessiiggnn
 FPGA manufacturer creates an
FPGA fabric; system designer
uses this fabric.
 FPGA fabric design issues:
 Study sample user designs.
 Select interconnect topology.
 Create logic element
structures.
 Design circuits, layout.
Major levels of
abstraction:
 Specification
 Architecture
 Logic Design
 Circuit Design
 Layout
24

25. CCoonnffiigguurraattiioonn vvss.. PPrrooggrraammmmiinngg
 CPU programming:
 Instructions are fetched from a memory.
 Instructions select complex operations.
add r1, r2 addI Rr1, r2
memory CPU
 FPGA configuration:
 Bits stay at the device they program.
 A configuration bit controls a switch or a logic bit.
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26. AAddvvaannttaaggeess ooff FFPPGGAA
 Small development overhead.
 shorter design cycle.
 No NRE (non-recurring engineering) costs.
 Quick time to market.
 no manufacturing delay.
 Reprogrammable.
 FPGAs reduce inventory.
26

27. DDiissaaddvvaannttaaggeess ooff FFPPGGAA
 Least efficient use of silicon/wiring resources
 Limited size options
 Limited performance
 Not good for high volume applications
 If used for prototyping, still may have significant changes
when migrate to higher performance design and package
solution.
27

28. AA NNOOVVEELL DDEESSIIGGNN OOFF AA
RREEVVEERRSSIIBBLLEE FFIIEELLDD
28
PPRROOGGRRAAMMMMAABBLLEE GGAATTEE AARRRRAAYY

29. UUsseedd RReevveerrssiibbllee GGaatteess
29
FFGG
AA
BB
AA
AA Å B B
AA
BB TTGG
C C
AA
BB
AABBÅ C C
AA
BB FFRRGG
C C
AA
AA’B’B Å A ACC
AABBÅ A A’C’C
D D
BB
Å
Å
AABBCC D D
BB
BSP
Gate
BSP
Gate
AA
C C
AA
AABB C C

30. 44 ttoo 11 MMUUXX
Input S0 S1 Output
I0 0 0 I0
I1 0 1 I1
I2 1 0 I2
I3 1 1 I3
The characteristics equation of a 4-to-1 MUX can be written as
Output =I0 S´0S´1 + I1S´0S1+I2 S0S´1 + I3 S0 S1.
30

31. DDEESSIIGGNN OOFF TTHHEE PPRROOPPOOSSEEDD
RREEVVEERRSSIIBBLLEE 44--11 MMUUXX
Output = I0 S´ 0S´ 1 + I1S´ 0S1+ I2 S0S´ 1 + I3 S0 S1 Output = I0 S´ 0S´ 1 + I1S´ 0S1+ I2 S0S´ 1 + I3 S0 S1
 The first 2 FGs are
used to complement
the select bits (S0, S1)
 BSP gates are used to
generate the 3-input
AND-ed output
 Last 3 FGs are used to
combine the AND
outputs of BSP gates
31

32. CCoommppaarriissoonn
4 to 1 MUX
COMPONENTS AND COST
No of gates Garbage Output
Using Existing Gates 11 13
Ours 9 11
32

33. DD LLaattcchh
Clock D Q
Rising Edge 0 0
Rising Edge 1 1
Non rising X (Don’t Care) Qprev (No change)
33
The characteristics equation of D latch can be
written as,
Q =CD+C’Q

34. DDEESSIIGGNN OOFF TTHHEE PPRROOPPOOSSEEDD
RREEVVEERRSSIIBBLLEE DD--LLAATTCCHH 34
 The FRG is used to generate the output Q =CD+C’Q
 NH gate is used to make the copy and complement of the
generated output

35. CCoommppaarriissoonn
D-Latches COMPONENTS AND COST
No of gates Garbage Output Quantum Cost
Existing circuit
[4]
7 8 48
Existing circuit
[5]
11 12 42
Existing circuit
[6]
5 3 12
Existing circuit
[7]
2 2 10
Proposed 2 2 9
35

36. MMaasstteerr SSllaavvee FFFF
36
 A master–slave D flip-flop is created by connecting two gated
D latches in series, and inverting the enable input to one of
them.
 It is called master–slave because the second latch in the
series only changes in response to a change in the first
(master) latch.

37. DDeessiiggnn ooff tthhee PPpprrooppoosseedd RReevveerrssiibbllee
WWrriittee EEeennaabbllee MMaasstteerr SSllaavvee FFFF
37
 The FRG is used to generate the desired output of the write
enable master slave flip flop.
 The first FG is used make the complement of the Clock
Pulse(CP).
 The D-FFs are used to register the result.
 The last FG is used to make a copy the output so that it can
be fed back to the FRG.

38. CCoommppaarriissoonn
Write Enable
Master Slave FF
COMPONENTS AND COST
No of gates Garbage Output Quantum Cost
Existing circuit
[6]
9 9 38
Ours 7 7 25
38

39. CCoonncclluussiioonn
 Here we presented the design of a first ever proposed
reversible logic block of FPGA.
 The sequential circuits that are used to realize the FPGA
have been improved.
 Efficiency of the proposed circuits is clearly highlighted by
using comparison here.
 The number of gates, number of garbage outputs and
quantum cost have been reduced as well.
39

40. References
40
[1] R. Landauer, “Irreversibility and Heat Generation in the Computational Process”,
IBM Jo urna l o f Re s e a rch a nd De ve lo pm e nt, vol. 3, pp. 183-191, 1961.
[2] C.H. Bennett, “Logical Reversibility of Computation”, IBM J. o f Re s e a rch a nd
De ve lo pm e nt, pp. 525-532, November 1973.
[3] N. Huda, “On the Implementation of Reversible Random Access Memory”, M.Sc.
thesis, Session: 2003-04, Department of CSE , University of Dhaka.
[4] H. Thapliyal, Vinod, A.P.,”Design of Reversible Sequential Elements with
Feasibility of Transistor Implementation”, Circuits and Systems, 2007. ISCAS
2007. IEEE International Symposium on Volume, Issue , 27-30 May 2007
Page(s):625 – 628
[5] H. M. H. Babu, M. R. Islam, A. R. Chowdhury, and S. M. A. Chowdhury,
“Reversible Logic Synthesis for Minimization of Full-Adder Circuit,” IEEE
Conference on Digital System Design 2003; 50-4.
[6] H. M. H. Babu, M. R. Islam, A. R. Chowdhury, and S. M. A. Chowdhury,
“Synthesis of Full-Adder Circuit Using Reversible Logic,” 17th International
Conference on VLSI Design 2004; 757-60.
[7] Richard P. Feynman, “Quantum Mechanical Computers,” Foundations of Physics,
vol. 16, no. 6, pp. 507-531, 1986.

41. TThhaannkk
YYoo uu
41