student_pres120202final

SLSAdvancedDesignMethodologies2002
Philips Semiconductors
Presented by John Marquis
Philips Semiconductors Systems Laboratory Southampton

History Lesson number 1
• One of the First Philips Teletext Decoders
• Teletext Acquisition Control (TAC)
• 1980
Chip Size
Process
No. Gates
Development
Time
50 mm2
6 µm NMOS
3000
4 man years

Today’s Design complexity
• Philips Global Positioning System
• Communication And Reliable Positioning Engine for Telematics (Carpet)
Chip Size
Process
No. Gates
Development
Time
56 mm2
0.25 µm CMOS
1.5 Million
30-40 man years

Today’s Design complexity (2)
• Intel Pentium III
Chip Size
Process
No. Gates
Development
Time
106 mm2
0.18 µmCMOS
28 Million
??? years

0.6µ
1994
0.5µ
1995
0.35µ
1996
0.25µ
1997
0.2µ
1998
0.15µ
1999
LogScale
380K
603K
957K
1,520K
2,410K
3,830K
Gates/cm
2
Moore’s Law
100K
125K
156K
195K
244K
305K Average CB Design
IncreasingGap
Reducing the Widening Productivity Gap

The increasing pace of change in Electronics
Time-to-market gets shorter and shorter
• We need to demonstrate our concepts early.
• Build competence (not always silicon)
• Demonstrate function/concept
• Try different architectures/designs
• Develop & Test new HDL IP blocks fast.
• Show System functionality before Silicon exists.
• Allow early Software Development.
• Replicate Prototypes for “Customers”
Philips Semiconductors’ Nexperia™
Silicon System Platforms allow new waves
of creativity to happen today

We
Need
Design Tools & Methods

SLS ADM
The Need for Advanced Design MethodologiesAdvanced Design Methodologies
TimeTime
ComplexityComplexity SystemSystem
S/W & H/WS/W & H/W
Physical PlatformPhysical Platform
complexitycomplexity
SLS Advanced Design MethodologiesSLS Advanced Design Methodologies
provide the required competencies toprovide the required competencies to
manage future System S/W & H/Wmanage future System S/W & H/W
design complexitiesdesign complexities
UMLUML
Handel CHandel C
System CSystem C
PurePure
MagicMagic
VHDLVHDL
VerilogVerilog
AutomaticAutomatic
Platform BuildingPlatform Building
ToolsTools
SchematicSchematic
CaptureCapture
ManuallyManually
builtbuilt

Prototyping Platforms
Design Verification
Design VerificationProof of Concept
Proof of Concept
C/C++C/C++
toto
HardwareHardware
RTLRTL
toto
HardwareHardware
ARMARM
ProcessorProcessor
FPGAFPGA
VerticalVertical
QuickTurnQuickTurn
NapaNapa
XplorerXplorer
PreDictPreDict
FPGAFPGA
PrototypesPrototypes
FPGAFPGA
VerticalVertical
ProcessorProcessor
C to H/WC to H/W
ProcessorProcessor
FPGAFPGA
VerticalVertical
C to H/WC to H/W
ProcessorProcessor
FPGAFPGA
VerticalVerticalFPGAFPGA
VerticalVertical
C to H/WC to H/W

Philips Prototype Platforms.
• Xplorer
• The Generic FPGA
• ITCL
• The Generic II
• Nat Lab

Example of a Xplorer Prorotype System
FPGA
672
SDRAM
Microprocessor Tile
PSU
X board
Clock
Tile
Interface board
FPGA
672

Configuration for each FPGA tile
FPGA
672
Tile Configuration
•Type of FPGA
eg 20k400 or20k100
•Global Clocks & Reset
•Jumper setting
FPGA
672

Simple way to describe connections to the real world
Interface board
Interface to real world
•Logic Analyser probes
•Memory modules
SDRAM

Describing connection between each xplorer tile
FPGA
672
SDRAM
Microprocessor Tile
PSU
X board
Clock
Tile
Interface board
FPGA
672
Board interconnect
•Description of how you
connect from module
to another.
•Both Horizontally and Vertically

The Prototype can also be built vertically
FPGA 672
FPGA 672
FPGA 672
FPGA 672
FPGA 672 FPGA 672

Open top allows probing
CPUs/Memory
FPGA card
Peripherals
Backplane allows
probing and logic
analyzer connections
Cards interconnect
through backplane
TOP Bottom
Front panel I/O &
Logic Analyzer
accessible
Ejectors to eject
or insert board
Peripherals
300W Power Supply
Two Drive Bays
Nexperia™
Advanced Prototyping Architecture

Scalable VLIWScalable VLIW
Media Processor:Media Processor:
• 100 to 300+ MHz100 to 300+ MHz
• 32-bit or 64-bit32-bit or 64-bit
NexperiaNexperia™™
System BusesSystem Buses
• 32-128 bit32-128 bit
General-purposeGeneral-purpose
Scalable RISCScalable RISC
ProcessorProcessor
• 50 to 300+ MHz50 to 300+ MHz
• 32-bit or 64-bit32-bit or 64-bit
Library of DeviceLibrary of Device
IP BlocksIP Blocks
• Image coprocessorsImage coprocessors
• DSPsDSPs
• UARTUART
• 13941394
• USBUSB
……and moreand more
TM-xxxxTM-xxxxTM-xxxxTM-xxxx
D$D$D$D$
I$I$I$I$
TriMedia CPUTriMedia CPU
DEVICE IP BLOCKDEVICE IP BLOCKDEVICE IP BLOCKDEVICE IP BLOCK
..
..
..
DVP SYSTEM SILICON
PIBUS
SDRAMSDRAM
MMIMMI
DVPMEMORYBUS
DEVICE IP BLOCKDEVICE IP BLOCK
PRxxxxPRxxxx
D$D$
I$I$
MIPS CPU
.
.
.
PIBUS
TriMediaTriMedia™™MIPSMIPS™™
Nexperia™ DVP (Digital Video Platform)
Hardware Architecture

PrEDICT
PCI
ASP
Tuner front end boardTuner front end board
Cable modem boardCable modem board
Ethernet boardEthernet board
viper board 1viper board 1
viper board 2viper board 2
FPGA boardFPGA board
Back planeBack plane
PCPC cabinetcabinet
Front panelFront panel
DVD
PrEDICT
PHILIPS
Power Supply
Drive Bays
Plug-in BoardsPlug-in Boards
For (I =0;I<x;I++)
{
tm_send(*Z[I]);
a = something
etc.
SDS
Configuration Builder
Host interfaceHost interface
PC tools for system configurationPC tools for system configuration
and High level debuggingand High level debugging
T
PrEDICT

PCI-PCI Bridge
INTEL 21554
Application
FLASH
8 MB, Intel
28F008S3
Serial Boot
ROM
Microchip
93LC66
Clocking
Clocking
JTAG Conn.
Ser. Conn.
Coax Conn.
Secondary PCI bus
- adrress/data & control
Config.
Jumpers
Primary PCI bus
- adrress/data & control
Secondary PCI
bus arbitration
PCISLOT4
PCISLOT5
PCISLOT6
PCISLOT7
PCISLOT3
PCISLOT2
PCISLOT1
Reset
Reset
Reset
Reset
Reset
Reset
Reset
prsnt
prsnt
prsnt
prsnt
prsnt
prsnt
prsnt PCI interrupt
lines ABCD
JTAG(PCI)
JTAG(PCI)
JTAG(PCI)
JTAG(PCI)
JTAG(PCI)
JTAG(PCI)
JTAG(PCI)
SecondaryPCIReset
Primary PCI Reset
Jumper
Block
PCI interrupt
lines ABCD
System IO Controller
Winbond W83C553
IDE Conn.
Primary PCI
bus arbitration
Config.
Jumpers
ISA Addr. Trans.
Altera EPM7064
UART, IrDA and
Parallel Port
TI 16PIR552
Par. Conn.
Ser. Conn.
Experimental
Areas ISA Address
Translation
Use empty IO pins from
switches and
programmable devices
IR Conn.JTAG Conn.
14MHz
Global System Reset
SIOINT
XIO Handler
Altera EPM7512AE
EPLD
Local MIPS PCI Bridge
V3 V320USC
JTAG Conn.
BitBlaster
MIPS/XIO buffer
Xilinx XC95288
DIMM
64 MB FLASH
8 x AMD
AM29LV641
Control
XIO A/D
Control
FLASH D
320 INT
MIPS Control
40.5 MHz
XIO/CS
Control
I2C
Boot ROM
AT24C02
Global System Reset
FLASH CS
I2C0
I2C1
7240_I2C
BUS
SWITCH
4xPericom,
PI3834X245
Dp
Ds
CS/INT
Dp
Ds
CS/INT
Dp
Ds
CS/INT
Dp
Ds
CS/INT
CS/INT_r
BUS
SWITCH
4xPericom,
PI3834X245
BUS
SWITCH
4xPericom,
PI3834X245
ASP0
ASP1
ASP2
ASP3
ASP4
ASP5
ASP6
ASP7
Mictor
Conn.
CS/INT_r CS/INT_r CS/INT_r CS/INT_r CS/INT_r CS/INT_rCS/INT_r
MIPS/ASP
Router
Latice ispGDX160VA
Global System Reset
7240_TS
JTAG
Conn.
Buffered 7240 D
Buffered 7240 A
7240 A
7240 D
CS/INT Router
Latice ispGDX160VA
Global System Reset
MIPS IO Expander
Xilinx XC95288
JTAG Conn.
for programming CPLD
Global CS/INT
JTAG Conn.
for controlling switches
Secondary PCI Reset
Jumpers for
manual mode
PrimaryPCIReset
7240 PIO JTAG
7240 control
188 Devide
JTAG Router
Latice ispGDX160VA
Reset Slot 0
7 x EJTAG Conn.
20 pins Samtec
for internal use
5 x JTAG via
SCSI Conn
LVDS Conv.
SN65LVDS387
Ext. JTAG Conn
Ext. JTAG Conn
Ext. JTAG Conn
Backplane Processor
Philips SAA 7240
Clock
Buffers
40.5 MHz
16MB
SDRAM
2x Samsung
K4S641632
64 MB
FLASH
AMD
AM29LV641
Power
Guard
DS1834A
RS232 Conv.
Maxim
MAX239
Ser. Conn.
RS232 Conv.
DS14C232
Osc.
13MHz
Using National Semicond.
CGS74B2525 Clock Driver
Using National Semicond.
CGS74B2525 Clock Driver
SystemI2C
JTAG
Conn.
GlobalSystemReset
JTAGRESET
40.5 MHz
Coax Conn.
ExternalJTAGConnectors
Ds
Dp Dp
Ds
Dp
Ds
PowerGoodSignal
Primary PCI Reset
Buff.cntr.Buff.cntr.
Buff.Cntr.
Output Enable
OutputEnable
Output EnableJTAG RESET
OutputEnable
Output Enable
PCI Slot Reset
PrODICT Backplane Diagram
Version: Draft 0.2
Date: 19 September 2000
Drawn by: Richard Snijders
PrEDICT Back Plane
Backplane
processor
PCI bus
ASP Bus
Unified boot
memory
JTAG support
(no PC-trace)
CNTRL
PREDICTMODULE1
PREDICTMODULE2
PREDICTMODULE3
PREDICTMODULE4
PREDICTMODULE5
PREDICTMODULE6

Velocity
Rapid Silicon Prototyping (RSP)
Logic Analyzer
HW Emulator
FPGA
Proto Board
Standard
Plug-in Board
JumpStart ARM
Host Compiler
& DebuggerUser Interface
On-Board
GateField FPGA
JTAG
Control
Velocity™ Rapid Silicon
Prototyping System
• From system-on-a-benchtop to system-on-a-chip

RSP9 ASIC Block Diagram
AHB
Arbiter
ARM 946
Complex
JTAGETM
AHB
Decoder
POR
AHB
64K
SRAM
Ext. SRAM
/FLASH
AHB to PCI
/Cardbus
Off-Chip
AHB
PLLs-2
Global
Config
VPB
Power
Mgmt
GPIOs
16550
UART
16550
UART - IR
Off-Chip
VPB
A to D
Interrupt
Control
Timers-4
Fast
I2
C
RTC
nvRAM
USB 1.1
Device
Multi-port
SDRAM
CLCD
Controller
AHB to VPBUSB
System
Performance
Monitor

ARM Integrator System
ARM
Core
Module
SVGA
Epson
SED1356
Ethernet
D - Link
DFE 500TX
Logic
Module
Interface
Module
Analyzer
Module

SLSSLS
Advanced DesignAdvanced Design
MethodologiesMethodologies
Building Design Solutions for the futureBuilding Design Solutions for the future

student_pres120202final

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Viewers also liked

Viewers also liked (20)

Similar to student_pres120202final

Similar to student_pres120202final (20)

student_pres120202final

Editor's Notes