Ce diaporama a bien été signalé.
Nous utilisons votre profil LinkedIn et vos données d’activité pour vous proposer des publicités personnalisées et pertinentes. Vous pouvez changer vos préférences de publicités à tout moment.

KS Resume_3

240 vues

Publié le

  • Soyez le premier à commenter

  • Soyez le premier à aimer ceci

KS Resume_3

  1. 1. CURRICULUM VITAE Name :Ooi Kim Shuan Personal Particulars Permanent Address : 2D-17-9, D’Piazza Condominium, Lengkuk Mayang Pasir 1, 11950, Bayan Baru, Penang. Mobile No. : +6012-5290895 Home No. : +6012-5508220 Email : ooikimshuan@yahoo.com Age : 31 Date of Birth : 08 Apr 1985 Nationality : Malaysia Gender : Male Marital Status : Married IC No. : 850408-02-5035 Permanent Residence : Malaysian Religion : Buddhist Educational Background Highest Education Level : Degree Programme : Bachelor of Engineering (Hons) Degree programme Major : Electrical and Electronics University : Universiti Putra Malaysia Located In : Malaysia Session : 2004/05 Duration : 4 years CGPA : 3.0 Secondary School School : Sekolah Menengah Kebangsaan Keat Hwa Alor Star Major : Science Stream Session : 1998 till 2002 Duration : 5 years Grade : Sijil Pelajaran Malaysia (SPM) 2002 – 5A’s Penilaian Menengah Rendah (PMR) 2000 – 1A’s Primary School School : Sekolah Rendah Jenis Kebangsaan (C) Boon Teik, Tokai, Kedah. Duration : 6 years Session : 1992 till 1997 Grade : Ujian Peperiksaan Sekolah Rendah (UPSR) 1997 - 5A’s 1
  2. 2. Additional Computer Skills Microsoft Word Microsoft Excel Microsoft Power Point Microsoft Access Microsoft FrontPage Altera Quartus II P-spice Altera Maxplus II Matlab C Programming Unigraphic Digsilent Unix Code Languages Skills • English language – fluent speaking and good in writing o Band six (General Certificate of Education Ordinary Level – GCE for the year of 2002) o Band three (Malaysian University English Test – MUET for the year 2003) • Chinese language – fluent in speaking and good in writing o B (Malaysian Certificate of Education - MCE for the year 2002) • Malay language – fluent in speaking and good in writing o B (Malaysian Certificate of Education - MCE for the year 2002)  Other language - Mandarin, Hokkien, Cantonese Final year project Title : Standalone XPC speed control for DC servo Project description: The objective of this project is modifying the connection to standalone and control the DC motor with only using the target PC. I’ve applied Matlab to complete my project with one of the toolbox in Matlab which is XPC Target. I control the speed using the XPC target and I’ll try to get the smooth result by tuning the parameters P, I and D. Smooth result is the result that closest to the set point. Employment History Jul 2014 - Present 1 year 8 months Staff NPI/Product Engineer Broadcom Limited Penang previously known as Avago | Penang, Malaysia Industry: Electrical & Electronics Specialization: Engineering - Electronics/Communication Role: Electronics Engineer Position Level: Senior Executive Job description : -As a Product Owner of HDD SOC and NPI of SSD SOC devices in the company. -Responsible on all the HDD SOC FT production transfer from Shang Hai subcon and Taiwan subcon to ASEM (Advance Semiconductor Malaysia). 2
  3. 3. -Understand product design, features, test program, test methodology, modules (e.g SCAN RC, PHY, SERDES etc.) and involve all the activities for NPI of SSD SOC. -Familiar with NPI characterization method (min, max, mean, stdev, Cpk). -Handle BOM setup for new product introduction inside Oracle system. -Well known with SPC skill set to analyze production low yield issue, engineering test parameters data and correlate the FT failure with wafer fab process. -Familiar with wafer sort process, wafer lot disposition and wafer map/pattern analysis e.g.: wafer edge pattern, row/column pattern, donut pattern at wafer center just to name a few. -Work closely with FAB/Wafer Sort Group to understand all the FAB issue of the new product, understand and study the wafer map of the new products, wafer sort program parameters’ tightening, Test Program Robustness, wafer sorting yield improvement and silicon related issues and solutions. -Work closely with designers, module owners, Tester Program Development Group to understand all the development changes, Test program parameters’ tightening, Test Program Robustness, Products’ test yield improvement and product related issues and solutions. -Handle all the quality and reliability study of the new product e.g. Burn-In, HTOL, HAST, LU, ESD (MM, HBM) in order to make sure our new silicon devices are strong and robust enough to go through mass production before ship to customer. -Responsible on all the CAR RMA Electrical failure analysis (EFA) for all HDD SOC product (wafer level and package level) to identify the root cause. -Responsible for yield improvement and test time reduction e.g mask off/exclude all those low ppm failure test items in order to decrease the test time and increase the throughput of the product. -To monitor/assist/support production yields, quality and issues once the New Product transfer and started mass production (legacy product). -Familiar with UFLEX tester debug features, IGXL interface and functions to debug the rejects/low yield lots and collect Engineering Characterization data in order to observe unit’s performances. -Knowledge in 8D, FMEA, Statistical Process Control and other Statistical Tools (e.g MicroSoft Excel, JMP, Data Conductor). 3
  4. 4. Jun 2012 - Jun 2014 2 years Senior Product Engineer (NPI) Freescale Semiconductor (M) Sdn Bhd | Selangor, Malaysia Industry: Semiconductor/Wafer Fabrication Specialization: Engineering - Electronics/Communication Role: Electronics Engineer Position Level: Senior Executive Company : Freescale Semiconductor Position : Senior Product Engineer (NPI) Duration : June 2012 - June 2014 Industry : Semiconductor Department : Automotive Microcontroller Product Group (Business Unit) Manager : Lew Boon Kiat Job description : - As a Product Owner for NPI of Ultra High Voltage 32kb Automotive Microcontroller (S12Z) devices in the company. -Understand product design, features, test program, test methodology, modules (e.g CAN phy, LIN phy etc.) and involve all the activities for NPI of UHV Automotive Microcontroller. -Work closely with FAB/Wafer Sort Group to understand all the FAB issue of the new product, understand and study the wafer map of the new products, wafer sort program parameters’ tightening, Test Program Robustness, wafer sorting yield improvement and silicon related issues and solutions. -Work closely with designers, module owners, Tester Program Development Group to understand all the development changes, Test program parameters’ tightening, Test Program Robustness, Products’ test yield improvement and product related issues and solutions. -Handle all the quality and reliability study of the new product e.g. Burn-In, HTOL, HAST, LU, ESD (MM, HBM) in order to make sure our new silicon devices are strong and robust enough to go through mass production before ship to customer. -Responsible on Electrical failure analysis (EFA) for all NPI S12Z product (wafer level and package level) to identify the root cause. -Study the failing pattern (Single Bit Failure, Row Failure, Column Failure, etc) in NVM flash memory and encounter some valid/abnormal failures in order to find out the actual root cause and failing location before proceed the failing unit to perform PFA (Physical Failure Analysis ) -Responsible for yield improvement and test time reduction [e.g Room Temp Elimination (RTE)] in order to decrease the test time and 4
  5. 5. increase the throughput of the product. -To monitor/assist/support production yields, quality and issues once the New Product transfer and started mass production (legacy product). -Familiarization with IGXL interface on Teradyne J750, Teradyne MFLEX & IFLEX tester features and functions to verify the rejects units, verify low yield lots and collect the Engineering Characterization data in order to observe unit’s performances. -Well known on benching knowledge for Automotive MCU with the EVB board, curve tracer, oscilloscope to indentify the product’s abnormalities. -Knowledge in 8D, FMEA, Statistic and other Statistical Tools (e.g Microsoft Excel, Mini Tab, JMP). Mar 2011 - Jun 2012 1 year 3 months Product Development and Deployment Engineer ALTERA CORPORATION | Penang, Malaysia Industry: Semiconductor/Wafer Fabrication Specialization: Engineering - Electronics/Communication Role: Electronics Engineer Position Level: Junior Executive New Product Introduction: o Successfully achieve ASOD to proto sample TAT(turnaround time) for 90% of all new customer designs assigned within 8 calendar days o Ensure that all test and device issues encountered are tracked, understood, addressed and fixed for current designs in a timely manner, and propagated to intercept new designs going forward. o Drive for resolution and closure on 80% of all latest Altera ASIC products TPRs (Test Program Change Request) before Q4 end, on all designs assigned before Q3 end, by EOY. Successfully ramp up and stabilize yields WS yields >70%.n 1 new design (out of those assigned) within 3 months of proto shipment. Cost Saving: - Achieve 20% reduction in test times for 1 new 2011 design, by EOY, under criteria that it is filed and approved in the AMAX cost tracker. - Complete test transfer to TSMC/AMKOR for 90% of all new designs assigned, no later than 3 months after proto ship date, or when necessitated by volume. Operational Excellence – Manufacturing Ensure WS yields meet Altera-TSMC DD goal for 2 new 2011 customer designs (prioritized by volume), by EOY. Operational Excellence - Customer Support 5
  6. 6. o Achieve average Hardcopy ERMA (Engineering Return Material Analysis) factory TAT (Turn Around Time) within 5 working days on all ERMAs assigned. o 80% of assigned ERMA closed within 7.5 factory working days. Satisfactorily support all customer issues and special requests when they arise. Organizational Development o Design and deliver 1 effective sharing sessions on the area of Hardcopy testing to the team: - Architecture of block under test - Test methodology Test implementation presentation (vector file familiarization) Jun 2008 - Mar 2011 2 years 9 months Product/Test Engineer Integrated Device Technology | Penang, Malaysia Industry: Electrical & Electronics Specialization: Engineering - Electronics/Communication Role: Electronics Engineer Position Level: Fresh / Entry Level - As a Product Owner for all the Asynchronous SRAM (Static Random Access Memory) devices in the company. -Understand product design, features, test program, test methodology and involve all the activities for Asynchronous SRAM. -Work closely with Tester Program Development Group to understand all the development changes, Test program parameters’ tightening, Products’ test yield improvement and product related issues and solutions. -Responsible on Electrical failure analysis (EFA) for all internal FA (Wafer FAB transfer from IDT FAB4 to TSMC FAB) and Customer Return Unit to localize the failing location. -Study the failing pattern (Single Bit Failure, Row Failure, Column Failure, etc) and encounter some valid/abnormal failures in order to find out the actual root cause and failing location before proceed the failing unit to perform PFA (Physical Failure Analysis ) -To monitor/assist/support all production yields, quality and issues. -Responsible for yield improvement and test time reduction in order to increase the throughput of the Product. -Familiarization on UNIX coding for Teradyne J937 & Teradyne J994 6
  7. 7. Tester and familiar with the function of Teradyne J937 & Teradyne J994 Tester to verify the rejects units, verify low yield lots and collect the Engineering Characterization data to observe unit’s performances. -Collect Engineering Characterization Data for SRAM include AC Test (Speed Test), DC Test & Supply Current Test. -Well known on benching skill for SRAM with the switch box, conversion socket, curve tracer (oscilloscope) to identify the product’s abnormalities. Project Handle in year 2010 (IDT): -Product Wafer Transfer from IDT FAB 4 to TSMC Wafer. -Responsible on supporting reliability test e.g: EOS (Electrical Over Stress) study, ESD (Electrostatic Discharge) Test, LU (Latch Up) Test. -Performed Engineering Qual e.g: Engineering evaluation on TSMC FAB reliability issue or changes during the TSMC FAB process. -Perform and collect Characterization Data on the SRAM unit with IDT wafer vs TSMC wafer. (Wafer performances comparison between TSMC wafer and IDT wafer). -To make sure the TSMC wafers perform equivalent or better than IDT wafer in term of Speed Test, DC test, etc. -Report and feedback to TSMC whenever production low yield with TSMC wafer for seeking improvement and implementation plans to recover the production yield. -Involve In-House Wafer Sort activities whenever TSMC wafers are low yield when tested through IDT’s Wafer Sort prober. -Study the TSMC wafer map failing pattern, identify the die failing location to decide whether the failing die can be recover by using laser process to improve the TSMC wafer yield. Else, will feedback to TSMC immediately for implementing their process. Apr 2007 - Jul 2007 3 months Process Engineer (Trainee) Plexus | Penang, Malaysia Industry: Manufacturing / Production Specialization: Manufacturing/Production Operations Role: Process Engineer Position Level: Non-Executive - This company is providing the PCBA (printed circuit board 7
  8. 8. assembly) services for the OEM companies. For example: Motorola, KLA Tencor, AE(Advance Energy), just to name a few. Trained under this position, I had learned a lot of SMT (surface mount technology) knowledge and process. Besides, I had learned the knowledge to prepare and revise the manual instructions for the operators and technicians. The purposes of these manual instructions are to reduce the burden of the operators and technicians. 8

×