DesignCon 2019 112-Gbps Electrical Interfaces: An OIF Update on CEI-112G Brian Holden, Kandou Bus Cathy Liu, Broadcom Steve Sekel, Keysight Nathan Tracy, TE Connectivity

1. 112-Gbps Electrical Interfaces:
An OIF Update on CEI-112G
Brian Holden, Kandou Bus
Cathy Liu, Broadcom
Steve Sekel, Keysight
Nathan Tracy, TE Connectivity

2. SPEAKERS
Nathan Tracy
OIF President/Board Member, TE Connectivity Technologist
ntracy@te.com
Cathy Liu
OIF Board Member, Broadcom Inc. SerDes Architect
cathyliu@broadcom.com
Steve Sekel
OIF PLL Interop WG chair, Keysight Technologies 400G Solutions Specialist
steve.sekel@keysight.com
Brian Holden
OIF Member, Kandou Bus, VP of Standards
brian@kandou.com
2

3. What is the OIF?
• Since 1998, OIF has brought together industry groups from
the data and optical worlds
• Mission: To foster the development and deployment of
interoperable products and services for data switching and
routing using optical networking technologies
• Our 100+ member companies represent the entire industry
ecosystem:
• Network operators and network users
• Component and systems vendors
• Testing and software companies
1/15/2019 OIF - 2019 3

4. The Challenge
• Allow network operators to
manage the underlying technical
complexity of their networks
• Support vendor innovation while:
• Preserving interoperability
• Maximizing performance
• Minimizing costs
1/15/2019 OIF - 2019 4

5. Roadblocks to Progress
• Proprietary solutions
• Lacking or lagging standards
• Lack of opportunities for collaboration
OIF Removes those Roadblocks
• Building industry consensus
• Contributing to formal standard bodies
• Accelerating progress through collaboration
1/15/2019 OIF - 2019 5

6. OIF Offers a Formal Process for:
• Identifying gaps and presenting new ideas
• Selecting among the best ideas and creating
work projects
• Drafting and adopting Implementation
Agreements
• Proving concepts through interoperability
demos
• Presenting proposals to formal standards bodies
1/15/2019 OIF - 2019 6

7. How OIF is Organized
Market
Awareness
and
Education
Committee
Technical Committee
Board of Directors
Networking
& Operations
WG
Interop
WG
Physical &
Link Layer
WG
NetOp
WG
Physical
Layer User
Group
Interoperability
Demonstrations
Implementation
Agreements
Implementation
Agreements
1/15/2019 OIF - 2019 7

8. Electrical Implementation Agreements
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019
SxI-5 CEI-1.0 CEI-2.0 CEI-3.0
6G
11G 25G & 28G
56G
CEI-3.1 CEI-4.0
112G
 CEI IA is a clause-based format supporting publication of new clauses over time:
 CEI-1.0: included CEI-6G-SR, CEI-6G-LR, and CEI-11G-SR clauses.
 CEI-2.0: added CEI-11G-LR clause
 CEI-3.0: added work from CEI-25G-LR, CEI-28G-SR
 CEI-3.1: added work from CEI-28G-MR and CEI-28G-VSR
 CEI-11G and -28G specifications have been used as a basis for specifications developed in IEEE 802.3, ANSI/INCITS T11, and IBTA.
 CEI 56G projects have recently completed in 2017: http://www.oiforum.com/wp-content/uploads/OIF-CEI-04.0.pdf
 LR: backplane
 MR: chip to chip
 VSR: chip to module
 XSR: chip to optics engine (separate chips)
 USR: chip to optics engine (2.5D or 3D package)
 CEI 112G project is in process
1/15/2019 OIF - 2019 8

9. OIF CEI-56G Application Space
CEI applications
target different
“reach” (loss)
applications.
CEI-56G-LR Chip Chip
Backplane or Passive Copper Cable
LR: Interface for chip-to-chip over
a backplane
• 100 cm, 2 connectors
• 35 dB loss at 14 GHz
CEI-56G-MR Chip Chip
Chip-to-Chip & Midplane Applications
MR: Interface for chip-to-chip and
midrange backplane
• 50 cm, 1 connector
• 15-25 dB loss at 14 GHz
• 20-50 dB loss at 28 GHz
CEI-56G-VSR Chip
Pluggable
Optics
Chip to Module
VSR: Chip-to-Module interfaces
• 10 cm, 1 connector
• 10-20 dB loss at 28 GHz
CEI-56G-XSR Chip Optics
Chip to Nearby
Optics Engine
XSR: Chip to nearby optics engine
or LR driver chip
• 5 cm, no connectors
• 5-10 dB loss at 28 GHz
CEI-56G-USR
3D Stack
USR: 2.5D/3D die-to-die applications
• 1 cm, no connectors, no packages
2.5D Chip-to-OE
2.5D Chip-to-OE
1/15/2019 OIF - 2019 9

10. Name Rate per pair Year Activities that Adopted, Adapted or were influenced
by the OIF CEI
CEI-112G 112Gbps 201X Five channel reach projects in progress
CEI-56G 56Gbps 2017 IEEE, InfiniBand, T11 (Fibre Channel)
CEI-28G 28 Gbps 2011 InfiniBand EDR, 32GFC, SATA 3.2, SAS-4,100GBASE-KR4,
CR4, CAUI4
CEI-11G 11 Gbps 2008 InfiniBand QDR, 10GBASE-KR, 10GFC, 16GFC, SAS-3,
RapidIO v3
CEI-6G 6 Gbps 2004 4GFC, 8GFC, InfiniBand DDR, SATA 3.0, SAS-2, RapidIO
v2, HyperTransport 3.1
SxI5 3.125 Gbps 2002-3 Interlaken, FC 2G, InfiniBand SDR, XAUI, 10GBASE-KX4,
10GBASE-CX4, SATA 2.0, SAS-1, RapidIO v1
SPI4, SFI4 1.6 Gbps 2001-2 SPI-4.2, HyperTransport 1.03
SPI3, SFI3 0.800 Gbps 2000 (from PL3)
OIF’s CEI Work Has Been a Significant Industry Contributor
1/15/2019 OIF - 2019 10

11. 11 |
CEI-112G
MCM and XSR
Brian Holden
Kandou Bus
KANDOU
BUS

12. 12 |
CEI-112G MCM and XSR Application Spaces
❖ CEI-112G-MCM:
❖ 2.5 cm bump-to-bump
❖ CNRZ-5 modulation
❖ DC coupled path
❖ Silicon to silicon
❖ Clock Forwarded
❖ Fat-pipe (i.e. between logic chips)
❖ System FEC typically not present
❖ CEI-112G-XSR:
❖ 5 cm bump to bump
❖ PAM-4 modulation
❖ On-die AC coupling if needed
❖ Silicon to analog supported
❖ Thin-pipe (optics-friendly)
❖ Possible to make backwards compatible
❖ Typically relies on system FEC
12
3D Stack 2.5D Chip-to-Chiplet
Chip Optics
2.5D Chip-to-OE Chip to Nearby
Optics Engine
Chip Optics

13. 13 |
CEI-112-MCM Application – I/O Chiplets
Big, 70mm packages are routine
Non-interposer MCMs can easily
use 20 or more dies
• A trend in IC technology is to more
away from monolithic chips toward the
use of chiplets tied together on an MCM
• Chiplets allow the:
– Combination of many dies into large packages
– Improvement in yield and cost because of a
smaller central die(s) – a major factor
– Distribution of heat away from a single die
– Use of the best semiconductor process for each die
– Enabling of multi-vendor ecosystems
– I/O subsystem dies containing SerDes to be
placed around the perimeter, creating
smaller virtual packages
13

14. 14 |
CEI-112-XSR Application – On-package Optics
• Design shown is half-and-half
• Electrical out bottom of package
• Optics out top
• A trend is to mount multi-channel optics
engines on top of the package
• Optics can be short-reach
• Convert to long reach optics in front
panel modules
• XSR link must traverse two packages
• Density is a challenge
14

15. 15 |
CEI-112-XSR Application - Optical Engines
• Another emerging trend is to put multi-
channel optical engines in small
packages around the perimeter of the
package
• These optical links can have simple,
short-reach optics
• Longer-reach optics can be on the front
panel
Shown is a half-and-half design
with electrical out the bottom and
optical out of the top
Study of the impact of chiplets
KANDOU
BUS

16. 16 |
25.6 Tb/s Switch Chip analyzed
• 70 mm BGA package
analyzed
• 1 mm ball pitch
• 2.5 mm keep-out
• 256 Tx and 256 Rx pairs
• Used 6-deep design rule for
pairs
• Max Bump-Ball trace length
= ~ 31mm
16

17. 17 |
With 16 chiplets
• 236 Tx and 236 Rx pairs with
this pinout
– Can get to 256 with a variant of
this
• Reserved space for chiplet
power & CNRZ-5 traces
• Max Chiplet-Ball = ~ 14mm
• Max Bump-Chiplet = ~ 22mm
17

18. 18 |
Summary of Data
• The CEI-112G-LR loss budget is
strained
• This graphs the electrical package
trace length vs. the number of
chiplets
– Chiplet-Ball in blue
• Switch to chiplet for 0 chiplet case
– Bump-Chiplet in green
• Dramatic reduction in length and
thus loss when using chiplets
18
0
5
10
15
20
25
30
35
0 4 16
Package Trace Length
Chiplet-Ball Bump-Chiplet

19. 19 |
CEI-112-XSR Application - Optical Engines
• Another emerging trend is to put multi-
channel optical engines in small
packages around the perimeter of the
package
• These optical links can have simple,
short-reach optics
• Longer-reach optics can be on the front
panel
Shown is a half-and-half design
with electrical out the bottom and
optical out of the top
Opinions of Kandou Bus about CEI-112G-MCM
KANDOU
BUS

20. 20 |
CNRZ-5
–5 bits on 6 wires
– Dual symmetrical triads
–5 comparators
–Ideal for shorter
connections including
die-to-die interconnect
inside a package
–Has NRZ-shaped eyes
at the decision point

21. 21 |
Many MCM applications don’t require pair orientation
• Many applications just need massive bandwidth at low power
– Applications are often outside of the I/O subsystem
– Packet Processor to I/O Subsystem or Traffic Manager
– Processor to Processor
• 10 Tb/s between two dies is not an unusual requirement
• Chordal codes such as CNRZ-5 can save power
– These codes need more wires to be correlated, but that is easy on MCMs
– Natively needs less equalization than PAM-4
– Natively robust to reflections

22. 22 |
Reinventing the Bus

23. Click to edit Master title
style
Click to edit Master subtitle style
CEI-112G: Status Update on VSR, MR and
LR Channels
Nathan Tracy, OIF President and TE Connectivity Technologist

24. What is Required for Equipment with 112Gbps Electrical
Signaling?
24
Interoperable channel and SerDes specification for the following links:
✓ Die to Die links in a package with “fat pipe” capability, CEI-112G-
MCM (MultiChip Module)
✓ Die to Die links in a package or short channel with “pair to pair”
correlation, CEI-112G-XSR (Extra Short Reach)
✓ Chip to Module links, CEI-112G-VSR (Very Short Reach)
✓ Chip to Chip links between two PCBs, CEI-112G-MR (Medium
Reach)
✓ Chip to Chip links over a backplane, CEI-112G-LR (Long Reach)
All these projects are underway in the OIF

25. Focusing On VSR and LR Channels
25
Host IC
Module
Connector
AC
Coupling
Cap
Module
IC / Retimer
Very Short Reach Channel
(Chip to module)
Long Reach Channel
(Backplane)
Cabled Backplane
Orthogonal Backplane
What reaches are required?
Channel topologies, number of interconnects,
channel materials, impairments,
everything needs to be considered

26. VSR Channel, Test vs Model Results, Existing 50Gbps
Connector
Red Model (56G Connector)
Blue Test (56G Connector)
26
Note: Measured channel includes second set of vias to test point,
modeled channels do not include the second set of vias.

27. 100G Connector Improvements (in the same 15dB channel)
Improved 100Gbps
OSFP connector
Efforts were focused on insertion
loss and return loss optimizations
Red Model (56G Connector)
Blue Test (56G Connector)
Pink Model (100G Connector)
27
Note: Measured channel includes second set of vias to test point,
modeled channels do not include the second set of vias.

28. Top Row
Victim
Bot Row
Victim
Improved Connector in a 12dB Channel – Layer 15 Route-out
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
G Tx1+ Tx1- G Tx3+ Tx3- G Tx5+ Tx5- G Tx7+ Tx7- G SB SB SB SB G Rx8- Rx8+ G Rx6- Rx6+ G Rx4- Rx4+ G Rx2- Rx2+ G
G Tx2+ Tx2- G Tx4+ Tx4- G Tx6+ Tx6- G Tx8+ Tx8- G SB SB SB SB G Rx7- Rxy+ G Rx5- Rx5+ G Rx3- Rx3+ G Rx1- Rx1+ G
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
G Tx1+ Tx1- G Tx3+ Tx3- G Tx5+ Tx5- G Tx7+ Tx7- G SB SB SB SB G Rx8- Rx8+ G Rx6- Rx6+ G Rx4- Rx4+ G Rx2- Rx2+ G
G Tx2+ Tx2- G Tx4+ Tx4- G Tx6+ Tx6- G Tx8+ Tx8- G SB SB SB SB G Rx7- Rxy+ G Rx5- Rx5+ G Rx3- Rx3+ G Rx1- Rx1+ G
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Blue – Bot Row
Red – Top Row
Victim
FEXT Aggressor
NEXT Aggressor
Victim
FEXT Aggressor
NEXT Aggressor
28

29. VSR Channel Summary
29
• A draft baseline specification has been established and is evolving
• Channel losses are still being discussed
• Will optical modules and copper cables have the same host channel?
• Channels simulations and measurements continue to be contributed to the OIF
• Conventional PCB based channels and internal cable channels have been contributed
• Inputs have been received on multiple PCB materials and foil finishes
• Discussions continue on test fixtures (compliance board parameters)
• Good progress is being made to define a 112G VSR channel that enables next generation equipment

30. LR Channel Simulations Based On Updated Connectors
30
Multiple channels have been contributed by members for analysis including conventional
backplanes, direct plug orthogonal backplanes and cabled backplanes.
10 20 30 40 500 60
-90
-80
-70
-60
-50
-40
-30
-20
-10
-100
0
freq, GHz
Magnitude(dB)
Differential Insertion Loss TX/RX 8-Aggressor PowerSum Crosstalk
• 18” PCB Trace Total
• 9” Trace per board
• 6/6/6 trace geometry
• Meg7N Laminates
• HVLP Foils
• 140mil (3.56mm) Thick PCBs
• Victim pair uses layer 2 routing
• Victim pair: 15mil Stub w/ Shallow EON Technology
• Aggressor Pairs are thru board to bottom layer
• Next-Gen STRADA Whisper Connector Model
• Direct-Plug Orthogonal
• Stub resonance has been addressed
• Additional noise control features

31. LR Channel Simulations Based On Updated Connectors
31
Cabled Backplane
TX/RX 8-Aggressor PowerSum Crosstalk
• 12” PCB Trace Total
• 6” Trace per Board
• 6/6/6 Geometry
• Meg7N Laminates
• HVLP Foils
• 140mil (3.56mm) Thick Footprints
• Victim pair uses layer 2 routing
• Victim pair: 15mil stub w/ shallow EON technology
• Aggressor Pairs are thru board to bottom layer
• Next-Gen STRADA Whisper Connector Model
• Cabled header to R/A receptacle
• Additional noise control features
• Stub resonance addressed
• 1m Cable Length
• 30AWG TurboTwin twinax cable

32. LR Channel Summary
32
• A draft baseline specification has been established and is evolving
• Channel losses are targeted at 28dB
• Channels simulations and measurements continue to be contributed to the OIF
• Conventional PCB based channels, orthogonal channels and cable backplane channels have been
contributed and are being analyzed
• Inputs have been received on multiple PCB materials and foil finishes as well as copper cables
• Good progress is being made to define a 112G LR channel that enables next generation equipment

33. VSR, MR and LR Channel Summary
33
• VSR channels have been supplied and continue to be improved as the analysis of the channels is on-
going
• Other VSR parameters continue to be refined which affect channel allocations
• The MR project is just beginning but is expected to borrow heavily from VSR and LR
• LR channels have been contributed supporting a number of architectures and continue to be improved
• Excellent progress is being made to develop the 112Gbps Implementation Agreements for VSR, MR and
LR
• 112Gbps electrical signaling is not a trivial task and requires the combined inputs of the end users,
equipment developers/suppliers, component suppliers including silicon suppliers, optics suppliers,
connector suppliers, cable and PCB suppliers as well as test and measurement providers. Come join us
at the OIF.

34. EVERY CONNECTION COUNTS
© 2018 TE Connectivity Corporation. TE Connectivity, TE, TE connectivity (logo) and EVERY CONNECTION COUNTS are trademarks.

35. 35 |
PLL CEI-112G Equalization
Cathy Liu
OIF Board Member
Broadcom Inc.

36. 36 |
• PAM4 modulation scheme becomes dominant in OIF CEI-112 Gbps interface IA
• One SerDes core might not be able to cover multiple applications from XSR to LR
• For short reach applications, simpler and lower power equalizations are desired
112G Tx and Rx Reference Equalization
CEI-112G-LR Chip Chip
Backplane or Passive Copper Cable
CEI-112G-MR Chip Chip
Chip-to-Chip & Midplane Applications
CEI-112G-VSR Chip
Pluggable
Optics
Chip to Module
CEI-112G-XSR Chip Optics
Chip to Nearby Optics Engine
CEI-112G-MCM
3D Stack
CNRZ-5: up to 25mm package substrate
No equalization/FEC
Minimize power (pJ/bit)2.5D Chip-to-Chiplet
2.5D Chip-to-OE
PAM4: up to 50mm package substrate
6-10 dB at 14GHz
Lite FEC, Rx CTLE
PAM4: 12-16 dB at 14GHz
FEC to relax BER to 1e-6
Multi-tap Tx FIR and Rx CTLE + multi-tap FFE or DFE
PAM4: 20dB at 14GHz
FEC to relax BER to 1e-5
Multi-tap Tx FIR and Rx CTLE + multi-tap FFE or DFE
PAM4: 28-30dB at 14GHz
FEC to relax BER to 1e-4
Multi-tap Tx FIR and Rx CTLE + multi-tap FFE or DFE

37. 37 |
• 11 channels + packages under consideration for 112 Gb/s support
112Gbps Trends – Channels
XSR
VSR
MR
LR

38. 38 |
• 28~30dB IL target at 28GHz is not “long reach” anymore for traditional backplane or Cu
cable
– Rule of Thumb of 0.1dB/inch/GHz channel loss ->28dB IL for a 10” PCB trace
– 3~5dB IL for a 30mm package
• Emerging technologies to shorten the “long reach”
– Chiplets
– Fly over cables
– Retimer/Repeater
How long is long for 112Gbps?
Flyover cables
Chiplets

39. 39 |
Equalization Block Diagram
Precoder FFE
Driver
+ term.
DFE
Slicer
CDR
Inverse
precoder
CTLE VGA FFE
Term.
ACC
To FEC decoder
From FEC encoder
Package
incl.
crosstalk
Equalizer parameters continuously adapted
Package
incl.
crosstalk
Channel incl. crosstalk Far-end
aggressor
Near-end
aggressor
External noise
Aggressor
Transmitter
Receiver
The reference receiver equalization is defined for both analog solution
and DSP solution (if ADC is implemented at the analog front end)

40. 40 |
SNR Required for Target BER – CEI-112G
For probability of error propagation a = 0.75
Test case SNR req’d, dB
Burst only 21.16
Burst + precode 18.85
Burst + CI(2)+ precode 18.60
4:1 bit mux. 22.34
4:1+precode 19.00
4:1+CI(2) 20.23
4:1+CI(2)+precode 18.89
1e−15 equivalent (OIF CEI-112G-LR)
CEI SNR target

41. 41 |
112G Gbps Trends - Salz SNR (Ideal Case)
Decision-point SNR for ideal DFE (a.k.a. Salz SNR) [4]
𝑆𝑁𝑅 𝑀𝑀𝑆𝐸−𝐷𝐹𝐸 =
1
2𝜋
න
−𝜋
𝜋
10log10 𝐹(𝜃) + 1 𝑑𝜃
𝐹 𝜃 =
1
𝑇
෍
𝑚
𝑆
𝜃 + 2𝜋𝑚
2𝜋𝑇
2
−𝜋 < 𝜃 ≤ 𝜋
…where 𝑭(𝜽) is the folded SNR at frequency 𝜽.
…and 𝑺(𝒇) is the frequency-dependent ratio of
signal power to noise power.
Parameter Value
Driver differential output amplitude (peak), V 0.4
Driver rise/fall times (20-80%), UI 1/3
Uncorrelated jitter, mUI RMS 23
Transmitter signal-to-noise ratio, dB 32.5
Far-end aggressor output amplitude (peak), V 0.4
Near-end aggressor output amplitude (peak), V 0.6
External noise spectral density (1-sided), V2/Hz 1.6e−8
Modeled impairments

42. 42 |
• Salz SNR can be computed very quickly
which is useful for large data set
• However, it is an upper bound on
performance and SNR degradation is
expected for the limitations of practical
receivers
– Finite-length filters
– Quantization effects
– Circuit noise and distortion
– Receiver jitter
– Impairments not readily included in a Salz SNR
analysis (e.g., even-odd jitter)
• For short reach applications, simpler and
lower power equalizations are desired
Salz SNR vs. Practical Equalization
SNR targets for different BERs
1e-4 1e-5 1e-6
XSR
VSR
MR
LR

43. 43 |
Practical Equalization
• Terminations:
– Design extracted
• Tx:
– 4-tap FIR defined in 802.3cd [7]
• RX:
– CTLE defined in CEI-112G-VSR [1]
– Finite FFE taps with LSB = 0.02
– 1-tap DFE with step size 1.2mV
• Trade-off for different applications:
– XSR – CTLE only
– VSR – CTLE+5-tap FFE
– MR – CTLE+10-tap FFE
– LR – CTLE + 20-tap FFE not sufficient, need 1-
tap DFE followed1e-4 1e-5 1e-6
VSR
MR
LR
XSR
4-tap
TX FIR
Pkg.
Term.
Pkg.
Term.
n-tap
RX FFEchannel
CTLE
DFE

45. 45
112-Gbps Electrical Interfaces: An OIF update on CEI-112G
Meas

46. 46
• Not making compliance measurements at this stage
• Some silicon vendors are characterizing test chips and proprietary designs
• Likely see some compliance testing in the next year
• Very tight margins in link budget will challenge measurements
• Tx output measurements use 43 GHz BT4 filter to represent package – significant reduction from
56G (used 40 GHz)
• Concerns with reference receiver used for Tx measurements and Rx stress calibration -
repeatability

47. 47
• Qualitative prediction of link integrity by measuring signals were we can access
them
• Near end to assess Tx performance
• Far end to assess Rx capability
• Indirect results when we add signal processing, such as equalization
Purpose of measurements in the physical link
Transmitter Receiver
Channel
De-
Emphasis
Equalizer

48. 48
• Problem – measurement instrument may “see” artifacts in the link signal that will
not impact the receiver.
• (e.g. higher frequency components beyond receiver bandwidth)
• Solution – add a “Reference Receiver” to constrain measurement to signals as
seen by actual receiver
• Removes out of band noise, DC from measurement
• Accuracy required for measurement repeatability
Instrument ‘sees’ more than receiver
Transmitter Receiver
Measurement
Instrument
Reference
Receiver

49. 49
• Accurate measurement of what the DUT is seeing, results when reference
receiver uses this approximation:
Where HDUT par.(X) is the actual receiver response to the parameter being measured
• E.g. receiver’s BW emulated by LPF in reference receiver
The Reference Receiver
HDUT par.(x) = HRef.Rec.(x)
Transmitter Receiver
Reference
Receiver
Measurement
Instrument

50. 50
• Adding a tunable filter / gain stage with instructions “Tune for the best response”
-OK for actual receivers, but not in front of instruments when repeatability is desired
Reference
Receiver
Measurement
Instrument
Filter Pole Freq.: (specified fixed value)
Filter roll-off: (specified slope value)
Amplifier gain: (specified fixed value)
Reference
Receiver
Measurement
Instrument
Filter Pole Freq.: (tune for best response)
Filter roll-off: (tune for best response)
Amplifier gain: (tune for best response)
Note: CTLE tuning frequency not adjusted in reference receiver – used as example to illustrate effects of FFE
and DFE
Example – self optimizing equalizer gives 50% UI EW in one case, with same Tx and channel, 58% in another.
Fine for a real receiver, but not a measurement instrument !

51. 51
• Self optimizing equalizers, such as Decision Feedback Equalization (DFE),
inherently never exactly replicate optimized state in the reference receiver
• Tap resolution, gain, and even data pattern sample points yield different optimal converged states
• Resulting in non-repeatable measurement
• Significant differences in receivers using high performance equalization schemes
• Advanced equalization topology is a competitive differentiator between SerDes designs – not
shared with the Standard working group
• Standard must be generic – adopting transfer function from particular receiver topology would
direct designers into specific implementation
• Typical response from ‘generic’ reference receiver equalizer often has more remaining eye
closure than any real DUT design
How close does RR emulate actual receiver?

52. 52
• Much discussion over reference receiver - # of taps in FFE and DFE, but topology
is firm: CTLE + FFE + DFE
• All are self optimizing
• CTLE – select LF gain from table or range
• FFE + DFE - # of taps, range, and step size specified
• Concern with recent example – TDECQ measurement (output Tx output in 400G
802.3cd standard project)
• Significant non-repeatability between instrument vendors and poor correlation with BER results
required several draft iterations. Large cause was found in single stage of self optimizing eq.

53. 53
• It theory optimizing equalizers could be used in reference receivers and give
repeatable measurements when these conditions are met:
• Order of placement of equalizer elements (CTLE first, followed by DFE or FFE, followed by ___)
• Linear systems should allow interchanging or, but this ignores action of noise on individual equalizer elements
• Tap configuration
• Cursor placement
• Lange limits
• Increment step size
• Optimization stop criteria
• Will actual implementations follow theory and be repeatable?

54. 54
• Need to formalize criteria for repeatability requirements listed in Standards
documents
• In addition to obtaining repeatability, work will be required to speed measurement
acquisition and processing to a reasonable level
• (Measuring true EW-6*EH-6 product for optimization is much too slow!)
• Instrument vendors need to implement reference receiver and test with real silicon
– sooner than later !

56. Questions?
1/15/2019 OIF - 2019 56

57. 112-Gbps Electrical Interfaces:
An OIF Update on CEI-112G