Wireless base stations, like most network nodes, have traditionally been vertically integrated boxes. FlexRAN is a reference architecture developed by Intel to implement software based radio stations which can sit on any part of the wireless networks from edge to core.

1. Lei Xu PhD (lei.l.xu@intel.com)
Strategic Business Development
Intel PSG Wireless BU

2. equires Agility, Scalability and Intelligence Across Network, Cloud &
Higher speeds, greater capacity, and lower latency
Billions of connected devices and things
Emerging standards and proliferation of
network deployment  flexible solutions
Cellular Comms
2
G
Data and the
app revolution
3
G
Faster data &
More Users
4
G
5
GMassive
Machine-
To-Machine
(mMTM)
Enhanced
Mobile
Broadband
(eMBB)
Ultra-
Reliable
and Low
Latency
(URLCC)

3. SCALABLE & FLEXIBLE TECHNOLOGIE
Smart
Devices
Wireless
Technolog
y
Access &
Edge
Network
Core
Network Cloud
vEPC / 5GC
NFVI
Security
FlexRAN
MEC
Back Haul
Radio
Front Haul
Baseband
Intel’s scale meets 5G scope

4. Baseband
Transport
Control
Sync
BBU
Virtualized
BBU Pool
Virtualized RAN
RAN
3GPP 5G NR Rel.15 New Radio
Architecture
Intel FlexRAN Architecture
Virtualization
Smart Antenna
Radio
RRU
2
FH3
1
Baseband
Transport
Control
Sync
Baseband
Transport
Control
Sync
Baseband
Transport
Control
Sync
Smart Antenna
Radio
RRU
2
Smart Antenna
Radio
RRU
2
Smart Antenna
Radio
RRU
2
FH3
1

5. 9
FlexRAN Concept
NFV Concept
MEC
Virtualization layer:
KVM
VF (networking, QAT)
Hardware:
Server, Storage, Networking
HW accelerator
Guest:
Pooling Framework
FastPath
Pooling Framework
RAN: 5G
RAN:
LTE
vEPC
VNF
Infrastructure
Intel® Xeon +FPGA GPP Platform Enabling Digital Radio,
IOT Connectivity, Services, Applications

6. FlexRAN (Intel vRAN Reference Implementation)
Overview
• Software Reference Implementation of BBU software (L1 – L3).
• Targeting 4G and 5G (NR) networks.
• Runs on Centralized or Distributed Intel Silicon Platforms.
• Intel Provides L1. Eco system partners provide L2 & L3.
What is
FlexRAN
• Demonstrate Baseband functionality on Intel Silicon.
• Help eco system optimize L1 on Intel Silicon.
• Support the eco-system in accelerating the development of
commercial solutions.
FlexRAN
Objective
• Intel licenses the FlexRAN L1.
• Only allowed to run it on Intel silicon.
• Customer use it as an SDK or integrate modules into their code.
Engagement
Model
• Outdoor and Indoor (Rural, Urban, Enterprises, Venues,
Stadiums, Malls, Public Spaces etc.)
• Scales from single carrier to multiple carriers
• Centralized, Distributed and Integrated network architectures
FlexRAN
Segments
VNFs
Simple & Cost Effective Approach To Deploy RAN On General Purpose Processing
TA
FlexRAN is a 4G/5G reference
implementation from Intel that is
available today for active
customer engagements under a
free Intel software license
agreement.

7. FlexRAN Hardware
(COTS Implementation – Example)
11
Dual Intel Processor Blades
Layer 1 processing
Layer 2 /3 processing
MEC
Intel Vista Creek Card
Intel FPGA FEC Acceleration
Turbo/LDPC/Polar
Intel FPGA Fronthaul Acceleration
RoE / eCPRI / CPRI
(i)FFT & CP+/-
PRACH
*HW shown are example only.
Ultra Dense Scalable and Flexible
RAN form factor design

8. FlexRAN Solution Ingredients
Platform (IA + FPGA)
Xeon-D: Broadwell-DE to Skylake-D & next gen;
Atom: Denverton-NS & next gen
Intel FPGA: Arria10 to Stratix10 & next gen
Virtualization
L2-L3 Commercial Software
(Vendors)
L1 Reference Software
(4G initially, with roadmap to 5G)
4G LTE + 4G Scale out
and 5G:
Intel working with Eco
system partners (e.g. TIP,
xRAN) to enable vendors
and solutions providers
with FlexRAN Software.
Some ecosystem vendors
include:
Altiostar, Mavenir, ASTRI.
RRU vendors such as
CommScope etc.
Ecosystem
openRAN
https://telecominfraproject.com/proj
ect/access-projects/openran/

9. SDK Modules – DRAFT
13

10. 15
FlexRAN Common Architecture (4G/5G)
MEC
Enc
Codec
Dec
Codec
IQ
CPRI for compatible of existing 4G RRU
Frontend target embedded in RRU for 5G
FrontEnd
Processing

11. IA+FPGA Function Mapping
17
DMRS REF
Gen
PDCCH
PUCCH
DL Sync /
BCH
CRC Gen and
Segmentation
LDPC
Encoder
Rate
Matching
Scrambler
Modulation
Mapper
Layer
Mapper
Precoder
Res Elem
Mapper
IFFT
Add CP
RF
FEC FPGA
Time Domain IQ Samples over QSFP
using proprietary protocol
BBU Cores
L1/L2/L3
Front Haul FPGA
PCIE
FFT
CP
Removal
PRACH
FrontEnd
Channel
Estimation
MMSE and
Equalizer
TA and PN
Comp
HARQ
Combining
Rate De-
Matching
LDPC
Decoder
CRC Check
and TB Gen
Demodulati
on
Descramble
r
PCIEETH
Intel Server(Xeon + FPGA)
Same function mapping as mmWave
Just different dimension.May change according
different RF vendor.

12. 18
L2, L3 Function Partition
• Real Time and none Real time split
• Centralized Part and distributed Part Split
• Base Station Level a Cell Level Split
• 4G/5G common Part and 4G/5G dedicated Part Split
• Best way to support standalone and none standalone
Split
eNB
PDCP
RLC
5G Node
PDCP
RLC
MAC
RLC
MAC
PDCP
SWI/SPL
eNB
PDCP
RLC
RRC
SRB
5G Node
DRB
5G RRC
PDCP
RLC
MAC
S1-U S1-U
S1-C