MIPI DevCon Seoul 2018: Next Generation Verification Process for Automotive and Mobile Designs with CSI-2 Interface
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With MIPI CSI-2℠ integrated in many complex systems, this presentation from Thierry Berdah and Yafit Snir, both of Cadence Design Systems, Inc., focuses on methodology for a full verification flow, from the IP level to the SOC level.
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MIPI DevCon Seoul 2018: Next Generation Verification Process for Automotive and Mobile Designs with CSI-2 Interface
- 1. Thierry Berdah, Yafit Snir Cadence Design Systems Next Generation Verification Process for Automotive and Mobile Designs with MIPI CSI-2SM Interface
- 2. © 2018 MIPI Alliance, Inc. 2 • Typical Verification Challenges of MIPI CSI-2SM designs • IP, Sub System and System Level Verification • Simulation verification methodology for MIPI CSI-2SM spec compliancy • Acceleration Methodology Overview • Concepts for building MIPI CSI-2SM acceleration-ready environment • MIPI CSI-2SM IP Level: From simulation to acceleration Cadence Design Systems Agenda
- 3. © 2018 MIPI Alliance, Inc. 3 • Widely adopted serial high-speed protocols • Implemented in complex systems, for a variety of applications in different markets: – Mobile – Video Games – Automotive – Multimedia – Virtual reality, augmented reality and others Cadence Design Systems MIPI CSI-2℠ adoption
- 4. © 2018 MIPI Alliance, Inc. 4 Cadence Design Systems MIPI Interfaces usage example in Complex SOCs Customer’s Application Specific Components SoC Interconnect Arm CPU Subsystem 3D Graphics Core DSP A/V High speed, wired interface peripherals LPDDR3 PHY Storage & Memory SAS SD SATA MIPI UFS Other Memory Low-speed peripheral subsystem MIPI high speed peripheral interfaces, and other. MIPI SoundWire® MIPI LLI℠ MIPI UniPro℠ MIPI D-PHY℠ MIPI M-PHY® I2C JTAG MIPI CSI-2SM MIPI DSISM MIPI DigRF℠ Application Accelerators … AES … A15 L2 cache USB3.0 3.0 PHY 2.0 PHY PCIe Gen 2,3 PHY Ether- net PHY A15 A7 L2 cache A7 Cache Coherent Fabric Software Further complicated by hardware/ software interactions
- 5. © 2018 MIPI Alliance, Inc. 5 Cadence Design Systems MIPI CSI-2SM Verification Challenges • Reach system verification coverage goals prior to code freeze • MIPI CSI-2SM spec compliancy based on design and system configuration • Time to market: Requires parallel development of hardware and software design, early in development cycle • Validating software and hardware integration • Create and validate real world scenarios in a pre-silicon environment
- 6. © 2018 MIPI Alliance, Inc. 6 Subsystem System Sub Sys Sub Sys IP IP IP SOC IP Verification VIP Accelerated VIP Basic MIPI CSI-2SM Testsuite Simulation Acceleration Full Verification Testsuite Cadence Design Systems Design Verification Flow
- 7. © 2018 MIPI Alliance, Inc. 7 Integrate VIP(s) Create Tests Compliance Debug DUT issues Coverage closure Basic Testsuite IP IP IP IP Verification Full Testsuite VIPs VIP’s Coverage Model vPlan VIP’s checkers Cadence Design Systems IP-Level Verification
- 8. © 2018 MIPI Alliance, Inc. 8 Subsystem Sub Sys Sub Sys System SOC Integrate VIP(s) or AVIP(s) Create Tests Debug DUT Issues CoverageTestsuite Protocol and system debug tools VIP Coverage AVIPs VIPs AVIPs VIPs Cadence Design Systems Emulation Coverage Sub-System/SoC Level Verification
- 9. © 2018 MIPI Alliance, Inc. 9 Cadence Design Systems Verification methodology for Spec compliancy • Spec verification is based on two aspects: 1. MIPI CSI-2SM I/F spec compliance • Protocol checking based on MIPI CSI-2SM spec • Coverage aligned to the design configuration • Complete Testsuite to cover MIPI CSI-2SM DUT 2. System behavioral correctness • Integrity checking based on system definition CSI-2SM VIP Agent Driver (BFM) Sequencer (sequence driver) Monitor DUT I/F checking coverage UVM Config
- 10. © 2018 MIPI Alliance, Inc. 10 Integrity checking (Scoreboard) Protocol checking Compliance Testsuite Cadence Design Systems Verification methodology for Spec compliancy • User needs full visibility into and controllability over VIP on Configuration, traffic injection, protocol checking and functional coverage Callback Configuration VIP Testbench (User Layer) Transaction
- 11. © 2018 MIPI Alliance, Inc. 11 Cadence Design Systems Full Verification 3. Verification Plan • Protocol-meaningful verification objectives • Linked to coverage database • Filtered to match DUT specific configuration • Able to integrate with simulation tools • Easy to understand correlation of coverage results to protocol specification 2. VIP Functional Coverage • Native verification language database • Reachable and tested • Filtered per user configuration • Complete coverage of your configuration 1. Test Suite • Ready to use, spec driven tests • Optimized combination of Directed and Constrained-random sequences • Reaching 100% of the Verification Plan • Filtered per DUT configuration • Early & Fast verification Verification methodology for Spec compliancy
- 12. © 2018 MIPI Alliance, Inc. 12 Cadence Design Systems VIP User feeds the DUT’s specific Configuration ConfigurationFile SpecificationOfMyArchitecture BFM Monitor UI DUT TestSuite Native Coverage Transaction Tests Pipe Tests Link Layer Tests Physical Layer Tests Configuration Tests DUT specific info is created VIP configured To DUT vPlan, Coverage and TestSuite based on DUT config Verification methodology for Spec compliancy
- 13. © 2018 MIPI Alliance, Inc. 13 Cadence Design Systems How to create the MIPI CSI-2SM Verification Plan?
- 14. © 2018 MIPI Alliance, Inc. 14 Cadence Design Systems TEXT Gradient shapes Subsystem System SubSys SubSys IP IP IP SOC IP Verification VIP Accelerated VIP Simulation Acceleration VIP to AVIP Migration Development Flow and VIP Tools Map
- 15. © 2018 MIPI Alliance, Inc. 15 Cadence Design Systems Why Acceleration ? Customer’s Application Specific Components SoC Interconnect Arm CPU Subsystem 3D Graphics Core DSP A/V High speed, wired interface peripherals LPDDR3 PHY Storage & Memory SAS SD SATA MIPI UFS Other Memory Low-speed peripheral subsystem MIPI high speed peripheral interfaces, and other. MIPI SoundWire ® MIPI LLI℠ MIPI UniPro℠ MIPI D-PHY℠ MIPI M-PHY® I2C JTAG MIPI CSI-2SM MIPI DSISM MIPI DigRF℠ Application Accelerators … AES … A15 L2 cache USB3.0 3.0 PHY 2.0 PHY PCIe Gen 2,3 PHY Ether- net PHY A15 A7 L2 cache A7 Cache Coherent Fabric Software Complex SoCs, comprised of tens of millions of logic gates, will impede software simulators, even when running on the fastest servers.
- 16. © 2018 MIPI Alliance, Inc. 16 • Emulator assisted verification – Simulation Acceleration – Virtual Emulation – In-Circuit Emulation • FPGA Prototyping Cadence Design Systems Overview of hardware assisted verification
- 17. © 2018 MIPI Alliance, Inc. 17 Cadence Design Systems Simulation Acceleration & Accelerated VIP Transaction Based Acceleration Signal Based Acceleration • Bit-by-bit signal level exchange between testbench and DUT • Performance bottleneck can be the communication channel or testbench time Transaction Based Acceleration • Reduces communication channel overhead from signal based to transaction based • Leverages fast hardware for DUT execution Workstation Emulator Communication Channel Testbench Design Under Test Testbench Design Under Test TBA I/F TBA I/F B F M Palladium Z1Workstation Accelerated VIP (AVIP) Drv Mon Seq
- 18. © 2018 MIPI Alliance, Inc. 18 Cadence Design Systems Virtual emulation & Virtual Device Signal Based Acceleration • Bit-by-bit signal level exchange between testbench and DUT • Performance bottleneck can be the communication channel or testbench time Virtual emulation • Enables testing the design with real- world traffic • Leverages fast hardware for DUT execution Workstation Emulator Communication Channel Design Under Test Virtual Device Model Design Under Test TBA I/F TBA I/F P R O X Y B F M Palladium Z1Workstation Virtual Device
- 19. © 2018 MIPI Alliance, Inc. 19 Cadence Design Systems WorkstationEmulator SOC Design MIPI CSI-2SM Host Controller Enables visualization of the HW/SW operation of the video/image processing subsystem in real time Frame buffer SW stack/drivers GPU Image processor BFM SW Proxy MIPI CSI-2SM AVIP MIPI CSI-2SM Virtual Device Model Model Logic Image filesMIPI CSI-2SM Virtual Device MIPI CSI-2SM Virtual Device
- 20. © 2018 MIPI Alliance, Inc. 20 Cadence Design Systems Emulator SOC Design MIPI CSI-2SM Host Controller Enables connection of real sensors to emulated SOC designs for live video and closed loop testing Frame buffer SW stack/drivers GPU Image processor MIPI CSI-2SM Real Sensor MIPI CSI-2SM Rate Adapter MIPI CSI-2SM Emulation/Prototyping with real sensor
- 21. © 2018 MIPI Alliance, Inc. 21 Cadence Design Systems Concepts for building an acceleration-ready environment • Use consistent API for VIPs/AVIPs • Use Dual-Top structure for the verification environment – The Hardware top will include the DUT, Interfaces, clocks generation, etc. – The software top will include the SW Verification Environment. • Use event based delays instead of cycle/time based delays whenever possible. • Pre define simulation and acceleration subset of shared sequences Emulator Simulator Shared AVIP/VIP Interface User API Shared AVIP/VIP API DUT VIP Core Simulator Shared AVIP/VIP Interface User API DUT Accelerated VIP Core Consistent SW API Consistent HW API Shared AVIP/VIP API
- 22. © 2018 MIPI Alliance, Inc. 22 Cadence Design Systems MIPI CSI-2SM IP Level: From simulation to acceleration Simulation stage MIPI CSI- 2SM RX DIP APB IF PPI IF APB VIP Active Agent MIPI CSI-2SM VIP Passive Agent APB VIP Passive Agent MIPI CSI-2SM I/F APB I/F Clocks gen Pixel Custom UVC VIP Hardware Top (Simulator) User Sequences User Sequences User Sequences Software Top (Simulator) MIPI CSI-2SM AVIP/VIP Shared API APB AVIP/VIP Shared API VIP CSI2 Passive VIP APB Passive VIP MIPI CSI-2SM AVIP VIP I/F APB AVIP VIP I/F MIPI CSI-2SM VIP Active Agent Core APB VIP Active Agent Core
- 23. © 2018 MIPI Alliance, Inc. 23 Cadence Design Systems MIPI CSI-2SM IP Level: From simulation to acceleration Step #1 Disabling passive agents used at IP level stage MIPI CSI- 2SM RX DIP APB IF PPI IF APB VIP Active Agent Clocks gen Pixel Custom UVC VIP Hardware Top (Simulator) User Sequences User Sequences User Sequences Software Top (Simulator) MIPI CSI-2SM AVIP/VIP Shared API APB AVIP/VIP Shared API VIP MIPI CSI-2SM AVIP VIP I/F APB AVIP VIP I/F MIPI CSI-2SM VIP Active Agent Core APB VIP Active Agent Core
- 24. © 2018 MIPI Alliance, Inc. 24 Cadence Design Systems MIPI CSI- 2SM RX DIP APB IF PPI IF APB VIP Active Agent Clocks gen Pixel Custom UVC Accelerated VIP Hardware Top (Simulator) User Sequences User Sequences User Sequences Software Top (Simulator) CSI2 AVIP/VIP Shared API APB AVIP/VIP Shared APIAccelerated VIP MIPI CSI-2SM AVIP VIP I/F APB AVIP VIP I/F MIPI CSI-2SM Accelerated VIP Active Agent Core APB Accelerated VIP Active Agent Core MIPI CSI-2SM IP Level: From simulation to acceleration Step #2 Migrating to Accelerated VIPs
- 25. © 2018 MIPI Alliance, Inc. 25 Cadence Design Systems MIPI CSI- 2SM RX DIP APB IF PPI IF APB VIP Active Agent Clocks gen Pixel Custom UVC Accelerated VIP Hardware Top (Simulator) User Sequences User Sequences User Sequences Software Top (Simulator) CSI2 AVIP/VIP Shared API APB AVIP/VIP Shared APIAccelerated VIP MIPI CSI-2SM AVIP VIP I/F APB AVIP VIP I/F MIPI CSI-2SM Accelerated VIP Active Agent Core APB Accelerated VIP Active Agent Core MIPI CSI-2SM IP Level: From simulation to acceleration Step #3 Choosing the subset of sequences required for acceleration Identifying AVIP/VIP Shared sequences
- 26. © 2018 MIPI Alliance, Inc. 26 Cadence Design Systems MIPI CSI- 2SM RX DIP APB IF PPI IF APB VIP Active Agent Clocks gen Pixel Custom UVC Accelerated VIP Hardware Top (Simulator) User Sequences User Sequences User Sequences Software Top (Simulator) CSI2 AVIP/VIP Shared API APB AVIP/VIP Shared APIAccelerated VIP MIPI CSI-2SM AVIP VIP I/F APB AVIP VIP I/F MIPI CSI-2SM Accelerated VIP Active Agent Core APB Accelerated VIP Active Agent Core MIPI CSI-2SM IP Level: From simulation to acceleration Step #4 Migrating to acceleration flow Design run time Accelerated !
- 27. © 2018 MIPI Alliance, Inc. 27 Summary: Advantages of using acceleration • Enables orders-of-magnitude gains in throughput over Simulation • Enables re using selected parts of your simulation verification environment • Enables advanced technologies with virtual emulation, like: – Hybrid operation for optimal partition of the design between HW and SW to achieve maximum speedup – Connection to Virtual Devices, Virtual machines, etc. • Enables OS-level benchmarks and driver bring-up Cadence Design Systems
- 28. © 2018 MIPI Alliance, Inc. 28 • MIPI Camera WG URL: https://members.mipi.org/wg/camera-wg/dashboard • MIPI CSI-2SM Spec URL: https://members.mipi.org/wg/camera- wg/document/75006 • Cadence Verification IP URL: https://ip.cadence.com/ipportfolio/verification- ip/simulation-vip • Cadence Accelerated VIP URL: https://ip.cadence.com/ipportfolio/verification- ip/accelerated-vip Cadence Design Systems ADDITIONAL RESOURCES