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Bài 1: Viết chương trình điều khiển 8 LED nháy tròn. Nguyên lý hoạt động của mạch - Mạch có chức năng là điều khiển 8 LED nháy dịch từ LED1 đến LED8 và được sắp xếp thành vòng tròn, chương trình chạy khi clock=1 Code VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity bai1 is Port (clk: in STD_LOGIC; P: out STD_LOGIC_VECTOR (7 downto 0)); end bai1; architecture Behavioral of bai1 is Signal Q: integer := 0; begin process(clk) begin If rising_edge(clk) then if Q = 8 then Q <= 0; else Q <= Q+1; end if; end if; end process;
process(Q) begin case Q is when 0 => P <= "00000000"; when 1 => P <= "10000000"; when 2 => P <= "01000000"; when 3 => P <= "00100000"; when 4 => P <= "00010000"; when 5 => P <= "00001000"; when 6 => P <= "00000100"; when 7 => P <= "00000010"; when 8 => P <= "00000001"; when others => P <= "00000000"; end case; end process; end Behavioral; Test bench library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is end test; architecture Behavioral of test is Component Bai1 is Port ( clk : in STD_LOGIC; P : out STD_LOGIC_VECTOR (7 downto 0) );
end Component; Signal clk: STD_LOGIC := '0'; Signal P: STD_LOGIC_VECTOR(7 downto 0); begin VVT: Bai1 Port map( CLK => CLK, P => P ); CLK <= not CLK after 10 ns; end Behavioral; Bài 2: Viết chương trình mô tả bộ đếm lùi Mod 9 (có CLK, CLR, Pause) Nguyên lí hoạt động của mạch - Mạch đếm lùi mode 9 có clock, clear và pause. Mạch thực hiện đếm từ 8 về 0,chương trình hoạt động khi clock=1 , khi clear=1 chương trình trở về trạng thái reset là bằng “0000” rồi tiếp tục đếm từ 8 về 0 Code VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bai2 is port (CLK: in std_logic; CLR: in std_logic; PAUSE: in std_logic; count: out std_logic_vector(3 downto 0));
end bai2; architecture Behavioral of bai2 is Signal counter: std_logic_vector(3 downto 0) := "1000"; begin process (CLK, CLR, PAUSE) begin if CLR = '1' then counter <= "0000"; end if; if rising_edge(CLK) and CLR = '0' and PAUSE = '0' then if (counter = "0000") then counter <= "1000"; else counter <= counter - 1; end if; end if; end process; count <= counter; end Behavioral; Test bench library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is end test;
architecture Behavioral of test is component bai2 is port ( CLK : in std_logic; CLR : in std_logic; PAUSE : in std_logic; count : out std_logic_vector(3 downto 0)); end component; signal CLK,CLR,PAUSE: std_logic := '0'; signal count: std_logic_vector(3 downto 0); begin uut: bai2 port map( CLK => CLK, CLR => CLR, PAUSE => PAUSE, count => count ); CLK <= not CLK after 10ns ; pausess: process begin PAUSE <= '0'; wait for 500ns; PAUSE <= '1'; wait for 80ns; end process; clearr: process begin CLR <= '0'; wait for 700ns; CLR <= '1'; wait for 10ns;
end process; end Behavioral; Bài 3 : Viết chương trình mô tả bộ đếm lùi BCD từ 59 đến 00 - hiển thị trên LED 7 đoạn Anode chung (CLK, CLR) Nguyên lí của mạch - Bộ đếm lùi BCD mod 60 đếm lùi từ 59 về 00 và hiển thị trên LED 7 đoạn Anode chung có xung clock và clear. Khởi tạo giá trị ban đầu 2 biến hàng chục và hàng đơn vị bằng 59 và cho chạy dần về 00. Mạch bắt đầu đếm khi clock = 1, khi clear = 1 mạch trở về trạng thái reset là “0000” rồi bắt đầu đếm lại từ 59 về 00 Code VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Bai3 is Port (CLK: in STD_LOGIC; CLR: in STD_LOGIC; Led1: out STD_LOGIC_VECTOR (6 downto 0); Led2: out STD_LOGIC_VECTOR (6 downto 0); OutChuc: out STD_LOGIC_VECTOR(3 downto 0); OutDvi: Out STD_LOGIC_VECTOR(3 downto 0)); end Bai3;
architecture Behavioral of Bai3 is Signal Chuc: STD_LOGIC_VECTOR(3 downto 0) := "0101"; Signal Dvi: STD_LOGIC_VECTOR(3 downto 0) := "1001"; begin process (CLK, CLR) begin if CLR = '1' then Chuc <= "0000"; Dvi <= "0000"; elsif CLK'event and CLK = '1' then if (Dvi = "0000") then Dvi <= "1001"; if Chuc = "0000" then Chuc <= "0101"; else Chuc <= Chuc - 1; end if; else Dvi <= Dvi - 1; end if; end if; end process; OutChuc <= Chuc; OutDvi <= Dvi; --Hien thi led process(Dvi) begin case Dvi is when x"9" => Led1 <= "0010000"; when x"8" => Led1 <= "0000000"; when x"7" => Led1 <= "1111000"; when x"6" => Led1 <= "0000010"; when x"5" => Led1 <= "0010010";
when x"4" => Led1 <= "0011001"; when x"3" => Led1 <= "0110000"; when x"2" => Led1 <= "0100100"; when x"1" => Led1 <= "1111001"; when others => null; end case; end process; process(Chuc) begin case Chuc is when x"5" => Led2 <= "0010010"; when x"4" => Led2 <= "0011001"; when x"3" => Led2 <= "0110000"; when x"2" => Led2 <= "0100100"; when x"1" => Led2 <= "1111001"; when others => null; end case; end process; end Behavioral; Test bench library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bai3comp is end bai3comp; architecture Behavioral of bai3comp is
component bai3code is Port ( CLK : in STD_LOGIC; CLR : in STD_LOGIC; Led1 : out STD_LOGIC_VECTOR (6 downto 0); Led2 : out STD_LOGIC_VECTOR (6 downto 0); OutChuc: out STD_LOGIC_VECTOR(3 downto 0); OutDvi : out STD_LOGIC_VECTOR(3 downto 0)); end component; Signal CLK, CLR: STD_LOGIC := '0'; Signal Led1, Led2: STD_LOGIC_VECTOR(6 downto 0); Signal OutChuc: STD_LOGIC_VECTOR(3 downto 0); Signal OutDvi: STD_LOGIC_VECTOR(3 downto 0); begin MDH: bai3code port map( CLK => CLK, CLR => CLR, Led1 => Led1, Led2 => Led2, OutChuc => OutChuc, OutDvi => OutDvi ); CLK <= not CLK after 10ns; clear: process begin CLR <= '0'; wait for 500ns; CLR <= '1'; wait for 80ns; end process; end Behavioral;
Bài 4: Viết chương trình mô tả bộ phân kênh 1:16 (Enable hoạt động ở mức thấp) Nguyên lý hoạt động Bộ phân kênh 1 đầu vào 16 đầu ra, sử dụng Sel 4 bit thay đổi liên tục 16 trạng thái. Khi enable = 0 ứng với mỗi trạng thái Sel tại mỗi thời điểm sẽ làm thay đổi đầu ra tương ứng. Khi enable = 1 toàn bộ đầu ra bằng 0. Code VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bai4 is Port ( Enable : in STD_LOGIC; Sel : in STD_LOGIC_VECTOR(3 downto 0); Din : in STD_LOGIC; OutData : out STD_LOGIC_VECTOR (15 downto 0)); end bai4; architecture Behavioral of bai4 is Signal OutPut: STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000"; begin process(Sel, Enable, Din) begin OutPut <= "0000000000000000";
if Enable = '0' then Case Sel is when "0000" => OutPut(0) <= Din; when "0001" => OutPut(1) <= Din; when "0010" => OutPut(2) <= Din; when "0011" => OutPut(3) <= Din; when "0100" => OutPut(4) <= Din; when "0101" => OutPut(5) <= Din; when "0110" => OutPut(6) <= Din; when "0111" => OutPut(7) <= Din; when "1000" => OutPut(8) <= Din; when "1001" => OutPut(9) <= Din; when "1010" => OutPut(10) <= Din; when "1011" => OutPut(11) <= Din; when "1100" => OutPut(12) <= Din; when "1101" => OutPut(13) <= Din; when "1110" => OutPut(14) <= Din; when others => OutPut(15) <= Din; end case; end if; end process; OutData <= OutPut; end Behavioral; Testbench library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is
end test; architecture Behavioral of test is component main is Port ( Enable : in STD_LOGIC; Sel : in STD_LOGIC_VECTOR(3 downto 0); Din : in STD_LOGIC; OutData : out STD_LOGIC_VECTOR (15 downto 0)); end component; Signal Enable, Din : STD_LOGIC :='0'; Signal Sel : STD_LOGIC_VECTOR(3 downto 0) := "0000"; Signal OutData : STD_LOGIC_VECTOR(15 downto 0); begin uut: main port map( Enable => Enable, Sel => Sel, Din => Din, OutData => OutData ); Enable <= not Enable after 200ns; Din <= not Din after 50ns; process begin Sel <= "0000"; for i in 0 to 15 loop wait for 10ns; Sel <= Sel + 1; end loop; end process;
end Behavioral; Bài 5 : Viết mô tả VHDL (Entity và Architecture) cho mạch đó. Viết testbench để kiểm tra hoạt động của mạch. Code VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity bai5 is Port ( CLK : in STD_LOGIC; X : in STD_LOGIC; Z : out STD_LOGIC ); end bai5; architecture Behavioral of bai5 is component JKFF is Port ( CLK: in STD_LOGIC; J : in STD_LOGIC; K : in STD_LOGIC; Q : out STD_LOGIC; QN : out STD_LOGIC ); end component; ----------------------------------------
signal j0_data : std_logic; signal k0_data : std_logic; signal q0_data : std_logic; signal q0n_data : std_logic; signal k1_data : std_logic; signal q1_data : std_logic; signal q1n_data : std_logic; begin j0_data <= q1n_data and X; k0_data <= q1_data xor X; k1_data <= q0n_data nand X; Z <= q0_data and q1_data and X; JKFF_INST0: JKFF Port map ( CLK => CLK, J => j0_data, K => k0_data, Q => q0_data, QN => q0n_data ); JKFF_INST1: JKFF Port map ( CLK => CLK,
J => q0_data, K => k1_data, Q => q1_data, QN => q1n_data ); end Behavioral; Test bench LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Test_bench IS END Test_bench; ARCHITECTURE behavior OF Test_bench IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Bai5 PORT( CLK : IN std_logic; X : IN std_logic; Z : OUT std_logic ); END COMPONENT; --Inputs signal CLK : std_logic := '0';
signal X : std_logic := '0'; --Outputs signal Z : std_logic; -- Clock period definitions -- constant CLK_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Bai5 PORT MAP ( CLK => CLK, X => X, Z => Z ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for 10 ns; CLK <= '1'; wait for 10 ns; end process; -- Stimulus process stim_proc: process
begin -- hold reset state for 100 ns. wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '0'; --000 wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '1'; --001 wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '1'; --010 wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '0'; -- 011 wait until rising_edge(CLK);
X <= '0'; wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '1'; --100 wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '0'; --101 wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '1'; --110 wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '1'; -- insert stimulus here end process; END;
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vhdll.docx

  • 1. Bài 1: Viết chương trình điều khiển 8 LED nháy tròn. Nguyên lý hoạt động của mạch - Mạch có chức năng là điều khiển 8 LED nháy dịch từ LED1 đến LED8 và được sắp xếp thành vòng tròn, chương trình chạy khi clock=1 Code VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity bai1 is Port (clk: in STD_LOGIC; P: out STD_LOGIC_VECTOR (7 downto 0)); end bai1; architecture Behavioral of bai1 is Signal Q: integer := 0; begin process(clk) begin If rising_edge(clk) then if Q = 8 then Q <= 0; else Q <= Q+1; end if; end if; end process;
  • 2. process(Q) begin case Q is when 0 => P <= "00000000"; when 1 => P <= "10000000"; when 2 => P <= "01000000"; when 3 => P <= "00100000"; when 4 => P <= "00010000"; when 5 => P <= "00001000"; when 6 => P <= "00000100"; when 7 => P <= "00000010"; when 8 => P <= "00000001"; when others => P <= "00000000"; end case; end process; end Behavioral; Test bench library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is end test; architecture Behavioral of test is Component Bai1 is Port ( clk : in STD_LOGIC; P : out STD_LOGIC_VECTOR (7 downto 0) );
  • 3. end Component; Signal clk: STD_LOGIC := '0'; Signal P: STD_LOGIC_VECTOR(7 downto 0); begin VVT: Bai1 Port map( CLK => CLK, P => P ); CLK <= not CLK after 10 ns; end Behavioral; Bài 2: Viết chương trình mô tả bộ đếm lùi Mod 9 (có CLK, CLR, Pause) Nguyên lí hoạt động của mạch - Mạch đếm lùi mode 9 có clock, clear và pause. Mạch thực hiện đếm từ 8 về 0,chương trình hoạt động khi clock=1 , khi clear=1 chương trình trở về trạng thái reset là bằng “0000” rồi tiếp tục đếm từ 8 về 0 Code VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bai2 is port (CLK: in std_logic; CLR: in std_logic; PAUSE: in std_logic; count: out std_logic_vector(3 downto 0));
  • 4. end bai2; architecture Behavioral of bai2 is Signal counter: std_logic_vector(3 downto 0) := "1000"; begin process (CLK, CLR, PAUSE) begin if CLR = '1' then counter <= "0000"; end if; if rising_edge(CLK) and CLR = '0' and PAUSE = '0' then if (counter = "0000") then counter <= "1000"; else counter <= counter - 1; end if; end if; end process; count <= counter; end Behavioral; Test bench library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is end test;
  • 5. architecture Behavioral of test is component bai2 is port ( CLK : in std_logic; CLR : in std_logic; PAUSE : in std_logic; count : out std_logic_vector(3 downto 0)); end component; signal CLK,CLR,PAUSE: std_logic := '0'; signal count: std_logic_vector(3 downto 0); begin uut: bai2 port map( CLK => CLK, CLR => CLR, PAUSE => PAUSE, count => count ); CLK <= not CLK after 10ns ; pausess: process begin PAUSE <= '0'; wait for 500ns; PAUSE <= '1'; wait for 80ns; end process; clearr: process begin CLR <= '0'; wait for 700ns; CLR <= '1'; wait for 10ns;
  • 6. end process; end Behavioral; Bài 3 : Viết chương trình mô tả bộ đếm lùi BCD từ 59 đến 00 - hiển thị trên LED 7 đoạn Anode chung (CLK, CLR) Nguyên lí của mạch - Bộ đếm lùi BCD mod 60 đếm lùi từ 59 về 00 và hiển thị trên LED 7 đoạn Anode chung có xung clock và clear. Khởi tạo giá trị ban đầu 2 biến hàng chục và hàng đơn vị bằng 59 và cho chạy dần về 00. Mạch bắt đầu đếm khi clock = 1, khi clear = 1 mạch trở về trạng thái reset là “0000” rồi bắt đầu đếm lại từ 59 về 00 Code VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Bai3 is Port (CLK: in STD_LOGIC; CLR: in STD_LOGIC; Led1: out STD_LOGIC_VECTOR (6 downto 0); Led2: out STD_LOGIC_VECTOR (6 downto 0); OutChuc: out STD_LOGIC_VECTOR(3 downto 0); OutDvi: Out STD_LOGIC_VECTOR(3 downto 0)); end Bai3;
  • 7. architecture Behavioral of Bai3 is Signal Chuc: STD_LOGIC_VECTOR(3 downto 0) := "0101"; Signal Dvi: STD_LOGIC_VECTOR(3 downto 0) := "1001"; begin process (CLK, CLR) begin if CLR = '1' then Chuc <= "0000"; Dvi <= "0000"; elsif CLK'event and CLK = '1' then if (Dvi = "0000") then Dvi <= "1001"; if Chuc = "0000" then Chuc <= "0101"; else Chuc <= Chuc - 1; end if; else Dvi <= Dvi - 1; end if; end if; end process; OutChuc <= Chuc; OutDvi <= Dvi; --Hien thi led process(Dvi) begin case Dvi is when x"9" => Led1 <= "0010000"; when x"8" => Led1 <= "0000000"; when x"7" => Led1 <= "1111000"; when x"6" => Led1 <= "0000010"; when x"5" => Led1 <= "0010010";
  • 8. when x"4" => Led1 <= "0011001"; when x"3" => Led1 <= "0110000"; when x"2" => Led1 <= "0100100"; when x"1" => Led1 <= "1111001"; when others => null; end case; end process; process(Chuc) begin case Chuc is when x"5" => Led2 <= "0010010"; when x"4" => Led2 <= "0011001"; when x"3" => Led2 <= "0110000"; when x"2" => Led2 <= "0100100"; when x"1" => Led2 <= "1111001"; when others => null; end case; end process; end Behavioral; Test bench library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bai3comp is end bai3comp; architecture Behavioral of bai3comp is
  • 9. component bai3code is Port ( CLK : in STD_LOGIC; CLR : in STD_LOGIC; Led1 : out STD_LOGIC_VECTOR (6 downto 0); Led2 : out STD_LOGIC_VECTOR (6 downto 0); OutChuc: out STD_LOGIC_VECTOR(3 downto 0); OutDvi : out STD_LOGIC_VECTOR(3 downto 0)); end component; Signal CLK, CLR: STD_LOGIC := '0'; Signal Led1, Led2: STD_LOGIC_VECTOR(6 downto 0); Signal OutChuc: STD_LOGIC_VECTOR(3 downto 0); Signal OutDvi: STD_LOGIC_VECTOR(3 downto 0); begin MDH: bai3code port map( CLK => CLK, CLR => CLR, Led1 => Led1, Led2 => Led2, OutChuc => OutChuc, OutDvi => OutDvi ); CLK <= not CLK after 10ns; clear: process begin CLR <= '0'; wait for 500ns; CLR <= '1'; wait for 80ns; end process; end Behavioral;
  • 10. Bài 4: Viết chương trình mô tả bộ phân kênh 1:16 (Enable hoạt động ở mức thấp) Nguyên lý hoạt động Bộ phân kênh 1 đầu vào 16 đầu ra, sử dụng Sel 4 bit thay đổi liên tục 16 trạng thái. Khi enable = 0 ứng với mỗi trạng thái Sel tại mỗi thời điểm sẽ làm thay đổi đầu ra tương ứng. Khi enable = 1 toàn bộ đầu ra bằng 0. Code VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bai4 is Port ( Enable : in STD_LOGIC; Sel : in STD_LOGIC_VECTOR(3 downto 0); Din : in STD_LOGIC; OutData : out STD_LOGIC_VECTOR (15 downto 0)); end bai4; architecture Behavioral of bai4 is Signal OutPut: STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000"; begin process(Sel, Enable, Din) begin OutPut <= "0000000000000000";
  • 11. if Enable = '0' then Case Sel is when "0000" => OutPut(0) <= Din; when "0001" => OutPut(1) <= Din; when "0010" => OutPut(2) <= Din; when "0011" => OutPut(3) <= Din; when "0100" => OutPut(4) <= Din; when "0101" => OutPut(5) <= Din; when "0110" => OutPut(6) <= Din; when "0111" => OutPut(7) <= Din; when "1000" => OutPut(8) <= Din; when "1001" => OutPut(9) <= Din; when "1010" => OutPut(10) <= Din; when "1011" => OutPut(11) <= Din; when "1100" => OutPut(12) <= Din; when "1101" => OutPut(13) <= Din; when "1110" => OutPut(14) <= Din; when others => OutPut(15) <= Din; end case; end if; end process; OutData <= OutPut; end Behavioral; Testbench library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is
  • 12. end test; architecture Behavioral of test is component main is Port ( Enable : in STD_LOGIC; Sel : in STD_LOGIC_VECTOR(3 downto 0); Din : in STD_LOGIC; OutData : out STD_LOGIC_VECTOR (15 downto 0)); end component; Signal Enable, Din : STD_LOGIC :='0'; Signal Sel : STD_LOGIC_VECTOR(3 downto 0) := "0000"; Signal OutData : STD_LOGIC_VECTOR(15 downto 0); begin uut: main port map( Enable => Enable, Sel => Sel, Din => Din, OutData => OutData ); Enable <= not Enable after 200ns; Din <= not Din after 50ns; process begin Sel <= "0000"; for i in 0 to 15 loop wait for 10ns; Sel <= Sel + 1; end loop; end process;
  • 13. end Behavioral; Bài 5 : Viết mô tả VHDL (Entity và Architecture) cho mạch đó. Viết testbench để kiểm tra hoạt động của mạch. Code VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity bai5 is Port ( CLK : in STD_LOGIC; X : in STD_LOGIC; Z : out STD_LOGIC ); end bai5; architecture Behavioral of bai5 is component JKFF is Port ( CLK: in STD_LOGIC; J : in STD_LOGIC; K : in STD_LOGIC; Q : out STD_LOGIC; QN : out STD_LOGIC ); end component; ----------------------------------------
  • 14. signal j0_data : std_logic; signal k0_data : std_logic; signal q0_data : std_logic; signal q0n_data : std_logic; signal k1_data : std_logic; signal q1_data : std_logic; signal q1n_data : std_logic; begin j0_data <= q1n_data and X; k0_data <= q1_data xor X; k1_data <= q0n_data nand X; Z <= q0_data and q1_data and X; JKFF_INST0: JKFF Port map ( CLK => CLK, J => j0_data, K => k0_data, Q => q0_data, QN => q0n_data ); JKFF_INST1: JKFF Port map ( CLK => CLK,
  • 15. J => q0_data, K => k1_data, Q => q1_data, QN => q1n_data ); end Behavioral; Test bench LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Test_bench IS END Test_bench; ARCHITECTURE behavior OF Test_bench IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Bai5 PORT( CLK : IN std_logic; X : IN std_logic; Z : OUT std_logic ); END COMPONENT; --Inputs signal CLK : std_logic := '0';
  • 16. signal X : std_logic := '0'; --Outputs signal Z : std_logic; -- Clock period definitions -- constant CLK_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Bai5 PORT MAP ( CLK => CLK, X => X, Z => Z ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for 10 ns; CLK <= '1'; wait for 10 ns; end process; -- Stimulus process stim_proc: process
  • 17. begin -- hold reset state for 100 ns. wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '0'; --000 wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '1'; --001 wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '1'; --010 wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '0'; -- 011 wait until rising_edge(CLK);
  • 18. X <= '0'; wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '1'; --100 wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '0'; --101 wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '0'; wait until rising_edge(CLK); X <= '1'; --110 wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '1'; wait until rising_edge(CLK); X <= '1'; -- insert stimulus here end process; END;