OPAL-RT - Democratize real-time simulation

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OPAL-RT TECHNOLOGIES

Presented at PES 2013

One Goal
Democratize Real-Time Simulation
“Real-time simulation is indispensable for
engineer-designers. OPAL-RT’s mission is to
make it accessible to all”
Jean Bélanger, CEO.

OPAL-RT’s
Unique Personality

What We Do Best

What it
Means for Our
Customers

More Power
HYPERSIM 32 cores
eMEGAsim (MMC)

HYPERSIM
Power System Real-Time Simulator

eMEGAsim
Leadership in the Modular Multilevel
Converter (MMC) Application

More Possibilities
eFPGAsim (eHS)
ePHASORsim
RT-LAB Berta Test Bench

eFPGAsim
Power Electronic Real-Time Simulator
Using the advanced electrical system solvers (eHS)

ePHASORsim
Real-Time Transient Stability Solver

RT-LAB BERTA
Test Bench
Power System Frequency Control

More Value
OP4500

OP4500
RT-LAB / RCP / HIL System
The first real-time power grid digital simulator
under $20,000

OPAL-RT
A Solid Alternative
to Overpriced
Real-Time Digital Simulators

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Clock gating is an effective method of reducing the dynamic power consumption in synchronous circuits. One of the ways to achieve this is by masking the clock that goes to the idle portion of the circuit. In This paper we will present a comparative analysis of existing clock gating techniques on some synchronous digital design like ALU (Arithmetic logical unit) etc. Also a new clock gating technique that provides more immunity to the existing problem in available technique. In new proposed clock gating the Gated Clock Generation Circuit is using tri state buffer and Gated logic is used which is created by the combination of double gated (AND, OR, AND logic gate) with bubbled input respectively. This circuit saves power even when Target device's clock is ON. All experiments are done on Xilinx14.1 EDA tool. Mentor Graphics Model SIM. For power calculation we are using XPOWER. Sparten-3 (90nm) FPGA platform is used for result and analysis. The proposed design will reduce the hardware complexity with approximately 10-20%. Similar clock power complexity will reduce with 5-10%. Keywords — Tri state buffer; VLSI; Xilinx; glitches; hazards;Sparten.

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2017 Atlanta Regional User Seminar Introduction

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The value of a flexible API Management solution for Open Banking Steve Melan, Manager for IT Innovation and Architecture - State's and Saving's Bank of Luxembourg Apidays New York 2024: The API Economy in the AI Era (April 30 & May 1, 2024) ------ Check out our conferences at https://www.apidays.global/ Do you want to sponsor or talk at one of our conferences? https://apidays.typeform.com/to/ILJeAaV8 Learn more on APIscene, the global media made by the community for the community: https://www.apiscene.io Explore the API ecosystem with the API Landscape: https://apilandscape.apiscene.io/

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OPAL-RT - Democratize real-time simulation

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8. More Power HYPERSIM 32 cores eMEGAsim (MMC)

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10. eMEGAsim Leadership in the Modular Multilevel Converter (MMC) Application

11. More Possibilities eFPGAsim (eHS) ePHASORsim RT-LAB Berta Test Bench

12. eFPGAsim Power Electronic Real-Time Simulator Using the advanced electrical system solvers (eHS)

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16. OP4500 RT-LAB / RCP / HIL System The first real-time power grid digital simulator under $20,000

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