2. REGISTERS
Group of Flip flops
Used to store binary numbers
One flip flop for each bit
To store 8-bit numbers = register must have eight flip flops
Binary number entered into the register and possibly shifted out
Shift Registers = A group of Flip flops connected to provide both
of these functions (enter & shift)
A bit in binary number == moved from one place to another in two
ways

3. Two methods
 Serial shifting – shifting the data bit in serial fashion,
beginning with either MSB or LSB
 Parallel shifting – shifting all the data bits simultaneously.
 two ways to shift data into a register === two ways to shift data out
of a register
 Four basic types (TTL MSI/LSI circuits)
Serial in - Serial out : IC 7491 : 8 bits
Serial in - parallel out : IC 74164 : 8 bits
Parallel in - serial out : IC 74165 : 8 bits
Parallel in - parallel out : IC 74194 : 4 bit
: IC 74198 : 8 bits

5. SERIAL IN – SERIAL OUT
 JK flip flop or D flip flop usually used for Registers.
 Data bit shifted must be present in J & K inputs during the clock pulses
 Two cases
 To shift a 0 into the flip flop, J = 0 and K = 1
 To shift a 1 into the flip flop, J = 1 and K = 0
 JK Master slave flip-flop is sensitive to negative clock transitions – shift pulse
 JK Master slave flip shift register
 At time A, Q = 0 ( 0 shifted into the flip flop) ( J = 0, K = 1)
 At time B, Q = 0 ( J = 0, K = 1)
 At time C, Q = 1 ( Flip flop is set)
( J = 1, K = 0)
 At time D, Q = 0 ( J = 0, K = 1)

6.  Four flip flops connected in series
 At time A, all flip flops = reset ( J = 0, K = 1)
T = reset, ( 0 in S shifted into T, 0 in R shifted
into S, 0 in Q shifted into R, data input 0
shifted into Q ) ===== QRST = 0000
 At time B, all flip flops = 0 ( 0 in S shifted into
T, 0 in R shifted into S, 0 in Q shifted into R,
data input 0 shifted into Q ) ,QRST = 0000
 At time C, ( J = 1, K = 0), ( 0 in S shifted into
T, 0 in R shifted into S, 0 in Q shifted into R,
data input 1 shifted into Q ) ,QRST = 1000
 At time D, ( J = 0, K = 1) ( 0 in S shifted into
T, 0 in R shifted into S, 1 in Q shifted into R,
data input 0 shifted into Q ) QRST = 0100
4 bit shift registers

7.  Shifting LSB first
 LSB in T & MSB in Q
 Technique is used to construct serial –input shift register
 J & K should complement to each other
 J = K & K = J
 Connect inverter between J & K = D flip flop , Single input , On negative
clock transition, the data present at the D input will shift into the flip flop.
 4-bit serial input register with D flip flop
 Before Time A == QRST = 1010
 At Time A, Data = 0, QRST = 0101
 At Time B, Data = 0, QRST = 0010
 At Time C, Data = 0, QRST = 0001
 At Time D, Data = 0, QRST = 0000
 Stored bit shift right, after four clock pulse it was
lost

8. Pinout diagram of 74LS91
Logic diagram of 74LS91
 8-bit TTL MSI Chip
 Eight RS flip flop connected = to
provide serial input & serial output
 Negative edge triggered flip flop
=== applied clk pulse pass through
inverter = shift on +ve edge pulse
 Inverter between RS flipflop = D FF
 Input = A or B

9. Serial in Parallel out
 Data shifted in serial , shifted out in parallel
 connecting output of each flip flop to an output pin
 8-bit shift register == 8 output lines
 IC 54/74164 = SIPO shift register.
 Constructed by using RS flip flop having clock inputs
that are sensitive to negative clock transitions

10.  Two exceptions
 First : true side of each flip flop = output
any number stored in register ==available as an output
 Second : has an asynchronous clear input ( not synchronous with clk input)
low at the input = reset all the flip flops.
Clear = low === Flip flop remains low.
Logic diagram of 54/74164

11.  Data at the serial inputs changed while clock is low or high
 Setup and hold times must be observed.
 Setup time = minimum 30ns
 Hold time =0.0nss
 Two inputs A & B
 Data input to A, B as an control inputs
 B =1, NAND = enabled, Input pass through NAND gate inverted, Data shifted
serially into the register
 B = 0, NAND output = high , input data = inhibited, next positive clk pulse shift 0
to the first flip flop, every pulse 0 shifted into each flipflops. Finally the register =
full of zeros

12.  Serial input at Pin 1 = A, Pin 2 = B
 Clear pulse at Time A, reset all the Flipflop to 0
 At B, Data bit (A) =1, control bit = 0, No change in
the output,
 At C, Data bit (A) =0, control bit = 1,
 At time D, First data 0 shifted into register
 At time E, F, G, H, I, J, K==== next 7 data were
shifted
 Final output = 0010 1100, LSB in QH
 Clk stopped, shifting process stopped,
otherwise data will lost