A COMPREHENSIVE STUDY AND PERFORMANCE COMPARISON OF M-ARY MODULATION SCHEMES ...
Report AdvancedCodingFinal - Pietro Santoro
1. Advanced Wireless Communications
Report of the laboratory sessions
2015/16
Student:
Pietro Santoro
Teacher:
Guido Montorsi
POLITECNICO DI TORINO
Master Degree in Telecommunication Engineering
2.
3. Pietro Santoro
Table of Contents
PC SESSION 1: LIMITS OF CODING ........................................................................................................................................ 1
1.1 Bounds for the capacity: Software implementation 2
1.2 Infinite block size analysis 3
1.3 Finite length analysis 5
1.4 Bounds achieved with MI statistics 7
PC SESSION 2: SISO DECODING ...............................................................................................................................................9
2.1 SISO Decoder, software implementation 10
2.2 SISO simulation results 16
PC SESSION 3: PCCC DECODING .......................................................................................................................................... 17
3.1 PCCC software implementation 18
3.2 PCCC simulation results 19
PC SESSION 4: SCCC DECODING ........................................................................................................................................... 21
4.1 SCCC software implementation 22
4.2 SCCC simulation results 22
PC SESSION 5: LDPC DECODING........................................................................................................................................... 24
5.1 LDPC codes 25
5.1 LDPC software implementation 26
5.1 LDPC simulation results 27
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PC session 1 – Limits of coding
Purpose of session:
To compute of mutual information for several common modulation sets
To compute the lower bounds to achievable frame error rate for several
information block sizes, codulator rates and 2 dimensional modulations
To compute, through the simulation software, the statistic of finite block size
mutual information for several information block sizes and two dimensional
modulations
Assignments:
1. Computation of mutual information for several common modulation sets (2,8,16)-PSK and
(4,16,64)-QAM (It is assumed infinite block size)
2. Using the sphere packing bound, computes lower bounds using the on achievable
performance (FER) with finite block size
a. Information Block sizes 100,1000,10000,100000, Infinity
b. Modulations (2,8,16)-PSK and (4,16)-QAM
c. FER 10-1
-10-8
3. Compute through simulation the statistic of finite block length MI for several values of the
codeword size (50,100, and 1000 channel uses). The finite block length MI is the random
variable defined as:
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1.1 Bounds for the capacity: Software implementation
The purpose of the following analysis is the comparison between different modulation sets in
terms of capacity. The block diagram is the following:
Figure 1.1
The input parameters for the system can be properly setting by modifying the file
input_finite_length_analysis.txt:
Output file prefix
Pit
Constellation type
QAM
Constellation Cardinality (log2)
2
Es/N0 [dB] (min,max,step)
0,20,1
Finite length analysis
0
Information size (min,max,step)
100,100000,10
-log10(P(e)) (min,max,step)
1,8,1
It is possible to set the constellation scheme (QAM or PSK) and its cardinality, the range in which
we want to vary the SNR and probability of error and finally we have also the possibility to choose
between finite and infinite length analysis by putting as flag 1 or 0 respectively .
The software is implemented in order to find the capacity of a Gaussian channel that is
constrained at the input with a 2D constellation. The formula that it applied in the simulation loop
is the following:
where:
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𝐸𝑠
𝑁0
is the SNR and in particular 𝐸𝑠 is the average energy per symbol
(𝑎𝑗 − 𝑎𝑖) and (𝑏𝑗 − 𝑏𝑖) are the coefficient for the constellation points
1.2 Infinite block size analysis
The first part of the simulation has been done under the following assumptions:
Infinite block size (and below “Finite length analysis” the flag is 0)
Constellation cardinality 𝑚 = 2
Spectral efficiency 𝜀 𝑏 =
2
𝑚
𝑟 = 𝑟
The Shannon Theorem for AWGN channel imposes a limit on the rate, 0 ≤ 𝑟 ≤ 𝐶 of the
communication, but ensures the existence of a code that achieves arbitrary low error probability
for infinite block size. The following graphs give information about the power employment in the
transmission respect to the amount of transmitted information bits. As we can observe in the
following graph (figure 1.2), the shape of the curves is the same for all the considered cases:
Figure 1.2 – Capacity of different constellation schemes in function of the SNR
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each line, that is for 𝑟 = 𝐶 , divides the plot into two regions: the upper region, where 𝑟 > 𝐶, that
represents the unattainable efficiency part and the lower one, where 𝑟 < 𝐶, that is the real and
less efficient part.
Because we are assuming that all the points of the constellation are transmitted with same
probability
1
𝑀
, differently from the optimal Gaussian distribution; the first thing we can notice is
the asymptotic trend of the curves under the limit log2 𝑀, that is the maximum number of bit per
channel use that we can transmit with an M-ary modulation scheme (with 4QAM and 4PSK we can
convey at maximum 2 bits per channel use, with 16QAM and 16 PSK, 4 bits and so on).
Another important aspect we want to highlight is the value that curves have for the value of
capacity 1 bit per channel use: we have 0 dB for the ideal case and 0.2 dB for the 4QAM: it
suggests that if we want to use a constellation scheme with higher cardinality we have to use it in
the best way we can. More bit for each block means more energy per signal and for this reason
the efficiency curve for 4QAM starts to move away from the ideal one.
It is interesting to compare the M-QAM modulation schemes with respect to the MPAM ones:
for a fixed value of Eb/No, MPSK has an unacceptable loss with respect to the
corresponding MQAM which is almost half of the capacity. This is due to the fact that M-
PSK modulation sets exploit only the phase variation. In the MQAM, we have two degree of
freedom in the structure of the constellation: phase and amplitude. For this reason MPSK is
never used with modulation efficiency up to 8.
for all the Eb/No values we notice that the best performance are achieved by the 64QAM
modulation scheme. The price to pay for, this good behavior is the complexity of the
transmission system. ( Above of all we have to pay for the complexity of the receiver )
M-QAM modulation techniques are very good but we have to notice that before they start
bending there's a residual gap due to the shaping loss. This loss comes from the comparison
between the Gaussian PDF with the discrete one of MQAM modulation sets. These PDFs are
represented with a series of delta function. Even if we increase the number of points of the
constellation we cannot reach the ideal case.
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1.2 Finite block size analysis
When we impose a finite value for the block size we find a lower bound for the 𝑃𝑤(𝑒) thanks to
the sphere packing bound. The bound is in the form 𝑃𝑤(𝑒) ≥ 𝑄 𝑛(𝜗; 𝐴), where:
and:
This bound has been obtained for Gaussian modulation. When we use the sphere packing bound
for modulations different from the Gaussian one it is a reasonable to follow the following
inequality and provide an Eb/No as below:
where:
are the minimum required Eb/No for information block size k to achieve a 𝑃𝑤(𝑒) using respectively
the modulation M and the unconstrained Gaussian modulation U, and:
are the minimum required Eb/No for an infinite information block size using respectively the
modulation M and the unconstrained Gaussian modulation U.
In the figure 1.3 is shown the lower bounds of the FER as function of Eb/No using 4QAM
modulation, for different block size k = 1000; 10000; 100000 in comparison with the ideal case
(infinite block size). The first curve in the graph represents the capacity for infinite block size and
unconstrained modulation (ideal condition): with a fixed codulator rate equal to 0.97 (code rate ≈
1/2 ) the required Eb/N0 is equal to -0.046 dB. The second one shows the capacity for infinite block
size but with a constrain in the modulation. The other curves vary according to the block size
(k=1000, 10000, 100000). As we can expect, for an higher value of k the performances are closer
and closer to the ideal case.
Moreover, for lower values of k the slope of the curve is less vertical because the choice of the
Pw(e) is not more arbitrary as in the ideal case and the gap of Eb/N0 becomes higher.
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1.3 Bounds achieved with MI statistics
In this section we apply a more general method for the study the mutual information that can be
applied to any type of channel.
The assumptions are: the channel is memoryless and ergodic. The instantaneous mutual
information is computed as:
where:
n is the block size
log(𝑃(𝑦𝑖|𝑥𝑖)) and log(𝑃(𝑥𝑖)) are LLRs
The following technique allows us to derive reliable statistics by just using simulations with a large
n. All the results obtained in this analysis have been carried out simulating a 4QAM modulation
scheme.
The statistics bring to a set of histograms that describes the distribution of the Mutual Information
for each imposed value of Es/N0. For n that tends to infinity the distribution becomes a delta
function centered into the mean that corresponds to the capacity.
Figura 1.4 – Distribution of the Mutual Information for different Eb/N0
In the following figures (1.5 and 1.6) we can compare the results for the 4QAM modulation
scheme with different block size 𝑛 = 100 and 𝑛 = 10000.
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The evolution of the mean is the same in both cases because for an increasing SNR the MI is
bounded with the capacity and the evolution of the variance changes. As we expect, for higher n,
the accuracy of the estimation is high and it can be observed in terms of lower variance.
Figura 1.5 – Mean and variance of the estimate for 4QAM and block size 100
Figura 1.6 - Mean and variance of the estimate for 4QAM and block size 10000
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PC session 2 – SISO decoding
Purpose of session:
To design and implement a C++ class realizing a Sliding Window with grouped
decisions Soft-Input Soft-Output decoder (SWG-SISO), with input and output binary
LLR.
To simulate the performance of a transmission system of Errore. L'origine
riferimento non è stata trovata. employing a binary convolutional code, 2-PAM
modulation, AWGN channel and the developed binary SWG- SISO decoder.
To compute the BER performance at the input and at the output of the SISO
decoder.
Figure a - Block diagram of the system
Assignments:
I. Comment the developed class (files “SISO_Decoder.cpp” and “SISO_Decoder.h”)
II. Simulate the results relative to the rate ½, 4 and 8 states convolutional encoder
reporting the 4 BER measures versus the Es/N0 in [dB]
Convol.
encoder
2-PAM
AWGN
2-PAM
AWGN
inf
enc
Soft
Demod
Soft
Demod
SISO
SISO
n0 bits
SISO
Dec
infRXI
encRXI
infRXO
BER
BER
BER
BER
encRXO
LLR
k0 bits
observbits
inf
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2.1 SISO decoding, software implementation
The following are the C++ classes, “SISO_Decoder.cpp” and “SISO_Decoder.h” that implement the
SISO decoder module that is depicted in the block diagram in figure a.
//BEGINNING SISO_Decoder.h
#pragma once
#include "Trellis.h"
class SISO_Decoder
{
public:
SISO_Decoder(void);
~SISO_Decoder(void);
void SetParameters(
const Trellis* trel,
const int D,
const int Nbl
);
void Run(
const int nsteps, // Number of processed trellis steps
const int* llruI, // Input bit LLR on information bits
const int* llrcI, // Input bit LLR on coded bits
int* llruO, // Output extrinsic LLR on inf bits
int* llrcO // Output extrinsic LLR on cod bits
);
void Reset();
private:
int time; // Counter of trellis steps
int ndata; // Number of data already read-out
int D; // Length of initialization window
int Nbl; // Length of updating window
int W; // Overall latency of the algorithm, length of the window
int k0; // Number of information bits per trellis step
int n0; // Number of coded bits per trellis step
int nbit; // Number of total bits per trellis steps (k0+n0)
int nsta; // Number of states
const Trellis* trel;
int* alpha; // Buffer to store results of forward recursion
int* beta; // Buffer to store results of backward recursion
int* llrinp; //buffer to store input LLR
int* llrout; //buffer to store output LLR
int* llrsym; // buffer to store output branch metrics
int* llrsymo; // buffer to store output branch metrics
int ntra; //Number of transitions = cardinality of input alphabet
int nlab; // Number of branch labels
int* aold,*anew;
};
//ENDING SISO_Decoder.h
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void maxacc(int& a, const int b)
{
int c=a-b;
if(c>0)return;
else
{ a=b;
return;
}
}
void bittobranch(const int nbit, const int* llrbit, int* llrsym)
{
int nsym=(1<<nbit); // number of symbols is 2^ number of bits
int i,k;
for(i=0;i<nsym;i++)
{
llrsym[i]=0;
for(k=0;k<nbit;k++)
{
llrsym[i] += ((i>>k)&1)* llrbit[k]; // Extract k-th bit from i
}
}
}
void branchtobit(const int nbit, int* llrsym, int* out)
{ int k,j,n0,n1;
int Nu=1<<nbit;
for(j=nbit-1;j>0;j--) // Cycle on constituent symbols
{ Nu>>=1;
/* 0 */
n0=llrsym[0];
for(k=1;k<Nu;k++)maxacc(n0,llrsym[k]);
/* 1 */
n1 = llrsym[Nu];
maxacc(llrsym[0],llrsym[Nu]);
for(k=1;k<Nu;k++)
{ maxacc(n1,llrsym[Nu+k]);
maxacc(llrsym[k],llrsym[Nu+k]);
}
out[j]=n1-n0;
}
out[0]=llrsym[1]-llrsym[0];
}
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// Core of the program!!
void SISO_Decoder::Run(
const int nsteps, // Number of processed trellis steps
const int* llruI, // INTPUT: LLR of input information bit (k0 LLR per trellis step)
const int* llrcI, // INTPUT: LLR of input coded bit (n0 LLR per trellis step)
int* llruO, // OUTPUT: LLR of input information bit (k0 LLR per trellis step)
int* llrcO // OUTPUT: LLR of input coded bit (n0 LLR per trellis step)
)
{
int i,j,k,e,s,u,p;
int Ne=nsta*ntra; // Number of edges
int *bn; // pointer to the new values of backward recursion
int *bo; // pointer to the old values of backward recursion
int label,temp;
int ntra=1<<k0;
int nlab=1<<nbit;
// LOOP ON EACH TRELLIS STEP:
1. Initialization of the backward recursion
2. Aggregation of the LLRs on bits into branch metric
3. Backward recursion of size W=D+Nbl
4. Forward recursion of size Nbl and computation of the output branch matric
5. Marginalization of the branch metrics into LLRs on the bits
6. Storing of the data it the output buffer llruO
for(i=0;i<nsteps;i++)
{
// The input data are stored in the vector llrinp (circular buffer) and the pointer time is
increased each time it is processed a new trellis step
for(j=0;j<k0;j++)llrinp[time*nbit+j]=llruI[j];
for(j=0;j<n0;j++)llrinp[time*nbit+k0+j]=llrcI[j];
// The output computed extrinsic LLR are stored in the vector llrout (circula buffer) and the
pointer is incremented each time it is processed a new trellis step
for(j=0;j<k0;j++)*llruO++=llrout[ndata*nbit + j];
for(j=0;j<n0;j++)*llrcO++=llrout[ndata*nbit + k0+j];
// The pointers ndata and time are restored to zero when they reach respectively the values Nbl
and W
ndata = (ndata+1)%Nbl;
time = (time+1)%W;
// Here I’m checking if a new block can be decoded
if(ndata==0)
{
// 1. Backward recursion initialization: because we don’t know the final state we are assuming that
all the states have the same probability and for this reason we are setting to zero the values of
beta
for(k=0;k<nsta;k++)beta[(W-1)*nsta+k]=0;
for(k=W-2;k>=0;k--)
{
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p = (time+k+1)%W; // Here I’m retrieving the position of the
column corresponding to the correct time
instant
// 2. I’m storing the branch metric into the vector llrsym
bittobranch(nbit,llrinp + p*nbit, llrsym);
bo = beta+(k+1)*nsta; // pointer to old beta metrics
bn = beta+(k)*nsta; // pointer to new beta metrics
// we need to pointers because one is in
function of the other
// In this loop I compute the branch metrics for all the edges e and
the first thing that I do is to initialize to - ∞ (-10-7
) all the metrics
for(s=0;s<nsta;s++)bn[s]=-10000000;
// Here I fill the trellis
for(e=0;e<Ne;e++)
{
// Here I compute the label associated to the edge
label=(trel->trel[4*e+2]<<k0)+trel->trel[4*e+1];
// 3. Here I compute backward path metric
maxacc(bn[trel->trel[4*e+0]], // Branch metric
associated to the Starting
state sS
(e)
bo[trel->trel[4*e+3]]+ // Branch metric
associated to the Ending
state sE
(e)
llrsym[label]); // Branch metric
associated to the label
associated with the edge
u(e)/c(e)
}
}
// Here we start the forward recursion
for(k=0;k<Nbl;k++)
{
// Compute input branch metrics from LLR
p=(time+k)%W;
bittobranch(nbit,llrinp+p*nbit,llrsym);
// Initialization of all max* accumulators
for(s=0;s<nsta;s++)anew[s] =-1000000;
for(s=0;s<nlab;s++)llrsymo[s]=-1000000;
// Loop on all edges
for(s=0;s<nsta;s++)for(u=0;u<ntra;u++)
{
label = (trel->output(s,u)<<k0)+trel->input(s,u);
maxacc(anew[trel->ending(s,u)],
aold[trel->starting(s,u)]+llrsym[label]
);
// 4. Here I compute forward path metric
maxacc(llrsymo[label],
aold[trel->starting(s,u)]
The complexity of all the
algorithm depends on
these important lines. The
most important parameter
in terms of complexity is
the number of states Ne
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+llrsym[label]
+ beta[j*nsta + trel->ending(s,u)]
);
}
// 5. Computation of the LLRs on bit from output branch metrics
branchtobit(nbit,llrsymo,llrout+j*nbit);
// 6. . Computation of the total LLR to extrinsic LLR
for(s=0;s<nbit;s++)llrout[j*nbit+s] -= llrinp[p*nbit+s];
// Swapping of the pointers of forward path metrics
bn=aold;
aold=anew;
anew=bn;
}
}
}
}
//ENDING
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2.2 SISO Decoder simulation results
In this section we will analyze the result figured out from the simulation of the system depicted in
the figure 2a. Here are exposed the graphs related to its performance that are expressed in term
of BER. As we can observe in the figure 2a, the block diagram contains a convolutional encoder
with and a SWG-SISO module as decoder. The convolutional encoder has been set with 4 and 8
states.
It may be also possible to adjust the window size by properly setting Nbl and D; but this is not
important for our goal because it could be useful only in those particular cases where has to be
analyzed the tradeoff between window size and decoding complexity.
The chosen Parameter for the SWG-SISO are D = 20 and Nbl = 1000.
Figure 3.1
In Figure 2.1 it can be observed the Information Bit Error curves as function of Eb/N0 for 4 and 8
state Encoders before and after the SISO module. As we expect, increasing the number of states of
the encoder the performances improve since the correction capability of the code is related to its
memory.
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PC session 3 – PCCC decoding
Purpose of session:
To understand the simulation program for a PCCC
To understand the termination of convolutional codes
To simulate and plot the performance of a rate 1/3 PCCC with different constituent
encoders and interleaver block sizes
Figure 4a - Block diagram of coding system based on PCCC and correspondent iterative decoder
Assignments:
I. Simulate the system in figure 3a in order to obtain BER and FER plots with 4 and 8
state encoders and interleaver size 100, 1000, 10000 and comment the obtained
plots.
Convol.
encoder
1
2-PAM
AWGN
2-PAM
AWGN
inf
enc1
Soft
Demod
Soft
Demod
enc1RX
infRX
BER[2]
Convol.
encoder
2
Int
enc2RX
SISO
SISO
SISO
Dec2
IntDeint
infpRX infpRX
infRX1
enc2
infp
SISO
SISO
SISO
Dec1
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3.1 PCCC software implementation
In the following we will analyze the performance of a communication system that uses a Parallel
Concatenated Convolutional Code (figure 3a). The source generates a sequence of information
bits of length N (inf); the PCCC Encoder is composed of two constituent convolutional encoders
working in parallel: the upper encoder generates the sequence enc1 of encoded bits with rate r1
while the lower one, that receive a permuted version of the sequence of information bit infp ,
generates the sequence enc2 with rate r2.
The overall PCCC Encoder has rate 𝑟 =
𝑟1 𝑟2
𝑟1+ 𝑟2
Upper and lower encoders are systematic and recursive. They are chosen by setting the
coefficients of the pair [Z,H] in the file test_PCCC_decoder.cpp. For example if [Z,H]=[015,013] it
corresponds to the binary couple [001101,001011]. It is used to describe the polynomial
[1+D2
+D3
,1+D+D3
] that refers to the encoder in figure 3.1:
Figure 3.1 – 8-states, SR encoder described by the polynomial
// SETTING FOR 8-states
int H[]={013};
int Z[]={015};
// SETTING FOR 4-states
// int H[]={07};
// int Z[]={05};
The 4-states encoder is represented by the pair [05,07] while the 8-state one by the pair [015,013]
(as we can see in the reported code).
The sequences enc1 and enc2 are both mapped by a 2-PAM modulation scheme that outputs
respectively the sequences mod1 and mod2 that are transmitted over an AWGN Channel. The
received sequences, that are rec1 and rec2 are passed to the SISO module that produces LLRs
sequences on coded bits: enc1RX and enc2RX.
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The two sequences enc1RX and enc2RX are finally processed by the PCCC Decoder to extrapolate
the information bits. The core of the decoder is a couple of two SISO Decoders that share
information about the LLRs on output information bits in order to satisfy the equality:
The extrinsic information computed from one encoder is considered as a-priori information for the
other one and vice versa.
Thanks to the provided software, it has been possible to simulate a PCCC Decoder with overall rate
𝑟 =
1
3
, obtained by concatenating two systematic recursive constituent encoders with changeable
number of states. As requested from the assignment we have simulated the system with 4 and 8
states, and with interleaver size of 100, 1000 and 10000.
3.2 PCCC simulation results
By looking at the figure 3.1 and 3.2 we can easily observe that BER, and similarly FER, curves drop
more rapidly to smaller values of the Pb(e) when we increase the interleaver size N (a tradeoff has
to be considered between the increment of N and the performance we desire because the latency
of the decoder increases with the increment of the interleaver size).
If we focus on the BER and FER curves another thing that is easy to observe are the three main
regions of a the BER curve of a PCCC: the Non convergence, Waterfall and the Error Floor regions.
As we studied in the theory can be confirmed from the plot: by comparing performances of 4 and
8 states encoders we cannot say that one performs better than the other for all values of SNR
because there is a point where the two curves cross each other. The choice of the first or the
second will be done depending on the requirement.
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Figure 3.2 – BER curves for different values of #states and interleaver size N
Figure 3.3 – FER curves for different values of #states and interleaver size N
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PC session 4 – SCCC decoding
Purpose of session:
To understand the simulation program for a SCCC
To simulate and plot the performance of a rate 1/4 SCCC with different constituent
encoders and interleaver block sizes
Figure 4a - Block diagram of rate 1/4 coding system based on SCCC and correspondent iterative decoder
Assignments:
I. Simulate the system in figure 4a in order to obtain BER and FER plots with 4 and 8 state
encoders and interleaver size 100, 1000, 10000 and comment the obtained plots
Convol.
encoder
1
2-PAM
AWGN
inf
enc1
Soft
Demod
enc1RX infRX
BER[2]
Conv.
encoder
2
Int
enc2RX
SISO
SISO
SISO
Dec2
IntDeint
enc1pRX enc1pRX
enc2enc1p
SISO
SISO
SISO
Dec1
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4.1 SCCC software implementation
In this section of the report we will analyze the performance of a communication system that uses
a Serial Concatenated Convolutional Code (figure 3a). The architecture of the software is similar
to the one we have seen in the third chapter of the report for PCCC: the source generates a
sequence of information bits of length N (inf); the core of the SCCC Encoder is composed of two
constituent convolutional encoders working in serial: the outer encoder (convolutional encoder 1)
generates the sequence enc1 of encoded bits (at rate r1 ) that is interleaved and sent as input to
the inner encoder (convolutional encoder 2) as enc1p. This last one generates the sequence enc2
with rate r2. The overall SCCC Encoder has rate 𝑟 = 𝑟1 𝑟2
The sequence enc2 is mapped by a 2-PAM modulator and it is transmitted over an AWGN Channel.
The received sequence is passed to the SISO module that produces LLRs sequence on coded bits:
enc2RX.
The sequence enc2RX is finally processed by the SCCC Decoder to extrapolate the information bits.
The core of the decoder is a couple of two SISO Decoders that share information about the LLRs on
output information bits with the aim of allowing an iterative process that makes possible, as for
PCCC decoding, the convergence of the system of equations:
Figure 4.1 – Architecture of the core of the SCCC decoder
4.2 SCCC simulation results
In the following figures (4.1 and 4.2) is it possible to observe the BER and FER curves obtained
thanks to the simulation of the SCCC system by varying number of states (4 and 8 states) and
interleaver size (N=100,1000 and 10000). The curves we have obtained for SCCC are not well
define as we experienced for PCCC; it is an indication of the higher complexity of this algorithm
with respect to the same we have already used for PCCC because the tests has been done on the
same calculator.
Similarly to PCCC, we can notice that the interleaver size is the key parameter for the reaching of
low values of error probability: 8 states and 10000 is the best combination we can use for high
performance of the system.
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Figure 4.2 – BER curves for different values of #states and interleaver size N
Figure 4.3– FER curves for different values of #states and interleaver size N
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PC session 5 – LDPC decoding
Purpose of session:
To understand the simulation program for an LDPC
To understand LDPC encoding by back substitution
To understand the difference between optimal and suboptimal decoding algorithm (min-
sum-offset) for LDPC
To simulate and plot the performance of the LDPC code for the DVB-S2 standard.
Figure 5a - Block diagram of the transmission system using LDPC encoder
Assignments:
BER and FER plot with rate ¼ and 8/9 with medium block length (16200) with optimal and
suboptimal decoder
BER plot with rate ½ with optimal decoder and suboptimal decoder with for different
values of the offset parameter beta (short block)
BER plot with rate ½ and the three values of available block length (short, medium and long
code) use the algorithm that you like.
Comment on the plots
LDPC_Encoder
2-PAM
AWGN
inf
enc Soft
Demod
rec LDPC_Decoder
Run
RunSubopt
encRX
infRX
BER
betancode
isshort
DVBS2 Encoder
esn0
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5.1 LDPC codes
They are special linear block codes whose have a “sparse” parity check matrix H. Their importance
is due to the good performance that is possible to achieve (well comparable with PCCC and SCCC
performances). The encoding technique has low complexity since the code word would consist of
the message bits and some parity check bits. What the LDPC encoder do can be roughly
schematized as follow: it choose certain variable nodes to place the message bits on and in the
second step calculate the missing values of the other nodes. In this way it solves the parity check
equations.
In practice however, more clever methods are used to ensure that encoding can be done in much
shorter time (parallel processing is possible) by exploiting the property of “sparseness” of the
parity-check matrix and a certain structure for the Tanner graph.
The decoding process is based on belief propagation algorithm between the variable and check
nodes. The algorithm can be described graphically by constructing the Tanner Graph (figure 5.1) of
a generic LDPC code:
Figure 5.1 – Tanner Graph of an H matrix of a generic LDPC code
{𝑣1 , 𝑣2 … 𝑣 𝑛} are the variable nodes {𝑐1 , 𝑐2 … 𝑐 𝑛−𝑘} are the check nodes. The number of edges
connected to a variable node 𝑣𝑖 is the degree of the variable node 𝑑 𝑣𝑖 , whereas the number of
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edges connected to a check node 𝑐𝑗 is the degree of the check node 𝑑 𝑐𝑗 . At the nth
iteration of
the algorithm, the generic message sent by a variable node 𝑣𝑖 to a check node 𝑐𝑗 is denoted by
𝑓(𝑛)
(𝑣𝑖, 𝑐𝑗 ), whereas the message sent by a check node 𝑐𝑗 to a variable node 𝑣𝑖 is denoted by
𝑓(𝑛)
(𝑐𝑗 , 𝑣𝑖). Adopting the belief propagation algorithm:
𝑓(𝑛+1)
(𝑣𝑖, 𝑐𝑗 ) = 𝑙𝑙𝑟𝑖 + ∑ 𝑓(𝑛)
(𝑐 𝑚 , 𝑣𝑖)
𝑑 𝑣𝑖
𝑚=0,𝑚≠𝑗
All the 𝑓(𝑛)
(𝑐𝑗 , 𝑣𝑖) can be computed in two different ways:
Application of the Sum-prod operation
𝑓(𝑛+1)
(𝑐𝑗, 𝑣𝑖 ) = 2 arctanh ∏ tanh(
𝑓(𝑛)
(𝑣𝑖, 𝑐 𝑚 )
2
)
𝑑 𝑐𝑗
𝑚=1,𝑚≠𝑖
that is possible to approximate with 𝑔(∙) operator.
It represent the optimal computation for the decoding process.
Application of the Min-sum operation
𝑓(𝑛+1)
(𝑐𝑗, 𝑣𝑖 ) = − ∏ 𝑠𝑖𝑔𝑛 (−𝑓(𝑛)
(𝑣𝑖, 𝑐 𝑚 ))
𝑑 𝑐𝑗
𝑚=1,𝑚≠𝑖
∙ min
𝑚=1,𝑚≠𝑖
|𝑓(𝑛)
(𝑣𝑖, 𝑐 𝑚 )|
In order to reduce the performance loss of Min-Sum with respect to Sum-Prod, it is
possible to apply an offset. It represent the sub-optimal computation for the decoding
process.
The belief propagation algorithm works as follows: at the first step, the check nodes' sockets
𝑓(𝑛=0)
(𝑣𝑖, 𝑐𝑗 ) are initialized to a priori LLRs on coded bits coming from the soft demodulator.
At each step the variable nodes' sockets 𝑓(𝑛)
(𝑐𝑗, 𝑣𝑖 ) are obtained, either from sum-prod or min-
sum computations, and the check nodes' sockets 𝑓(𝑛)
(𝑣𝑖, 𝑐𝑗 ) are updated.
At the end of the iterations, a posteriori LLRs are computed and hard decision is performed.
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5.2 LDPC software implementation
The software implements the block diagram that is depicted in the figure 5a. The LDPC encoder is
can be properly set by changing the input parameters in order to satisfy all the requirements of
the session. It is possible to choose among different combination of rates of code and dimension
of the code (short with N=4096, medium with N=16200 and long code with N=64800) and to
choose the operator for the decoding block in order to evaluate optimal and sub-optimal
configurations for the decoder.
The possible rates used in DVBS-2 are r = [1/4; 1/3; 2/5; 1/2; 3/5; 2/3; 3/4; 4/5; 5/6; 8/9; 9/10] and
not all of them are possible with three different code length.
Output file
Data/temp.txt
Eb/N0 [dB]
0:10:0.1
Maximum number of frames
1000
Name of file of LDPC code (or DVBS2)
DVBS2
DVB-S2 Encoder
12
Short (2), Medium (1) or long code (0)?
2
Min-sum-offset (1) or sum-prod algorithm (0)?
1
Beta for offset
3
Number of decoder iterations
50
5.3 LDPC simulation results
As requested in the assignment of this laboratory session I have provided the BER and FER curves
for LDPC codes with different rate, ¼ and 8/9, and different decoding procedure, optimal (Sum-
Prod) and sub-optimal (Min-Sum) with an arbitrary offset. By looking at the plot of the figures 5.2
and 5.3 we can observe that:
LDPC code with rate ¼ offers better performance because of the lower rate.
Sub-optimal procedure introduces a loss that decreases with the increment of the SNR
because of the better approximation of the tanh() with the sign() function.
In figure 5.4 are depicted the BER curves for LDPC codes with the application of sub-optimal
routine and more specifically is depicted the variation of curve with the variation of the offset.
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The best result has been reached for γ=4.
Finally in figure 5.5 we can observe the BER curves for LDPC codes that uses different block size: as
expected from the theoretical results, for higher block size the performance of the overall system
are better by paying the good result with the drawback of a larger latency.
Figure 5.2 – BER curves for comparison of LDPC codes with different rate and different operator for the decoding
Figure 5.3 – FER curves for comparison of LDPC codes with different rate and different operator for the decoding
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Figure 5.4 – BER curves of LDPC codes with different offset for comparison between Min-Sum and Sum-Prod
Figure 5.5 – BER curves of LDPC code for different block size
