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Computer organisation report

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32 bit MIPS processor Code for FPGA using VIVADO

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Computer organisation report

  1. 1. Summary Report on “Synthesizable ALU Design” As a part of Teacher Assessment I of Computer Organization (ENT308) Submitted by 1) RajatShukla (73) , SEM VI ,Sec A 2) Kritika Jain (10) , SEM VI ,Sec A Prof. S.R.Pandey (Course Teacher) Department of Electronics Engineering Shri Ramdeobaba College of Engineering and Management, Nagpur- 440013 (An autonomous College of Rashtrasant Tukadoji Maharaj Nagpur University) Session:2018-2019
  2. 2. 32- BIT ALU CODE FOR MIPS PROCESSOR:- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_signed.all; -- VHDL code for ALU of the MIPS Processor entity bit32 is port( a,b : in std_logic_vector(31 downto 0); -- src1, src2 alu_control : in std_logic_vector(2 downto 0); -- function select alu_result: out std_logic_vector(31 downto 0); -- ALU Output Result zero: out std_logic -- Zero Flag ); end bit32; architecture Behavioral of bit32 is signal result: std_logic_vector(31 downto 0); begin process(alu_control,a,b) begin case alu_control is when "000" => result <= a + b; -- add when "001" => result <= a - b; -- sub when "010" => result <= a and b; -- and when "011" => result <= a or b; -- or when "100"=> result<=a nor b; --nor when "101" => if (a<b) then result <= "00000000000000000000000000000001"; else result <= "00000000000000000000000000000000"; end if; when others => result <= a + b; -- add end case; end process; zero <= '1' when result=x"00000" else '0'; alu_result <= result; end Behavioral;
  3. 3. TESTBENCH:- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity tbbit32 is -- Port ( ); end tbbit32; architecture Behavioral of tbbit32 is component bit32 is port( a,b : in std_logic_vector(31 downto 0); -- src1, src2 alu_control : in std_logic_vector(2 downto 0); -- function select alu_result: out std_logic_vector(31 downto 0); -- ALU Output Result zero: out std_logic -- Zero Flag ); end component; signal a,b,alu_result: std_logic_vector(31 downto 0); signal alu_control: std_logic_vector(2 downto 0); signal zero:std_logic; signal result: std_logic_vector(31 downto 0); begin uut:bit32 port map(a,b,alu_control,alu_result,zero); process begin wait for 10ns; a<="01010101010101010101010101010101"; b<="01010101010101010101010101010101"; alu_control<="000"; wait for 10ns; a<="01010101010101010101010101010101"; b<="01010101010101010101010101010101"; alu_control<="001"; wait for 10ns; a<="01010101010101010101010101010101"; b<="01010101010101010101010101010101"; alu_control<="010"; wait for 10ns; a<="01010101010101010101010101010101"; b<="01010101010101010101010101010101"; alu_control<="011";
  4. 4. wait for 10ns; a<="01010101010101010101010101010101"; b<="01010101010101010101010101010101"; alu_control<="100"; wait for 10ns; a<="01010101010101010101010101010101"; b<="01010101010101010101010101010101"; alu_control<="101"; result<=alu_result; end process; end Behavioral; OUTPUTS:- COMBINED:
  5. 5. FOR 000: FOR 001:
  6. 6. FOR 010: FOR 011:
  7. 7. FOR 100: FOR 101:
  8. 8. ZERO: Timing Analysis: -

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