Instruction Set : Computer Architecture

R
Instruction Set : Computer Architecture
Instruction Set : Computer Architecture
Instruction Set : Computer Architecture
Instruction Set : Computer Architecture
Instruction Set : Computer Architecture
INSRTUCTION SET
Registers Control Unit ALU Memory Input/Output
An abbreviation for the
Operational Code.
The portion
of the
instruction
set that
defines or
specifies
the
operations.
Defined in first few bits
of Instruction Set
Each
OPCODE
is unique
*The number of bits defined for (or assigned to) OPCODE varies from processor to processor.
}
}
}
}
}
Opcode Final address
Mode
Initial Address
Address of operand
Large number
of operations
to be
performed
Large
instruction set
is needed
More resistors
will be used
More BUS will
be required
More memory
will be
required
More Space
requirement
Change in
Architecture
Increased cost
Compromise
in time
efficiency
RISC
• Reduced Instruction Set Computer
• Specific purpose processors use it
• Effective length of instruction set is
fixed
• Has target based applications
• Opcodes are fixed
• Higher speed
• Time efficient
• Minimum power consumption
CISC
• Complex Instruction Set Computer
• Comparatively lower speed
• General purpose processors use it
• Effective length of instruction set
varies
• Has general purpose applications
• Opcodes may vary
• Comparatively lower speed
• Comparatively lower time efficiency
• Comparatively higher power
consumption
Instruction Set : Computer Architecture
Instruction Set : Computer Architecture
Instruction Set : Computer Architecture
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Instruction Set : Computer Architecture

  • 6. INSRTUCTION SET Registers Control Unit ALU Memory Input/Output
  • 7. An abbreviation for the Operational Code. The portion of the instruction set that defines or specifies the operations. Defined in first few bits of Instruction Set Each OPCODE is unique *The number of bits defined for (or assigned to) OPCODE varies from processor to processor.
  • 8. } } } } } Opcode Final address Mode Initial Address Address of operand
  • 9. Large number of operations to be performed Large instruction set is needed More resistors will be used More BUS will be required More memory will be required More Space requirement Change in Architecture Increased cost Compromise in time efficiency
  • 10. RISC • Reduced Instruction Set Computer • Specific purpose processors use it • Effective length of instruction set is fixed • Has target based applications • Opcodes are fixed • Higher speed • Time efficient • Minimum power consumption CISC • Complex Instruction Set Computer • Comparatively lower speed • General purpose processors use it • Effective length of instruction set varies • Has general purpose applications • Opcodes may vary • Comparatively lower speed • Comparatively lower time efficiency • Comparatively higher power consumption