More Related Content Similar to Open Hardware PowerPC Notebook motherboard V.0.6 August 2020 (20) More from Roberto Innocenti (7) Open Hardware PowerPC Notebook motherboard V.0.6 August 20201. 1
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A A
B B
C C
D D
Version Control
Version
V0.1
Date
2018/12
Modifications
First release of Schematics
Page Description
1 SCHEMATIC PAGE LISTING
2
3
SYSTEM BLOCK DIAGRAM
4
5
6
7
8
9
10
11
12
13
14
15
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18
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20
21
22
23
24
25
26
27
28
29
30
T2080 FIRST BANK DDR3L INTERFACE
31
32
T2080 IFC INTERFACE
T2080 NOR and NAND FLASH INTERFACE
T2080 SPI FLASH and SDHC INTERFACE
T2080 SYSTEM LOGIC INTERFACE
T2080 ETHERNET and SERDES INTERFACE
T2080 USB INTERFACE
33
ACB_0001_0
SYSTEM POWER INPUT
T2080 CORE POWER CONVERTOR
SYSTEM CLOCK GENERATORs (cont.)
MECHANICALs
SYSTEM POWER CONVERTORs
CPLD WRAPPER AND IO EXPANDER
CHANGE LIST
SYSTEM POWER CONVERTORs (cont.)
SYSTEM CLOCK GENERATORs
RGMII ETHERNET PORT 1
KEYBOARD INTERFACE
KB_LED_AND_LED
T2080 DUART and I2C DEVICE INTERFACE
T2080 GROUND
T2080 POWER SUPPLY (cont.)
T2080 POWER SUPPLY
ETHERNET PORT CONNECTOR
SATA3 CONTROLLER
SATA3 CONNECTORS
USB3 CONTROLLER CONNECTORS
USB3 CONTROLLER
PCIE CONNECTORS
PCIE BRIDGE
3G LTE MODEM
PCIE BRIDGE POWER
MXM PCIE
MXM VIDEO OUT
I2C WRAPPER
AUDIO CMEDIA
AUDIO CONNECTORS
MAIN POWER
BATTERY CHARGER
34
35
36
37
38
39
40
41
V0.2 2019/09 Second release of Schematics
T2080 SECOND BANK DDR3L INTERFACE
42
43
USB_HUB V0.3 2020/04 Third release of Schematics
44
ETHERNET CARD
V0.5
2020/05 Fourth release of Schematics
2020/06
V0.4
Fifth release of Schematics
V0.6 2020/08 Sixth release of Schematics
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PAGE LISTING
0 B1 45
Monday, September 28, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PAGE LISTING
0 B1 45
Monday, September 28, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PAGE LISTING
0 B1 45
Monday, September 28, 2020
<Variant Name>
2. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
SYSTEM BLOCK DIAGRAM
ACB_0001_0Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
BLOCK DIAGRAM
0 A02 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
BLOCK DIAGRAM
0 A02 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
BLOCK DIAGRAM
0 A02 45
Monday, August 10, 2020
<Variant Name>
3. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
T2080 DDR3L MEMORY INTERFACE
1.35V DDR3L SDRAM SODIMM
4GB (x64, DDR3L)
SPD ADDR = 0x51
1G6 For DDR3L-1600
T2080 REV 1.0: 187 ohm
3V3
1V35
1V35
MVREF
1V35
1V35
1V35 VTT MVREF
1V35
3V3
VTT
MVREF
DDR_RST_N4,15
DDR_REFCLK 35
DDR_MBA[0..2]4
DDR_MA[0..15]4
DDR_MWE_N4
DDR_MCS2_N4
DDR_MCS3_N4
DDR_MCK2_P4
DDR_MCK2_N4
DDR_MCK3_P4
DDR_MCK3_N4
DDR_MCKE24
DDR_MCKE34
DDR_MCRAS_N4
DDR_MRAS_N4
DDR_MDM[0..8]4
DDR_DQ[0..63]4
DDR_MDQS0_P4
DDR_MDQS0_N4
DDR_MDQS1_P4
DDR_MDQS1_N4
DDR_MDQS2_P4
DDR_MDQS2_N4
DDR_MDQS3_P4
DDR_MDQS3_N4
DDR_MDQS4_P4
DDR_MDQS4_N4
DDR_MDQS5_P4
DDR_MDQS5_N4
DDR_MDQS6_P4
DDR_MDQS6_N4
DDR_MDQS7_P4
DDR_MDQS7_N4
I2C_DDR3_1_SCL32
I2C_DDR3_1_SDA32
DDR_MODT24
DDR_MODT34
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
3 45
Monday, August 10, 2020Saturday, April 20, 2013
A30
DDR3
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
3 45
Monday, August 10, 2020Saturday, April 20, 2013
A30
DDR3
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
3 45
Monday, August 10, 2020Saturday, April 20, 2013
A30
DDR3
<Author> <Approved by><Cheked by>
<Variant Name>
TP8
M1
MT8KTF51264HZ-1G6
C10
100NF
C22
100NF
C8
100NF
C15
100NF
TP9
C12
100NF
C16
100NF
TP10
R3
187
C18
100NF
TP11
C7
100NF
R4
187
C23
100NF
CONN204_DDR3_SODIMM
NC
NC
VTT
VTT
VREFCA
VREF/DQ
VDDSPD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J3F1B
2 OF 2
CONN
E85705-003
1
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
75
76
77
81
82
87
88
93
94
99
100
105
106
111
112
117
118
122
123
124
126
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
199
203
204
C11
100NF
C19
100NF
TP2
C20
100NF
C6
100NF
TP3
R2
1K
TP7
C21
100NF
TP4
CONN204_DDR3_SODIMM
A<12>/BC_N
A<14>
A<13>
A<11>
A<15>/BA3
A<10>/AP
A<3>/A4
A<4>/A3
A<2>
A<9>
A<1>
A<8>/A7
A<7>/A8
A<6>/A5
A<5>/A6
A<0>
CK0P
S0_N
S1_N
BA0/BA1
BA1/BA0
CK0N
BA2
CKE1
CKE0
CAS_N
RAS_N
RST_N
CK1P
CK1N
WE_N
ODT1
ODT0
SCL
SA1
SA0
SDA
DQS0P
DM0
DM1
DM2
DM3
DM4
DM5
DM7
DM6
DQS0N
DQS4N
DQS4P
DQS1P
DQS5P
DQS1N
DQS2P
DQS2N
DQS3P
DQS3N
DQS5N
DQS6P
DQS6N
DQS7P
DQS7N
DQ<63>
DQ<62>
DQ<61>
DQ<59>
DQ<60>
DQ<58>
DQ<54>
DQ<53>
DQ<57>
DQ<56>
DQ<55>
DQ<52>
DQ<49>
DQ<50>
DQ<51>
DQ<48>
DQ<47>
DQ<46>
DQ<43>
DQ<40>
DQ<39>
DQ<41>
DQ<42>
DQ<44>
DQ<45>
DQ<38>
DQ<30>
DQ<29>
DQ<37>
DQ<36>
DQ<35>
DQ<34>
DQ<33>
DQ<32>
DQ<31>
DQ<28>
DQ<18>
DQ<19>
DQ<22>
DQ<23>
DQ<21>
DQ<20>
DQ<24>
DQ<27>
DQ<26>
DQ<25>
DQ<14>
DQ<15>
DQ<16>
DQ<12>
DQ<11>
DQ<10>
DQ<8>
DQ<9>
DQ<13>
DQ<17>
DQ<7>
DQ<6>
DQ<5>
DQ<4>
DQ<3>
DQ<2>
DQ<1>
DQ<0>
EVENT_N
TEST
J3F1A
1 OF 2
CONN
E85705-003
4
5
6
7
10
11
12
15
16
17
18
21
22
23
24
27
28
29
30
33
34
35
36
39
40
41
42
45
46
47
50
51
52
53
56
57
58
59
62
63
64
67
68
69
70
73
74
78
79
80
83
84
85
86
89
90
91
92
95
96
97
98
101
102
103
104
107
108
109
110
113
114
115
116
119
120
121
125
129
130
131
132
135
136
137
140
141
142
143
146
147
148
149
152
153
154
157
158
159
160
163
164
165
166
169
170
171
174
175
176
177
180
181
182
183
186
187
188
191
192
193
194
197
198
200
201
202
C13
100NF
TP6
C9
100NF
TP5
C3
22uF
C5
100NF
C17
100NF
DDR1
(G1VDD)
OVDD
G1VDD/2
U1I
T2080NXN8PTB
D1_MDQ00
B24
D1_MDQ01
A24
D1_MDQ02
C25
D1_MDQ03
D24
D1_MDQ04
D25
D1_MDQ05
C26
D1_MDQ06
B27
D1_MDQ07
C27
D1_MDQ08
H23
D1_MDQ09
G23
D1_MDQ10
F24
D1_MDQ11
F25
D1_MDQ12
E25
D1_MDQ13
E26
D1_MDQ14
D27
D1_MDQ15
G25
D1_MDQ16
J23
D1_MDQ17
H24
D1_MDQ18
H25
D1_MDQ19
J26
D1_MDQ20
J25
D1_MDQ21
J27
D1_MDQ22
H28
D1_MDQ23
K28
D1_MDQ24
L23
D1_MDQ25
M25
D1_MDQ26
K24
D1_MDQ27
K27
D1_MDQ28
M24
D1_MDQ29
L27
D1_MDQ30
M27
D1_MDQ31
M28
D1_MDQ32
T27
D1_MDQ33
V27
D1_MDQ34
U25
D1_MDQ35
U26
D1_MDQ36
R25
D1_MDQ37
T25
D1_MDQ38
T24
D1_MDQ39
U23
D1_MDQ40
Y28
D1_MDQ41
Y27
D1_MDQ42
Y25
D1_MDQ43
Y24
D1_MDQ44
V25
D1_MDQ45
Y23
D1_MDQ46
V24
D1_MDQ47
W23
D1_MDQ48
AA27
D1_MDQ49
AB28
D1_MDQ50
AB27
D1_MDQ51
AC27
D1_MDQ52
AB24
D1_MDQ53
AB23
D1_MDQ54
AA23
D1_MDQ55
AA25
D1_MDQ56
AD28
D1_MDQ57
AD27
D1_MDQ58
AE27
D1_MDQ59
AC25
D1_MDQ60
AF28
D1_MDQ61
AF27
D1_MDQ62
AG27
D1_MDQ63
AE26
D1_MECC0
N25
D1_MECC1
N23
D1_MECC2
N26
D1_MECC3
N27
D1_MECC4
R27
D1_MECC5
R26
D1_MECC6
R23
D1_MECC7
P24
D1_MAPAR_ERR_B
E30
D1_MAPAR_OUT
AA30
D1_MDM0
A25
D1_MDM1
E27
D1_MDM2
G26
D1_MDM3
K25
D1_MDM4
T28
D1_MDM5
W25
D1_MDM6
AA26
D1_MDM7
AJ27
D1_MDM8
P25
D1_MDQS0
A26
D1_MDQS1
F28
D1_MDQS2
G27
D1_MDQS3
L26
D1_MDQS4
V28
D1_MDQS5
W27
D1_MDQS6
AB25
D1_MDQS7
AH26
D1_MDQS8
P27
D1_MBA0
AC30
D1_MBA1
AA29
D1_MBA2
D28
D1_MA00
Y30
D1_MA01
W29
D1_MA02
M30
D1_MA03
L30
D1_MA04
L29
D1_MA05
J30
D1_MA06
J29
D1_MA07
G29
D1_MA08
H30
D1_MA09
F30
D1_MA10
AB30
D1_MA11
G30
D1_MA12
E29
D1_MA13
AG29
D1_MA14
D30
D1_MA15
C29
D1_MCS0_B
AD30
D1_MCS1_B
AH30
D1_MCS2_B
AK28
D1_MCS3_B
AJ28
D1_MCKE0
B29
D1_MCKE1
B28
D1_MCKE2
C30
D1_MCKE3
A28
D1_MCK0
P30
D1_MCK1
R30
D1_MCK2
U29
D1_MCK3
W30
D1_MCK0_B
N30
D1_MCK1_B
R29
D1_MCK2_B
U30
D1_MCK3_B
V30
D1_MODT0
AG30
D1_MODT1
AH29
D1_MODT2
AF30
D1_MODT3
AJ29
D1_MDIC0
K30D1_MDIC1
N29
D1_MCAS_B
AE29
D1_MDQS0_B
B25
D1_MDQS1_B
F27
D1_MDQS2_B
H27
D1_MDQS3_B
L25
D1_MDQS4_B
U27
D1_MDQS5_B
W26
D1_MDQS6_B
AC26
D1_MDQS7_B
AH27
D1_MDQS8_B
P28
D1_MRAS_B
AC29
D1_MWE_B
AE30
D1_MVREF
F21
D1_DDRCLK
E23
D1_TPA
C23
C1
100NF
C2
22uF
C4
22uF
R1
4,7K
TP1
C14
100NF
DDR_MCK0_P
DDR_MCK0_N
DDR_MCK1_P
DDR_MCK1_N
DDR_MBA0
DDR_MBA1
DDR_MBA2
DDR_MDQS0_P
DDR_MDQS1_P
DDR_MDQS2_P
DDR_MDQS3_P
DDR_MDQS5_P
DDR_MDQS4_P
DDR_MDQS6_P
DDR_MDQS7_P
DDR_MDQS0_N
DDR_MDQS1_N
DDR_MDQS2_N
DDR_MDQS3_N
DDR_MDQS5_N
DDR_MDQS7_N
DDR_MDQS6_N
DDR_MDQS4_N
DDR_MCS0_N
DDR_MCS1_N
DDR_MCRAS_N
DDR_MRAS_N
DDR_MWE_N
DDR_MDM0
DDR_MDM1
DDR_MDM2
DDR_MDM3
DDR_MDM4
DDR_MDM5
DDR_MDM6
DDR_MDM7
DDR_MCKE0
DDR_MCKE1
DDR_MODT0
DDR_MODT1
DDR_MA[0..15]
DDR_MDM[0..8]
DDR_MBA[0..2]
DDR_MCK1_P
DDR_MCK1_N
DDR_MCK0_P
DDR_MCK0_N
DDR_MDQS0_P
DDR_MDQS1_P
DDR_MDQS2_P
DDR_MDQS3_P
DDR_MDQS5_P
DDR_MDQS4_P
DDR_MDQS6_P
DDR_MDQS7_P
DDR_MDQS8_P
DDR_MDQS0_N
DDR_MDQS1_N
DDR_MDQS2_N
DDR_MDQS3_N
DDR_MDQS5_N
DDR_MDQS7_N
DDR_MDQS6_N
DDR_MDQS4_N
DDR_MDQS8_N
DDR_MBA0
DDR_MBA1
DDR_MBA2
DDR_MA0
DDR_MA1
DDR_MA2
DDR_MA3
DDR_MA4
DDR_MA5
DDR_MA6
DDR_MA7
DDR_MA8
DDR_MA9
DDR_MA10
DDR_MA11
DDR_MA12
DDR_MA13
DDR_MA14
DDR_MA15
DDR_MDM0
DDR_MDM1
DDR_MDM2
DDR_MDM3
DDR_MDM4
DDR_MDM5
DDR_MDM6
DDR_MDM7
DDR_MDM8
DDR_MCKE0
DDR_MCKE1
DDR_MDM[0..8]
DDR_MBA[0..2]
DDR_MA[0..15]
DDR_MCS0_N
DDR_MCS1_N
DDR_MODT0
DDR_MODT1
DDR_MRAS_N
DDR_MCRAS_N
DDR_MWE_N
DDR_ECC0
DDR_ECC1
DDR_ECC2
DDR_ECC3
DDR_ECC4
DDR_ECC5
DDR_ECC6
DDR_ECC7
DDR_DQ0
DDR_DQ1
DDR_DQ2
DDR_DQ3
DDR_DQ4
DDR_DQ5
DDR_DQ6
DDR_DQ7
DDR_DQ8
DDR_DQ9
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31
DDR_DQ32
DDR_DQ33
DDR_DQ34
DDR_DQ35
DDR_DQ36
DDR_DQ37
DDR_DQ38
DDR_DQ39
DDR_DQ40
DDR_DQ41
DDR_DQ42
DDR_DQ43
DDR_DQ44
DDR_DQ45
DDR_DQ46
DDR_DQ47
DDR_DQ48
DDR_DQ49
DDR_DQ50
DDR_DQ51
DDR_DQ52
DDR_DQ53
DDR_DQ54
DDR_DQ55
DDR_DQ56
DDR_DQ57
DDR_DQ58
DDR_DQ59
DDR_DQ60
DDR_DQ61
DDR_DQ62
DDR_DQ63
DDR_DQ[0..63]
DDR_DQ62
DDR_DQ63
DDR_DQ60
DDR_DQ61
DDR_DQ58
DDR_DQ59
DDR_DQ56
DDR_DQ57
DDR_DQ54
DDR_DQ55
DDR_DQ52
DDR_DQ53
DDR_DQ50
DDR_DQ51
DDR_DQ48
DDR_DQ49
DDR_DQ46
DDR_DQ47
DDR_DQ44
DDR_DQ45
DDR_DQ42
DDR_DQ43
DDR_DQ40
DDR_DQ41
DDR_DQ38
DDR_DQ39
DDR_DQ36
DDR_DQ37
DDR_DQ34
DDR_DQ35
DDR_DQ32
DDR_DQ33
DDR_DQ30
DDR_DQ31
DDR_DQ28
DDR_DQ29
DDR_DQ26
DDR_DQ27
DDR_DQ24
DDR_DQ25
DDR_DQ22
DDR_DQ23
DDR_DQ20
DDR_DQ21
DDR_DQ18
DDR_DQ19
DDR_DQ16
DDR_DQ17
DDR_DQ14
DDR_DQ15
DDR_DQ12
DDR_DQ13
DDR_DQ10
DDR_DQ11
DDR_DQ8
DDR_DQ9
DDR_DQ6
DDR_DQ7
DDR_DQ4
DDR_DQ5
DDR_DQ2
DDR_DQ3
DDR_DQ0
DDR_DQ1
DDR_DQ[0..63]
DDR_MA0
DDR_MA1
DDR_MA2
DDR_MA3
DDR_MA4
DDR_MA5
DDR_MA6
DDR_MA7
DDR_MA8
DDR_MA9
DDR_MA10
DDR_MA11
DDR_MA12
DDR_MA13
DDR_MA14
DDR_MA15
DDR_MDM8
DDR_MDQS8_P
DDR_MDQS8_N
DDR_MCS2_N
DDR_MCS3_N
DDR_MCKE2
DDR_MCKE3
DDR_MCK2_P
DDR_MCK2_N
DDR_MCK3_P
DDR_MCK3_N
DDR_MODT2
DDR_MODT3
DDR_MDM[0..8]
DDR_MBA[0..2]
DDR_MA[0..15]
DDR_MCS2_N
DDR_MCS3_N
DDR_MCKE2
DDR_MCKE3
DDR_MCK2_P
DDR_MCK2_N
DDR_MCK3_P
DDR_MCK3_N
DDR_DQ[0..63]
DDR_MCRAS_N
DDR_MRAS_N
DDR_MWE_N
DDR_MDQS0_P
DDR_MDQS0_N
DDR_MDQS1_P
DDR_MDQS1_N
DDR_MDQS2_P
DDR_MDQS2_N
DDR_MDQS3_P
DDR_MDQS3_N
DDR_MDQS4_P
DDR_MDQS4_N
DDR_MDQS5_P
DDR_MDQS5_N
DDR_MDQS6_P
DDR_MDQS6_N
DDR_MDQS7_P
DDR_MDQS7_N
DDR_MODT2
DDR_MODT3
4. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
SPD ADDR = 0x52
4GB (x64, DDR3L)
1.35V DDR3L SDRAM SODIMM 1G6 For DDR3L-1600
1V35
3V3
MVREF
VTT
1V35 VTT MVREF
1V35
1V35
3V3
DDR_RST_N3,15
DDR_MA[0..15]3
DDR_MBA[0..2]3
DDR_MCS2_N3
DDR_MCS3_N3
DDR_MCK2_P3
DDR_MCK2_N3
DDR_MCK3_P3
DDR_MCK3_N3
DDR_MCKE23
DDR_MCKE33
DDR_MCRAS_N3
DDR_MRAS_N3
DDR_MWE_N3
DDR_MDM[0..8]3
DDR_DQ[0..63] 3
DDR_MDQS0_P3
DDR_MDQS0_N3
DDR_MDQS1_P3
DDR_MDQS1_N3
DDR_MDQS2_P3
DDR_MDQS2_N3
DDR_MDQS3_P3
DDR_MDQS3_N3
DDR_MDQS4_P3
DDR_MDQS4_N3
DDR_MDQS5_P3
DDR_MDQS5_N3
DDR_MDQS6_P3
DDR_MDQS6_N3
DDR_MDQS7_P3
DDR_MDQS7_N3
I2C_DDR3_2_SCL32
I2C_DDR3_2_SDA32
DDR_MODT23
DDR_MODT33
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
4 45
Monday, August 10, 2020Sunday, September 22, 2019
A30
DDR3_2
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
4 45
Monday, August 10, 2020Sunday, September 22, 2019
A30
DDR3_2
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
4 45
Monday, August 10, 2020Sunday, September 22, 2019
A30
DDR3_2
<Author> <Approved by><Cheked by>
<Variant Name>
R5
1K
C45
100NF
C26
22uF
C27
22uF
C28
100NF
C29
100NF
C30
100NF
M2
MT8KTF51264HZ-1G6
C32
100NF
C31
100NF
C33
100NF
C39
100NF
C34
100NF
CONN204_DDR3_SODIMM
NC
NC
VTT
VTT
VREFCA
VREF/DQ
VDDSPD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J3F2B
2 OF 2
CONN
E85705-003
1
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
75
76
77
81
82
87
88
93
94
99
100
105
106
111
112
117
118
122
123
124
126
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
199
203
204
C40
100NF
C35
100NF
C41
100NF
CONN204_DDR3_SODIMM
A<12>/BC_N
A<14>
A<13>
A<11>
A<15>/BA3
A<10>/AP
A<3>/A4
A<4>/A3
A<2>
A<9>
A<1>
A<8>/A7
A<7>/A8
A<6>/A5
A<5>/A6
A<0>
CK0P
S0_N
S1_N
BA0/BA1
BA1/BA0
CK0N
BA2
CKE1
CKE0
CAS_N
RAS_N
RST_N
CK1P
CK1N
WE_N
ODT1
ODT0
SCL
SA1
SA0
SDA
DQS0P
DM0
DM1
DM2
DM3
DM4
DM5
DM7
DM6
DQS0N
DQS4N
DQS4P
DQS1P
DQS5P
DQS1N
DQS2P
DQS2N
DQS3P
DQS3N
DQS5N
DQS6P
DQS6N
DQS7P
DQS7N
DQ<63>
DQ<62>
DQ<61>
DQ<59>
DQ<60>
DQ<58>
DQ<54>
DQ<53>
DQ<57>
DQ<56>
DQ<55>
DQ<52>
DQ<49>
DQ<50>
DQ<51>
DQ<48>
DQ<47>
DQ<46>
DQ<43>
DQ<40>
DQ<39>
DQ<41>
DQ<42>
DQ<44>
DQ<45>
DQ<38>
DQ<30>
DQ<29>
DQ<37>
DQ<36>
DQ<35>
DQ<34>
DQ<33>
DQ<32>
DQ<31>
DQ<28>
DQ<18>
DQ<19>
DQ<22>
DQ<23>
DQ<21>
DQ<20>
DQ<24>
DQ<27>
DQ<26>
DQ<25>
DQ<14>
DQ<15>
DQ<16>
DQ<12>
DQ<11>
DQ<10>
DQ<8>
DQ<9>
DQ<13>
DQ<17>
DQ<7>
DQ<6>
DQ<5>
DQ<4>
DQ<3>
DQ<2>
DQ<1>
DQ<0>
EVENT_N
TEST
J3F2A
1 OF 2
CONN
E85705-003
4
5
6
7
10
11
12
15
16
17
18
21
22
23
24
27
28
29
30
33
34
35
36
39
40
41
42
45
46
47
50
51
52
53
56
57
58
59
62
63
64
67
68
69
70
73
74
78
79
80
83
84
85
86
89
90
91
92
95
96
97
98
101
102
103
104
107
108
109
110
113
114
115
116
119
120
121
125
129
130
131
132
135
136
137
140
141
142
143
146
147
148
149
152
153
154
157
158
159
160
163
164
165
166
169
170
171
174
175
176
177
180
181
182
183
186
187
188
191
192
193
194
197
198
200
201
202
C36
100NF
C42
100NF
C37
100NF
C43
100NF
C38
100NF
C24
100NF
C44
100NF
C25
22uF
DDR_MA[0..15] DDR_DQ[0..63]
DDR_MA15 DDR_DQ63
DDR_MA14 DDR_DQ62
DDR_MA13 DDR_DQ61
DDR_MA12 DDR_DQ60
DDR_MA11 DDR_DQ59
DDR_MA10 DDR_DQ58
DDR_MA9 DDR_DQ57
DDR_MA8 DDR_DQ56
DDR_MA7 DDR_DQ55
DDR_MA6 DDR_DQ54
DDR_MA5 DDR_DQ53
DDR_MA4 DDR_DQ52
DDR_MA3 DDR_DQ51
DDR_MA2 DDR_DQ50
DDR_MA1 DDR_DQ49
DDR_MA0 DDR_DQ48
DDR_MBA[0..2] DDR_DQ47
DDR_MBA0 DDR_DQ46
DDR_MBA1 DDR_DQ45
DDR_MBA2 DDR_DQ44
DDR_DQ43
DDR_DQ42
DDR_DQ41
DDR_DQ40
DDR_DQ39
DDR_DQ38
DDR_DQ37
DDR_DQ36
DDR_DQ35
DDR_DQ34
DDR_DQ33
DDR_DQ32
DDR_MCRAS_N DDR_DQ31
DDR_MRAS_N DDR_DQ30
DDR_DQ29
DDR_MWE_N DDR_DQ28
DDR_DQ27
DDR_DQ26
DDR_DQ25
DDR_DQ24
DDR_DQ23
DDR_DQ22
DDR_DQ21
DDR_DQ20
DDR_DQ19
DDR_MDM[0..8] DDR_DQ18
DDR_MDM0 DDR_DQ17
DDR_MDM1 DDR_DQ16
DDR_MDM2 DDR_DQ15
DDR_MDM3 DDR_DQ14
DDR_MDM4 DDR_DQ13
DDR_MDM5 DDR_DQ12
DDR_MDM6 DDR_DQ11
DDR_MDM7 DDR_DQ10
DDR_DQ9
DDR_MDQS0_P DDR_DQ8
DDR_MDQS0_N DDR_DQ7
DDR_MDQS1_P DDR_DQ6
DDR_MDQS1_N DDR_DQ5
DDR_MDQS2_P DDR_DQ4
DDR_MDQS2_N DDR_DQ3
DDR_MDQS3_P DDR_DQ2
DDR_MDQS3_N DDR_DQ1
DDR_MDQS4_P DDR_DQ0
DDR_MDQS4_N
DDR_MDQS5_P
DDR_MDQS5_N
DDR_MDQS6_P
DDR_MDQS6_N
DDR_MDQS7_P
DDR_MDQS7_N
DDR_MCS2_N
DDR_MCS3_N
DDR_MCKE2
DDR_MCKE3
DDR_MCK2_P
DDR_MCK2_N
DDR_MCK3_P
DDR_MCK3_N
DDR_MODT2
DDR_MODT3
5. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
T2080 IFC INTERFACE
cfg_rcw_src0
cfg_rcw_src1
cfg_rcw_src2
cfg_rcw_src3
cfg_rcw_src4
cfg_rcw_src5
cfg_rcw_src6
cfg_rcw_src7
cfg_rcw_src8
cfg_ifc_te
cfg_pll_config_sel_b
cfg_por_ainit
cfg_svr0
cfg_svr1
cfg_dram_type
cfg_rsp_dis
0_0010_0111: NOR FLASH BOOT
0_0100_0000: SD CARD BOOT
0_0100_0101: SPI BOOT
1_0001_1001: NAND FLASH BOOT
For T2080 1: DDR3L
1: TE logic 0
cfg_rcw_src[0:8]
cfg_dram_type
T2080 RESET CONFIGURATION
CS0: NOR or NAND
CS1: NAND or NOR
CS2: CPLD
cfg_test_port_dis
ACB_0001_0
1V8
1V8
1V8
1V8
1V81V8
1V8
IFC_AD[0..15] 6
IFC_WE_N 6
IFC_CS0_N 15
IFC_CS1_N 15
IFC_CS2_N 15
IFC_CLE 6
IFC_OE_N 6
IFC_RB0_N 15
IFC_RB1_N 15
IFC_WP_N 6
IFC_AVD 6
IFC_NDWE_N 6
IFC_CLK 15
IFC_A[5..31] 5,6
IFC_A[5..31] 5,6
GPIO2_10 15
GPIO1_9 15
GPIO1_10 15
GPIO1_11 15
GPIO1_12 15
GPIO2_13 15
GPIO2_14 15
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
IFC
0 A35 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
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Page title
IFC
0 A35 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
IFC
0 A35 45
Monday, August 10, 2020
<Variant Name>
R47 33
U2
SN74LVC16373ADGGR
1Q1
2
1Q2
3
1Q3
5
1Q4
6
1Q5
8
1Q6
9
1Q7
11
1Q8
12
1D1
47
1D2
46
1D3
44
1D4
43
1D5
41
1D6
40
1D7
38
1D8
37
2D1
36
2D2
35
2D3
33
2D4
32
2D5
30
2D6
29
2D7
27
2D8
26
LE1
48
OE1
1
LE2
25
OE2
24
2Q1
13
2Q2
14
2Q3
16
2Q4
17
2Q5
19
2Q6
20
2Q7
22
2Q8
23
GND
4
GND
10
GND
15
GND
21
GND
28
GND
45GND
39GND
34VCC
7
VCC
18
VCC
31
VCC
42
R33 4,7K
R7
4,7K
R49
10
R37 33
R20 4,7K
5
6
7
8
3
2
1
4
ON
SW2
TDA08H0SB1R
1
2
3
4
8
7
6
5
9
10
11
12
13
14
15
16
R34 4,7K
R21 20K
R48
4,7K
R40 33
R24 4,7K
R8
4,7K
R13 20K
R41 33
R36 33
C46
100NF
R11 20K
R38
4,7K
R25 4,7K
R10
4,7K
R35 33
R43 33
R9 20K
C47
100NF
R26 4,7K
R42 33
R6 20K
R17 20K
R12
4,7K
R39
4,7K
IFC
(OVDD)
U1C
T2080NXN8PTB
IFC_AD00
A13
IFC_AD01
G13
IFC_AD02
C14
IFC_AD03
D13
IFC_AD04
A15
IFC_AD05
F13
IFC_AD06
E14
IFC_AD07
J13
IFC_AD08
E13
IFC_AD09
F14
IFC_AD10
H14
IFC_AD11
A14
IFC_AD12
C13
IFC_AD13
B15
IFC_AD14
F15
IFC_AD15
D14
IFC_PAR0
F18
IFC_PAR1
A17
IFC_A16
G15
IFC_A17
C15
IFC_A18
D15
IFC_A19
G14
IFC_A20
A16
IFC_A21
B14
IFC_A22
J15
IFC_A23
B18
IFC_A24
C16
IFC_A25
E17
IFC_A26
D16
IFC_A27
G17
IFC_A28
F16
IFC_A29
G16
IFC_A30
B21
IFC_A31
E16
IFC_CS0_B
H16
IFC_CS1_B
F17
IFC_CS2_B
D19
IFC_CS3_B
B17
IFC_CS4_B
E19
IFC_CS5_B
C18
IFC_CS6_B
D21
IFC_CS7_B
G19
IFC_WE0_B
D17
IFC_BCTL
H18
IFC_AVD
C17
IFC_CLE
H19
IFC_OE_B
G18
IFC_WP0_B
A18
IFC_RB0_B
J17
IFC_PERR_B
F19
IFC_CLK0
A22
IFC_CLK1
B20
IFC_TE
A19
IFC_NDDQS
J19
IFC_NDDDR_CLK
D18
IFC_RB1_B
C19
R15 20K
R14 4,7K
R44 33
C49
100NF
TP12
R27 4,7K
R31
4,7K
R45 33
R22 20K
R23 4,7K
R28 4,7K
R16 4,7K
C48
100NF
R46 33
R29 4,7K
R30
4,7K
5
6
7
8
3
2
1
4
ON
SW1
TDA08H0SB1R
1
2
3
4
8
7
6
5
9
10
11
12
13
14
15
16
R18 4,7K
R19 20K
R32
4,7K
IFC_AD8
IFC_AD9
IFC_AD10
IFC_AD11
IFC_AD12
IFC_AD13
IFC_AD14
IFC_AD15
IFC_CLE
IFC_TE
IFC_A18
IFC_A19
IFC_A16
IFC_A17
IFC_A21
IFC_AVD
IFC_AD0
IFC_AD1
IFC_AD2
IFC_AD3
IFC_AD4
IFC_AD5
IFC_AD6
IFC_AD7
IFC_AD8
IFC_AD9
IFC_AD10
IFC_AD11
IFC_AD12
IFC_AD13
IFC_AD14
IFC_AD15
IFC_A16
IFC_A17
IFC_A18
IFC_A19
IFC_A20
IFC_A21
IFC_A22
IFC_A23
IFC_A24
IFC_A25
IFC_A26
IFC_A27
IFC_A28
IFC_A29
IFC_A30
IFC_A31
IFC_TE
IFC_AD5
IFC_AD6
IFC_AD7
IFC_AD8
IFC_AD9
IFC_AD10
IFC_AD11
IFC_AD12
IFC_AD13
IFC_AD14
IFC_AD15
IFC_A5
IFC_A6
IFC_A7
IFC_A8
IFC_A9
IFC_A10
IFC_A11
IFC_A12
IFC_A13
IFC_A14
IFC_A15
IFC_A16
IFC_A17
IFC_A18
IFC_A19
IFC_AVD
IFC_OE_N
IFC_WE_N
IFC_WP_N
IFC_A20
IFC_A31
6. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
128MB 16-BIT NOR FLASH
T2080 NOR and NAND FLASH INTERFACE
ACB_0001_0
1V8
1V8
1V8
1V8
3V3
1V8 1V8
1V8
1V8
1V8
1V8
3V31V8
1V8
1V8
1V8
1V8
IFC_A[5..31]5 IFC_AD[0..15] 5,6
NOR_CS_N15
IFC_OE_N5,6
IFC_WE_N5
NOR_RST_N15
CFG_VBANK[0..2]15
IFC_AD[0..15] 5,6
IFC_CLE5
IFC_AVD5
IFC_OE_N5,6
IFC_NDWE_N5
IFC_WP_N5
NAND_CS_N15
NAND_RB_N15
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
FLASH
0 A36 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
FLASH
0 A36 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
FLASH
0 A36 45
Monday, August 10, 2020
<Variant Name>
C50
100NF
U4
WE
18
N.C
6
VCC
37
CE
9
RE
8
N.C
20
WP
19
N.C
5
N.C
1
N.C
2
N.C
3
N.C
4
N.C
21
N.C
22
N.C
23
N.C
24
R/B
7
N.C
26
N.C
27N.C
28
I/O0
29
N.C
34N.C
35
VSS
36
PRE
38N.C
39
VCC
12
VSS
13
ALE
17
N.C
11 N.C
10
N.C
14
N.C
15
CLE
16
N.C
25
N.C
33
I/O1
30
I/O3
32I/O2
31
N.C
47
N.C
46
N.C
45
I/O7
44I/O6
43I/O5
42I/O4
41
N.C
40
N.C
48
MT28EW01GABA1HJS-0AAT
U3
A0
31
A1
26
A2
25
A3
24
A4
23
A5
22
A6
21
A7
20
A8
10
A9
9
A10
8
A11
7
A12
6
A13
5
A14
4
A15
3
A16
54
A17
19
A18
18
A19
11
A20
12
A21
15
A22
2
A23
1
A24
56
CE
32
RESET
14
VIO
29
WE
13 OE
34
BYTE
53
WP/ACC
16
A25
55
VCC
43
NC2
28NC1
27
DQ0
35
DQ1
37
DQ2
39
DQ3
41
DQ4
44
DQ5
46
DQ6
48
DQ7
50
DQ8
36
DQ9
38
DQ10
40
DQ11
42
DQ12
45
DQ13
47
DQ14
49
DQ15/A-1
51
RDY/BUSY
17
GND
33
GND
52
NC3
30
R50
4,7K
C53
100NF
R54
4,7K
U7
SN74LVC1G86DCKT
I0
1
I1
2 O
4VCC
5
GND
3
C54
100NF
R53
4,7K
R55
4,7K
U5
SN74LVC1G86DCKT
I0
1
I1
2 O
4VCC
5
GND
3
R51
4,7K
C51
100NF
R56
1K
U6
SN74LVC1G86DCKT
I0
1
I1
2 O
4VCC
5
GND
3
C57
1UF
C52
100NF
R52
4,7K
C55
100NF
C56
100NF
C59
100NF
C58
100NF
IFC_A8
IFC_A9
IFC_A10
IFC_A11
IFC_A12
IFC_A13
IFC_A14
IFC_A15
IFC_A16
IFC_A17
IFC_A18
IFC_A19
IFC_A20
IFC_A21
IFC_A22
IFC_A23
IFC_A24
IFC_A25
IFC_A26
IFC_A27
IFC_A28
IFC_A29
IFC_A30
IFC_AD0
IFC_AD1
IFC_AD2
IFC_AD3
IFC_AD4
IFC_AD5
IFC_AD6
IFC_AD7
IFC_AD8
IFC_AD9
IFC_AD10
IFC_AD11
IFC_AD12
IFC_AD13
IFC_AD14
IFC_AD15
CFG_VBANK2
IFC_A7
CFG_VBANK1
IFC_A6
CFG_VBANK0
IFC_A5
IFC_VA7
IFC_VA6
IFC_VA5
IFC_AD7
IFC_AD6
IFC_AD5
IFC_AD4
IFC_AD3
IFC_AD2
IFC_AD1
IFC_AD0
7. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
64MB SERIAL FLASH
T2080 SPI FLASH and SDHC INTERFACE
TF CARD
LABEL = TF CARD VOLTAGE
ACB_0001_0
3V3
VDD_TF
VDD_TF
3V3
VDD_TF
3V3
3V31V8
3V3 3V3 3V3
1V8 VDD_TF
1V8 3V3 1V8 VDD_TF 1V8 VDD_TF
1V8
1V8 VDD_TF
3V3
VDD_TF
1V8
1V8
1V8
1V8
GPIO2_1 15
GPIO2_2 15
GPIO2_3 15
PROC_SPI_MISO15
PROC_SPI_MOSI15
PROC_SPI_CLK15
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
SPI&SDHC
0 A37 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
SPI&SDHC
0 A37 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
SPI&SDHC
0 A37 45
Monday, August 10, 2020
<Variant Name>
R65
20K
C63
100NF
R61
33
R76 4,7K
R59
20K
C61
100NF
R69
20K
eSPI/SDHC(CVDD)
SDHC(OVDD)
U1M
T2080NXN8PTB
SPI_MOSI
C1SPI_MISO
C2
SPI_CLK
B2
SPI_CS0_B/SDHC_DAT4
E3
SPI_CS1_B/SDHC_DAT5
K6
SPI_CS2_B/SDHC_DAT6
H5
SPI_CS3_B/SDHC_DAT7
L6
SDHC_CMD
A3
SDHC_DAT0
D2
SDHC_DAT1
D3
SDHC_DAT2
H6
SDHC_DAT3
G5
SDHC_CLK
C4
SDHC_CD_B
E4
SDHC_WP
F4
R62
10
R58
20K
R75
33
R57
20K
R63 4,7K
C69
100NF
C66
100NF
C62
100NF
R73 4,7K
C65
100NF
R74 4,7K
J1
JMP 3
1
3
2
R71 4,7K
R66
20K
C68
1UF
U9
S25FL256SAGMFI000
CS
7
SO
8
WP
9
GND
10
SI
15
SCK
16
HOLD
1
VCC
2
NC1
3
NC2
4
NC3
5
NC4
6
NC5
11
NC6
12
NC7
13
NC8
14
R68
20K
U11
TXS0104E
VCCA
1
A1
2
A2
3
A3
4
A4
5
NC1
6
OE
8
GND
7
VCCB
14
B1
13
B2
12
B3
11
B4
10
NC2
9
U10
TXS0104E
VCCA
1
A1
2
A2
3
A3
4
A4
5
NC1
6
OE
8
GND
7
VCCB
14
B1
13
B2
12
B3
11
B4
10
NC2
9
R67
20K
R72 4,7K
R64
10
R60
4,7K
U8
TXS0104E
VCCA
1
A1
2
A2
3
A3
4
A4
5
NC1
6
OE
8
GND
7
VCCB
14
B1
13
B2
12
B3
11
B4
10
NC2
9
J2
10067847-001RLF
CD/DAT3
1 CMD
2 VSS1
3 VDD
4 CLK
5 VSS2
6 DAT0
7 DAT1
8
DAT2
9
WP
10 CD
11
COM
13
R70 20K
C60
1UF
U12
RCLAMP0524J.TCT
1
2
9
3
4 5
6
7
8
C67
100NF
U13
RCLAMP0524J.TCT
1
2
9
3
4 5
6
7
8
C64
100NF
PROC_SPI_MISO
PROC_SPI_MOSI
PROC_SPI_CLK
PROC_SPI_CS0_N
SDHC_CMD
SDHC_CLK
SDHC_CD_N
SDHC_DAT2
SD_D2
SD_D1
SDHC_DAT0
SDHC_DAT1
SDHC_DAT3
SDHC_WP
SD_CLK
SD_CMD
SD_D3
SD_D0
SD_CD
8. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
T2080 SYSTEM LOGIC INTERFACE
cfg_test_port_mux_sel
cfg_xvdd_sel
XVDD use 1.35V
TEST_SEL_B
FOR T2080, PULL-UP
ACB_0001_0
1V83V3
1V8 1V81V8 1V8
1V83V3
1V8
3V3 1V8
3V3
3V3 3V3
3V3 1V8
1V8
2V5 2V5 1V81V8
3V3 3V32V5 2V5 2V5 2V5
2V5
3V3 1V8
3V3 1V8
2V5
3V3
2V5 2V5
3V3
2V5
3V3
2V5 3V3 3V3
3V3 3V3
3V3
2V53V33V3
3V3
SYS_REFCLK35
IRQ08 15
IRQ09 15
IRQ00 15
IRQ01 15
IRQ02 15
RTC_INT_N 14
EC1_INT_N 19
EC1_PME_N 19
LP_TMPDET_N 43
TEMP_DIODE_P 14
TEMP_DIODE_N 14
I2C1_SCL 14,32,36,37,38
I2C1_SDA 14,32,36,37,38
I2C2_SCL 32
I2C2_SDA 32
I2C3_SCL 32
I2C3_SDA 32
I2C4_SCL32
I2C4_SDA32
PORESET_N15
HRESET_N15
RESET_REQ_N15
GPIO4_415
GPIO4_515
GPIO4_615
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
SYS
0 A38 45
Tuesday, August 11, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
SYS
0 A38 45
Tuesday, August 11, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
SYS
0 A38 45
Tuesday, August 11, 2020
<Variant Name>
R106
4,7K
R128
220K
R117
220K
R112
10K
R77
4,7K
R104
4,7K
C70
100NF
R124
0
R118 10K
C76
100NF
C82
100NF
R97
1K
R90
4,7K
R103
4,7K
C71
100NF
U15
FXLP34P5X
VCC1
1
A
2
GND
3
O
4
VCC
5
R78
4,7K
R98
1K
R126
4,7K
R109
4,7K
R91
4,7K
R130
4,7K
U18
PCA9306DCT
VREF1
2
SCL1
3
SDA1
4
GND
1
VREF2
7
SCL2
6
SDA2
5
ENABLE
8
R79
4,7K
R122 10K
R1310
R127
4,7K
R108
4,7K
CNTR & MISC
DMA(DVDD)
DEBUG
MPIC
SYSCNTR.
(OVDD)
OVDD
LVDD
DVDD
CVDD
OVDD
OVDD
VDD_LP
JTAGCLOCK
DFT
U1E
T2080NXN8PTB
DMA1_DREQ0_B
L5
DMA1_DACK0_B
E1
DMA1_DDONE0_B
K5
DMA2_DREQ0_B
F3
DMA2_DACK0_B/EVT_B7
H1
DMA2_DDONE0_B/EVT_B8
G3
IRQ00
G11
IRQ01
E11
IRQ02
D10
IRQ03/SDHC_VS
C10
IRQ04
H12
IRQ05
D11
IRQ06
P5
IRQ07
P3
IRQ08
P6
IRQ09
P4
IRQ10/SDHC_SYNC_IN
J5
IRQ11
D1
IRQ_OUT_B/EVT_B9
C12
TMP_DETECT_B
C21
PORESET_B
F10
HRESET_B
F11
RESET_REQ_B
D12
CKSTP_OUT_B
D20
ASLEEP
A11
SYSCLK
A10
RTC
A20
EVT0_B
A12
EVT1_B
B12
EVT2_B
G12
EVT3_B
C11
EVT4_B
F12
CLK_OUT
E10
SCAN_MODE_B
H11
TEST_SEL_B
C9
TDI
D22
TMS
A21
TCK
C20
TDO
E20
TRST_B
B22
TD1_ANODE
K22
TD1_CATHODE
J21
LP_TMP_DETECT_B
R7
R129
4,7K
C78
100NF
R95
4,7K
U19
PCA9306DCT
VREF1
2
SCL1
3
SDA1
4
GND
1
VREF2
7
SCL2
6
SDA2
5
ENABLE
8
R88
4,7K
R110
10
C72
100NF
R116
4,7K
C77
100NF
R81
4,7K
R85
4,7K
U20
PCA9306DCT
VREF1
2
SCL1
3
SDA1
4
GND
1
VREF2
7
SCL2
6
SDA2
5
ENABLE
8
R123
0
R105
4,7K
R92
4,7K
R120
4,7K
R84
4,7K
R107
4,7K
R101
220K
C73
100NF TP14
R89
4,7K
R119
4,7K
R102
0
R121
4,7K
C74
100NF
R96
510
R93
4,7K
C83
100NF
R86
4,7K
R94
4,7K
R111
10K
R100
4,7K
C79
100NF
R80
4,7K
R87
4,7K
R125
220K
R99
10K
R114 10K
U14
FXLP34P5X
VCC1
1
A
2
GND
3
O
4
VCC
5
U17
PCA9306DCT
VREF1
2
SCL1
3
SDA1
4
GND
1
VREF2
7
SCL2
6
SDA2
5
ENABLE
8
C81
100NF
R83
4,7K
R82
4,7K
TP13
U16
TXS0104E
VCCA
1
A1
2
A2
3
A3
4
A4
5
NC1
6
OE
8
GND
7
VCCB
14
B1
13
B2
12
B3
11
B4
10
NC2
9
R113
10K
C80
100NF
D1
LED VERDE
R115 10K
C75
100NF
J3
STRIP 16
21
3
5
7
9
11
13
15
4
6
8
10
12
14
16
I2C(DVDD)
U1D
T2080NXN8PTB
IIC1_SCL
H3
IIC1_SDA
G2
IIC2_SCL
H4
IIC2_SDA
K2
IIC4_SCL/EVT_B5
K1
IIC4_SDA/EVT_B6
M1
IIC3_SCL
J6
IIC3_SDA
J2
ASLEEP
CKSTP_OUT_N
COP_TDO
COP_CKSTP_OUT_N
COP_TMS
COP_TCK
COP_TDI
JTAG_TRST_N
JTAG_TRST_N
JTAG_TMS
JTAG_TDO
JTAG_TCK
JTAG_TDI
9. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
T2080 ETHERNET and SERDES INTERFACE
EC1&EC2 OPERATE AT 2.5V EXCEPT EMI2 OPERATES AT 1.8V
LVPECL INPUT and OUTPUT
ACB_0001_0
CONF SERDES2 0X1F
CONF SERDES1 0XAA
SATA PCIE
MXM PCIE
BRIDGE PCIE
BRIDGE PCIE
MXM PCIE
M2 PCIE
M2 PCIE PCIE_1 X4
PCIE_4 X4
PCIE_3 X4
PCIE_2 X2
PCIE3 = x4 Gen2 PCIe Bridge
PCIE4 = x4 Gen3 MXM slot
PCIE1 = x4 Gen3 M.2 ssd slot
PCIE2 = x4 Gen2 Marvell SATA (only using x2 lanes)
2V5
XVDDSVDD
XVDDSVDD
3V3
3V3
EC1_TXCTL 19
EC1_GTXCLK 19
EC1_RXD[0..3] 19
EC1_RXCTL 19
EC1_RXCLK 19
EC1_REFCLK 19
EC1_TXD[0..3] 19
PEX_CLK_P36
PEX_CLK_N36
GPIO3_24 15
GPIO3_25 15
GPIO3_26 15
GPIO3_27 15
GPIO3_28 15
GPIO3_29 15
GPIO3_30 15
GPIO3_31 15
GPIO4_29 15
GPIO4_27 15
GPIO4_28 15
GPIO4_30 15
GPIO4_31 15
EMI1_MDC 19
EMI1_MDIO 19
SATA_PCIE_RX0P21
SATA_PCIE_RX0N21
SATA_PCIE_RX1P21
SATA_PCIE_RX1N21
BRIDGE_RXP026
BRIDGE_RXN026
BRIDGE_TXP0 26
BRIDGE_TXN0 26
MXM_PERN330
MXM_PERP330
MXM_PERN230
MXM_PERP230
MXM_PERP130
MXM_PERN130
MXM_PERN030
MXM_PERP030
M2_PERP022
M2_PERN022
M2_PERN122
M2_PERP122
M2_PERP222
M2_PERN222
M2_PERP322
M2_PERN322
MXM_PETP0 30
MXM_PETN0 30
MXM_PETP1 30
MXM_PETN1 30
MXM_PETP2 30
MXM_PETN2 30
MXM_PETP3 30
MXM_PETN3 30
M2_PETP0 22
M2_PETN0 22
M2_PETP1 22
M2_PETN1 22
M2_PETP2 22
M2_PETN2 22
M2_PETP3 22
M2_PETN3 22
SATA_PCIE_TX0P 21
SATA_PCIE_TX0N 21
SATA_PCIE_TX1P 21
SATA_PCIE_TX1N 21
BRIDGE_RXP126
BRIDGE_RXP226
BRIDGE_RXP326
BRIDGE_RXN126
BRIDGE_RXN226
BRIDGE_RXN326
BRIDGE_TXP1 26
BRIDGE_TXP2 26
BRIDGE_TXP3 26
BRIDGE_TXN1 26
BRIDGE_TXN2 26
BRIDGE_TXN3 26
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
EC&SD
0 A39 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
EC&SD
0 A39 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
EC&SD
0 A39 45
Monday, August 10, 2020
<Variant Name>
C101 100NF
C98 100NF
R135
1K
R148 0
R137
10
R134
10
R140 0
C90 100NF
R143 0
C96 100NF
R166
200
R153 0
L1
BLM18EG601SN1
C118 100NF
R151 0
R169 150R
C113
100NF
C94 100NF
C120
100NF
C112 100NF
C110 100NF
R172 130
C87 100NF
C108 100NF
R164 150R
R142 0
R163 82R
R133
10
R158
4,7K
R146
200
C106 100NF
C84 100NF
R165
698R
R145 0
R155 0
C104 100NF
R150 0 C102 100NF
C115
100NF
C99 100NF
R149 0
C89 100NF
C91
10PF
C114
100NF
C97 100NF
C95 100NF
R138
10
C119
100NF
C92 100NF
R144 0
C117 100NF
R168 150R
C93 100NF
ETH.CNTR(RGMII)1ETH.CNTR(RGMII)2
LVDD
ETH MII2
(1V2)
ETH MII1
(LVDD)
U1B
T2080NXN8PTB
EC1_GTX_CLK125
M2
EC2_GTX_CLK125
V1
EC1_TXD0
T6
EC1_TXD1
N1
EC1_TXD2
N2
EC1_TXD3
R4
EC1_TX_CTL
M3
EC1_GTX_CLK
P1
EC1_RXD0
R5
EC1_RXD1
N5
EC1_RXD2
N6
EC1_RXD3
L1
EC1_RX_CTL
L3
EC1_RX_CLK
M4
EC2_TXD0
W6
EC2_TXD1
U5
EC2_TXD2
U3
EC2_TXD3
V5
EC2_TX_CTL
R3
EC2_GTX_CLK
T1
EC2_RXD0
R1
EC2_RXD1
T2
EC2_RXD2
U4
EC2_RXD3
R2
EC2_RX_CTL
U6
EC2_RX_CLK
V6
EMI2_MDC
B3
EMI2_MDIO
F5
EMI1_MDC
T5
EMI1_MDIO
N3
SERDES 2
X2VDD
S2VDD
X2VDD
S2VDD
S2VDD
U1L
T2080NXN8PTB
SD2_TX0_P
AB2
SD2_TX0_N
AB1
SD2_TX1_P
AB5
SD2_TX1_N
AB6
SD2_TX2_P
AF1
SD2_TX2_N
AF2
SD2_TX3_P
AH1
SD2_TX3_N
AH2
SD2_TX4_P
AF5
SD2_TX4_N
AG5
SD2_TX5_P
AG6
SD2_TX5_N
AF6
SD2_TX6_P
AF8
SD2_TX6_N
AG8
SD2_TX7_P
AG9
SD2_TX7_N
AF9
SD2_REF_CLK1_P
AD6
SD2_REF_CLK1_N
AD5
SD2_REF_CLK2_P
AK11
SD2_REF_CLK2_N
AJ11
SD2_IMP_CAL_TX
AE10
SD2_IMP_CAL_RX
AA8
SD2_RX0_P
AA3
SD2_RX0_N
AA4
SD2_RX1_P
AC3
SD2_RX1_N
AC4
SD2_RX2_P
AD1
SD2_RX2_N
AD2
SD2_RX3_P
AK3
SD2_RX3_N
AJ3
SD2_RX4_P
AJ5
SD2_RX4_N
AK5
SD2_RX5_P
AK6
SD2_RX5_N
AJ6
SD2_RX6_P
AJ8
SD2_RX6_N
AK8
SD2_RX7_P
AK9
SD2_RX7_N
AJ9
SD2_PLL1_TPA
AC7
SD2_PLL2_TPA
AG11
SD2_PLL1_TPD
AC8
SD2_PLL2_TPD
AF11
R152 0
C111 100NF
C86 100NF
R132
10
R141 0
U21
859S0212BGILF
CLK_SEL
1
PCLK0
2
PCLK0
3
PCLK1
4
PCLK1
5
NC
6
OE
7
SEL_OUT
8
VCC_TAP
9 VEE
10
Q1
11Q1
12
Q0
13Q0
14
VEE
15VCC
16
R167
4,7K
R173 130
C109 100NF
R162 150R
R170 130
R136
10
R159 82R
R161 82R
R157
1,5K
R139 0
R147
698R
R171 130
R160 82R
R154 0
C107 100NF
C85 100NF
R156
10
SERDES 1
X1VDD
S1VDD
S1VDD
X1VDD
S1VDD
U1A
T2080NXN8PTB
SD1_TX0_P
AG14
SD1_TX1_P
AE16
SD1_TX2_P
AD18
SD1_TX3_P
AF18
SD1_TX4_P
AD20
SD1_TX5_P
AF21
SD1_TX6_P
AF23
SD1_TX7_P
AD23
SD1_TX0_N
AG15
SD1_TX1_N
AF16
SD1_TX2_N
AD19
SD1_TX3_N
AE18
SD1_TX4_N
AD21
SD1_TX5_N
AE21
SD1_TX6_N
AE23
SD1_TX7_N
AD24
SD1_RX0_P
AH12
SD1_RX1_P
AK13
SD1_RX2_P
AJ17
SD1_RX3_P
AH17
SD1_RX4_P
AJ20
SD1_RX5_P
AH20
SD1_RX6_P
AJ23
SD1_RX7_P
AH23
SD1_RX0_N
AH13
SD1_RX1_N
AJ13
SD1_RX2_N
AK17
SD1_RX3_N
AH18
SD1_RX4_N
AK20
SD1_RX5_N
AH21
SD1_RX6_N
AK23
SD1_RX7_N
AH24
SD1_REF_CLK1_P
AJ15
SD1_REF_CLK2_P
AJ25SD1_REF_CLK1_N
AK15
SD1_REF_CLK2_N
AK25
SD1_PLL1_TPD
AE14
SD1_PLL2_TPD
AG25
SD1_IMP_CAL_TX
AC22
SD1_IMP_CAL_RX
AA15
SD1_PLL1_TPA
AE15
SD1_PLL2_TPA
AF25
C105 100NF
C88 100NF
C116
100NF
C100 100NF
C103 100NF
EC1_RXD0
EC1_RXD1
EC1_RXD2
EC1_RXD3
EC1_TXD0
EC1_TXD1
EC1_TXD2
EC1_TXD3
SD1_REFCLK1_N
SD1_REFCLK1_P
SD2_REFCLK1_N
SD2_REFCLK1_P
3V3_859S0212I
SD2_REFCLK1_N
SD2_REFCLK1_P
SD1_REFCLK1_N
SD1_REFCLK1_P
10. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
T2080 USB INTERFACE
Resistor installed = Host Mode
Not installed = Device Mode
USBCLK BELONGS TO OVDD
ACB_0001_0
1V8
USB1_DN 11
USB1_DP 11
USB2_DP 15
USB2_DM 15
GPIO3_0 15
GPIO3_1 15
GPIO3_2 15
GPIO3_3 15
GPIO3_4 15
GPIO3_5 15
GPIO3_6 15
GPIO3_7 15
Project
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PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
USB
0 A310 45
Tuesday, August 11, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
USB
0 A310 45
Tuesday, August 11, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
USB
0 A310 45
Tuesday, August 11, 2020
<Variant Name>
U22
24MHZ
ON
1
GND
2
OUT
3
VDD
4
R174 0
R194
33
IEEE1588
(LVDD)
(OVDD)
USBPHY1&2
USB_HVDD
U1K
T2080NXN8PTB
TSEC_1588_CLK_IN
T3
TSEC_1588_CLK_OUT
V3
TSEC_1588_PULSE_OUT1
W2
TSEC_1588_PULSE_OUT2
W1
TSEC_1588_ALARM_OUT1
U1
TSEC_1588_TRIG_IN1
V4
TSEC_1588_TRIG_IN2
V2
TSEC_1588_ALARM_OUT2
W5
USB1_UDP
B8
USB1_UDM
C7
USB1_VBUSCLMP
E7
USB1_UID
E5
USB2_UDP
A6
USB2_UDM
B6
USB2_VBUSCLMP
C6
USB2_UID
D7
USBCLK
B11
USB_IBIAS_REXT
F7
USB1_DRVVBUS
A8
USB1_PWRFAULT
B9
USB2_DRVVBUS
B5
USB2_PWRFAULT
A5
R175 0
C125
100NF
R190
49,9
R182
4,7K
C124
1UF
R176 0
TP15
R183
4,7K
R186 0
R177 0
C123
10NF
TP16
R184
4,7K
C126
10PF
C121
100NF
TP17
R178 0
R193
1K
R192
49,9
TP18
R187 0
R179 0
C122
100NF
R188 0
R189
10K
R180 0
L2
BLM18EG601SN1
R191
49,9
R181 0
R185 0
1V8_OSC_USB USB_REFCLK
USB1_DP
USB1_DM
USB2_DP
USB2_DM
USB_REFCLK
11. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
ACB_0001_0
HUB USB
KB CONTROLLER
WLAN M2
M2 LTE
Card Reader
3V3
3V3
3V3
5V
3V3
3V3 3V3 3V3 3V3
3V3
3V3
3V3
HUB_USB3_DN 28
HUB_USB3_DP 28
HUB_USB4_DN 25
HUB_USB4_DP 25
USB1_DN 10
USB1_DP 10
HUB_USB1_DN 12
HUB_USB1_DP 12
HUB_USB2_DN 27
HUB_USB2_DP 27
Project
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PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
USB HUB
0 A311 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
USB HUB
0 A311 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
USB HUB
0 A311 45
Monday, August 10, 2020
<Variant Name>
R198
10K
C135
100NF
C127
100NF
R205
10K
R200
10K
C142
4,7uF
R209
100K
C134
1UF
L3
BLM18EG601SN1
R196
47K
R202 12,1K
Upstream
Downstream 1
Downstream 2
Downstream 3
Downstream 4
SOLO PER
IL
2514
EEPROM/Config
Common
U23
USB2514-AEZC
USBUP_DP
31
USBUP_DM
30
USBDN1_DP
2
USBDN2_DP
4
USBDN3_DP
7
USBDN4_DP
9
USBDN1_DM
1
USBDN2_DM
3
USBDN3_DM
6
USBDN4_DM
8
VBUS_DET
27
PRTPWR1
12
PRTPWR2
16
PRTPWR3
18
PRTPWR4
20
OCS1
13
OCS2
17
OCS3
19
OCS4
21
RBIAS
35
SDA/SMBDATA/NON_REM1
22
SCL/SMBCLK/CFG_SEL0
24
HS_IND/CFG_SEL1
25
XTAL1/CLKIN
33
XTAL2
32
RESET
26
LOCAL_PWR/NON_REM0/SUSP_IND_N
28
TEST
11
VDD33(IO)
23
VDDPLL18
34
VDDA33
29
VDDPLLREF/VDDA33
36
VDD33(REG)
15
VDDCR18
14
EP
VDDA33
5
VDDA33
10
Y1
24MHz
1
3
2
4
R208
100K
R195
22K
R204
10K
C138
100NF
R197
10K
R203
1M
R201
100K
R206
10K
C132
12PF
C131
4,7uF
C139
100NF
C128
100NF
R210
100K
C133
12PF
C130
100NF
D2
BAS116
C137
100NF
C140
100NF
R207
10K
C129
100NF
C141
100NF
R199
10K
C136
1UF
R211
100K
HUB_OCS1n
HUB_OCS2n
CFG_SEL0
CFG_SEL1
NON_REM1
HUB_USB2_DP
HUB_USB2_DN
HUB_USB1_DN
HUB_USB1_DP
NON_REM0
HUB_OCS3n
NON_REM0CFG_SEL0CFG_SEL1 NON_REM1
12. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
ACB_0001_0
NC FOR USB
3V3 3V3_KB
3V3_KB
3V3_KB
3V3_KB
3V3_KB 3V3_KB
3V3_KB
5V 5V_KB
5V_KB 3V3_KB 3V3_KB
KB_RESET 15
RGB_KB_DET#15
BKPWM15
CHGEN 42ACP 42
HUB_USB1_DN11
HUB_USB1_DP11
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
KEYBOARD
0 A312 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
KEYBOARD
0 A312 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
KEYBOARD
0 A312 45
Monday, August 10, 2020
<Variant Name>
R214330
D3
LED VERDE
C145
2,2UF
R224
10K
R225
10K
R2220
R2280
R223
10K
R230
330
J4
SFW30R-1STE9LF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
FIX
U25
SRV05-4
4
2 5
3
1 6
C144
100NF
R212
0
R221 330
R218
10K
R226
10K
J5
HEADER 12
2
1
3
5
7
9
11
4
6
8
10
12
R2270
TP20
R2200
R219 330
R216 0
SK5126
COL16
2
COL17
3
ROW7
4
ROW6
5
ROW5
6
ROW4
7
ROW3
8
ROW2
9
ROW1
10
ROW0
11
GPO1/BLPWM
13
NC1
14
NC2
15
GPO0
16
COL00/PRGC
17
VSS
18
D+/PS2CLK
19
D-/PS2DAT
20
VDD
21
COL01/PRGD
22
USBEN
23
XPS2C
25XRES
26COL02
27COL03
28COL04
29COL05
30COL06
31COL07
32
VSS
EP
COL08
33COL09
34COL10
35COL11
36
VDD1
41NC3
42NC4
43nLEDNUM
44nLEDFN
45COL14
46VSS1
47COL15
48
NC0
1
VMOD
12
XPS2D
24
COL12
37COL13
38nLEDSCROLL
39nLEDCAPS
40
R215
0
Q1
2N7002L
1
23
TP19
C143
100NF
Q2
2N7002L
1
23
D4
LED VERDE
R213330
TP21
R217
10K
R229
330
KB_ROW0
KB_ROW1
KB_ROW2
KB_ROW3
KB_ROW4
KB_ROW5
KB_ROW6
KB_ROW7
KB_COL17
KB_COL16
KB_COL15
KB_COL14
KB_COL0
KB_COL1
KB_COL2
KB_COL3
KB_COL4
KB_COL5
KB_COL6
KB_COL7
KB_COL8
KB_COL9
KB_COL10
KB_COL11
KB_COL12
KB_COL13
LEDFN
SCROLL#
USBEN
SCROLL#
CAPS#
LEDFN
LEDNUM
KB_ROW0
KB_ROW1
KB_ROW2
KB_ROW4
KB_ROW5
KB_ROW3
KB_ROW6
KB_ROW7
KB_COL7
KB_COL8
KB_COL9
KB_COL10
KB_COL11
KB_COL12
KB_COL13
KB_COL15
KB_COL14
KB_COL4
KB_COL5
KB_COL6
KB_COL1
KB_COL2
KB_COL3
KB_COL0
CAPS#
LEDNUM
13. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
ACB_0001_0
JLED2
JLED1
5V
5V
5V
5V
KB_LED_PWM 15
KB_RED15
KB_GREEN15
KB_BLUE15
JLED_RED 15
JLED_GREEN 15
JLED_BLUE 15
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
KB_LED_AND_LED
0 A313 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
KB_LED_AND_LED
0 A313 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
KB_LED_AND_LED
0 A313 45
Monday, August 10, 2020
<Variant Name>
M7
DMN3730U-7 1
23
C152
2,2UF
M5
DMN3730U-71
23
C150
2,2UF
R232 0
C148
1UF
J7
SWF-0810H17
2
1
3
5
7
9
11
4
6
8
10
12
R238
4,7K
M8
DMN3730U-7 1
23
R233 0
J8
SWF-0810H17
2
1
3
5
7
9
11
4
6
8
10
12
R239
0
J6
F1013-0402
1
2
3
4
5
6
R234 0
M9
DMN3730U-7 1
23
C146
100NF
R235 0
C147
2,2UF
M3
DMN3730U-71
23
M6
DMN3730U-71
23
R231 0
R236 0
M4
DMN3730U-7 1
23
R241 0
R237 0
R240 0
C151
100NF
C149
100NF
KBL2
KBL3
KBL4
KB_LED_VDD
RED-
GREEN-
BLUE-
VLED-
14. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
T2080 DUART and I2C DEVICE INTERFACE
I2C ADDR = 0x50
I2C EEPROM
I2C THERMAL MONITOR
I2C ADDR = 0x4C
RTC
I2C ADR = 0x68
Lithium Rechargeable Battery
ACB_0001_0
3V3
3V3
3V3
3V3
3V3
3V3
3V32V5
2V5 3V3
VBAT
3V33V3
2V5 3V3
2V5
2V5
I2C1_SCL8,14,32,36,37,38
I2C1_SDA8,14,32,36,37,38
TEMP_DIODE_P8
TEMP_DIODE_N8
RTC_INT_N 8
I2C1_SCL8,14,32,36,37,38
I2C1_SDA8,14,32,36,37,38
THERM_ALERT_N 43
THERM_FAULT_N 15
I2C1_SDA8,14,32,36,37,38
I2C1_SCL8,14,32,36,37,38
UART2_RTSB 27
UART2_CTSB 27
UART1_RTSB 15
UART1-CTSB 15
UART2_TXD 27
UART2_RXD 27
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
UART&I2C
0 A314 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
UART&I2C
0 A314 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
UART&I2C
0 A314 45
Monday, August 10, 2020
<Variant Name>
C168
100NF
Y2
32,768KHz
R2440
C159
100NF
U29
DS1339U-33+
X1
1
X2
2
VBACKUP
3
GND
4
SDA
5 SCL
6
SQWINT
7
VCC
8
R2490
C153
100NF
C155
100NF
C165
100NF
BTH1
3098
2
1
1
R2450
C154
100NF
BATT1
3V 5mAh
C157
100NF
U26
TXS0104E
VCCA
1
A1
2
A2
3
A3
4
A4
5
NC1
6
OE
8
GND
7
VCCB
14
B1
13
B2
12
B3
11
B4
10
NC2
9
U30
AT24C256C-SSHL-B
A0
1
A1
2
A2
3
GND
4
SDA
5 SCL
6
WP
7
VCC
8
L5
BLM18EG601SN1
R2500
U31
ADT7481ARM
VDD
1
D1+
2
D1-
3
THERM
4
GND
5
ALERT/THERM2
8
SDATA
9 SCLK
10
D2-
6 D2+
7
R2520
R257 100
J9
STRIP 2x3
1
1
3
3
5
5
2
2
4
4
6
6
R261
100
R2530
C167
1NF
TP22
DUART(DVDD)
U1J
T2080NXN8PTB
UART1_SOUT
J1
UART1_SIN
J3
UART1_RTS_B
G1
UART1_CTS_B
L4
UART2_SOUT
K3
UART2_SIN
F2
UART2_RTS_B
J4
UART2_CTS_B
F1
C161
470PF
R255 100R2540
C166
10uF
C163
470PF
C158
100NF
TP23
R2560
R264
100
R259 100
R2480
C1+
V+
VCC
C1-
C2+
C2- V-
T
T
GND
T1OUT
T2OUT
T1IN
T2IN
R
R
R1IN
R2IN
R1OUT
R2OUT
TTL 232
TTL 232
U27
MAX3232ECPWR
1 16
3
4
5
15
11
10 7
14
2
6
9
12 13
8
L4
BLM18EG601SN1
L6
BLM18EG601SN1
C162
470PF
C164
100NF
R251 100
C156
100NF
U28
TXS0104E
VCCA
1
A1
2
A2
3
A3
4
A4
5
NC1
6
OE
8
GND
7
VCCB
14
B1
13
B2
12
B3
11
B4
10
NC2
9
R2460
R260
1K
R2420
R263
4,7K
C160
470PF
R262
4,7K
R2470
L7
BLM18EG601SN1
R2430
R2580
RS232_TXD2
RS232_RXD2
RS232_TXD1
RS232_RXD1
PROC_UART1_RXD
PROC_UART1_TXD
PROC_UART2_RXD
PROC_UART2_TXD
UART1_TXD_OUT
UART2_TXD_OUT
UART1_RXD_OUT
RS232_TXD1
RS232_RXD1
RS232_TXD2
RS232_RXD2
UART2_RXD_OUT
PROC_UART2_RTSB
PROC_UART2_CTSB
PROC_UART1_RTSB
PROC_UART1_CTSB
15. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
ACB_0001_0
BANK0
BANK1
3V3_CPLD 3V3_CPLD
3V3_CPLD
VCCIO04 VCCIO21
3V3
GND GND GND GND GND GND
3V3_CPLD
VCCIO01 VCCIO02 VCCIO03
VCCIO02
VCCIO04
3V3_CPLD
VCCIO01
VCCIO31
VCCIO03
VCCIO12
3V3_CPLD
VCCIO11
VCCIO21
3V3
3V3
3V3
3V3
VCCIO12
VCCIO31
VCCIO11
VCCIO04
VCCIO01
VCCIO02
VCCIO03
M2_RSTN 22
SATA_RSTN 21
PCIE_BRIDGE_RSTN 26
MXM_RSTN 30
USB2_DP10
USB2_DM10
USB_CAM_DP 31
USB_CAM_DN 31
SATA3_WAKE_N 21
PE_WAKEN 27
PDETECT 22
PROC_SPI_MISO7
PROC_SPI_MOSI7
PROC_SPI_CLK7
GPIO2_17
GPIO2_27
GPIO2_37
GPIO2_105
GPIO1_95
GPIO1_105
GPIO1_115
GPIO1_125
GPIO2_135
GPIO2_145
GPIO4_299
GPIO3_279
GPIO3_269
GPIO3_259
GPIO3_249
GPIO4_279
GPIO4_289
GPIO3_319
GPIO3_30 9
GPIO3_29 9
GPIO3_28 9
GPIO4_30 9
GPIO4_31 9
GPIO3_4 10
GPIO3_2 10
GPIO3_1 10
GPIO3_3 10
GPIO3_7 10
GPIO3_6 10
GPIO3_5 10
GPIO3_0 10
IRQ00 8
IRQ01 8
IRQ028
IRQ088
PORESET_N 8
HRESET_N 8
RESET_REQ_N 8
UART1_RTSB14
IRQ098
CPLD_RST# 15
EC1_RST_N 19
DDR_RST_N 3,4
NOR_CS_N 6
NOR_RST_N 6
NAND_CS_N 6
PCIE_PWR_ON 28
PWR_ON_OFF 28
BT_EN 27
WLAN_EN 27
3G_EN 28
WLAN_WAKEUP 27
IFC_RB0_N5
IFC_RB1_N5
IFC_CLK5
IFC_CS0_N5
IFC_CS1_N5
IFC_CS2_N5
NAND_RB_N 6
CFG_VBANK[0..2] 6
USB3_PEWAKEB 23
PRSNT_R# 30
MXM_WAKE# 15,30
PWR_RST_N 43
MXM_WAKE# 15,30
VCORE_EN 37,38,40
UART1-CTSB14
FAN_PWM 43
MXM_TH_PWM 30
BKPWM 12
GPIO4_68
GPIO4_58
EXP_SDA32
EXP_SCL32
VLED_ON 31
WLAN_PWR_EN 27
RGB_KB_DET# 12
MXM_PGOOD 30
MXM_PWR_EN 30
JLED_RED 13
JLED_GREEN 13
JLED_BLUE 13
CLK_REQ# 30
THERM_FAULT_N 14
GPIO4_4 8
KB_RED 13
KB_GREEN 13
KB_BLUE 13
BRIGHTNESS 31
KB_LED_PWM 13
KB_RESET 12
CPLD_RST# 15
VCORE_PGOOD 37,38
VCORE_HOT_N 37,38
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
WRAPPER
0 A315 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
WRAPPER
0 A315 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
WRAPPER
0 A315 45
Monday, August 10, 2020
<Variant Name>
R293 0
TP24
R358 0
C171
100NF
R364 0
R281 0
C178
100NF
R304 0
R307 0
R2720
R340
10K
R338 0
TP25
C188
4,7uF
C191
100NF
R331 0
R351 0
C172
100NF
C179
4,7uF
R282 0
R287 0
R342 0
R308 0
TP30
R329 0
U35
TCA6424ARGJR
P00
1
P01
2
P02
3
P03
4
P04
5
P05
6
P06
7
P07
8
P10
9
P11
10
P12
11
P13
12
P14
13
P15
14
P16
15
P17
16
P20
17P21
18P22
19P23
20P24
21P25
22P26
23P27
24
GND
25 ADDR
26 VCCP
27 RESET
28 SCL
29 SDA
30 VCCI
31 INT
32
EP
R298 0
C173
100NF
C180
100NF
R283 0
R266 0
C189
100NF
C190
100NF
R320 0
R325 0
R333 0
R309 0
C182
100NF
R310 0
R299 0
R265 0
C174
100NF
TP26
C181
4,7uF
R284 0
R352 0
R344 0
R350 0
R322 0
R318 0
R311 0
R278
10K
J10
STRIP 8
1
2
3
4
5
6
7
8
R326
10K
R301 0
R312 0
C175
100NF
R285 0
R354 0
R330 0
R335 0
R356
10K
R324 0
R343 0
R341
10K
R313 0
C183
100NF
U33
50MHZ
ON
1
GND
2
OUT
3
VDD
4
R302 0
U34
PCA9532
LED0
4
LED1
5
LED2
6
LED3
7
LED4
8
LED5
9
LED6
10
LED7
11
LED8
13
LED9
14
LED10
15
LED11
16
LED12
17
LED13
18
LED14
19
LED15
20
VDD
24
A0
1
A1
2
A2
3
RESET
21
SCL
22 SDA
23
R269 0
R355 0
R321 0
R328 0
TP29
U32
LCMXO640C-3TN100C
PR3D
69
TMS
26
PL9B
27
TCK
28
PB2A
29
PB2B
30
TDO
31
PB2C
32
TDI
33
PB2D
34
VCC
35
PB3A/PCLKT1_1
36
PB3B
37
PB3C/PCLKT1_0
38
PB3D
39
GND
40
VCCIO1
41
GNDIO1
42
PB4A
43
PB4B
44
PB4C
45
PB4D
46
PB5A
47
SLEEPN
48
PB5C
49
PB5D
50
PR9B
51PR9A
52PR8B
53PR8A
54PR7D
55PR7C
56PR7B
57PR7A
58PR6B
59
PL3D
6
PL4A
7
PL4B
8
PL5A
9 PR4A
68
PR4B
67
PR5A
66
PR5B
65
PR5C
64
PR5D
63
GNDIO0
62
PR6A
61
VCCIO0
60
VCCIO1
24
PL3B
4
PL7C
19
PL9A
23
PL2A
1
PL8A
21
GNDIO1
25
PL3C
5
PL3A
3 PL2B
2
PL8B
22
PL7D
20
PL5D/GSR_N
14
PL5B
11
PL6A
15
PL5C
13
VCCIO3
10
PL6B/TSALL
16
PL7A
17
GNDIO1
12
PL7B
18
PT5A
79
PT5B
78
PT5C
77
PR2A
76
GNDIO0
75
VCCIO0
74
PR2B
73
PR3A
72
PR3B
71
PR3C
70
PT2B
99PT2A
100
PCLKT0_1/PT4B
85
GND
84
PT4C
83
PT4D
82
PT4E
81
PT4F
80
PT2C
98
PT2D
97
PT2E
96
PT2F
95
PT3A
94
GNDIO0
93
VCCIO0
92
PT3B
91
VCC
90
PT3C
89
VCCAUX
88
PT3D
87
PCLKT0_0/PT4A
86
R353
10K
C184
100NF
R359 0
R332 0
R339
10K
R270 0
R305 0
R314 0
R280 0
R360 0
TP27
R347 0
R275 0
R306 0
R2740
TP31
R315 0
TP28
R334 0
R361 0
R294 0
R277 0
R276 0
R316 0
R362 0
R295 0
R289 0
R27933
C169
100NF
R271 0
R327
10K
TP32
R348 0
R296 0
R317 0
R297 0
R349 0
C185
100NF
TP33
R288 0
R267 0
C176
100NF
R291 0
R273 0
R323
10K
R336 0
TP34
R319 0
R268 0
R300 0
R292 0
C186
4,7uF
R345 0
R303 0
C170
100NF
R363 0
R357 0
C177
4,7uF
R290 0
R337 0
R286 0
R346 0
C187
100NF
CFG_VBANK1
CFG_VBANK2
CFG_VBANK0
CPLD_TDO
CPLD_TDI
CLK_50MHZ
CPLD_TMS
CPLD_TCK
VCCIO0
CLK_50MHZ
CPLD_TMS
CPLD_TCK
CPLD_TDO
CPLD_TDI
EXP_SDA
EXP_SCL
EXP_SDA
EXP_SCL
16. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
T2080 POWER SUPPLY
USB_SVDD supply must ramp before or after the
USB_HVDD and USB_OVDD supplies have ramped.
ACB_0001_0
VCORE
VCORE
3V3
1V8
1V8
1V35
1V35
1V35
1V35
VCORE
SENSEVDD 37
SENSEGND 37
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PROC PWR1
0 A316 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PROC PWR1
0 A316 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PROC PWR1
0 A316 45
Monday, August 10, 2020
<Variant Name>
C273
100nF
C221
100nF
C275
100NF
R368
330m
C263
100NF
C247
3,3NF
C311
220NF
C304
1UF
C272
100nF
C220
100NF
C210
4,7uF
C204
1UF
C230
2.2UF
C307
100NF
R371
5.1
C222
100NF
C266
100NF
C252
100NF
C269
100NF
C260
4,7uF
R374
5.1
C243
100NF
C300
100NF
C284
100NF
C209
4,7nF
R365
330m
C235
4,7nF
C306
100NF
C259
4,7nF
C239
100NF
C303
10uF
C267
2.2UF
C254
100NF
C298
100NF
C278
100NF
R366
330m
C199
22uF
C257
100NF
C237
100NF
R373
5.1
C216
100nF
C236
4,7uF
PS
CORES&PLATFORM(1V0)
PLL SERDES
(1V35,1V5/0V)
(XVDD
filtered)
PLL PLATFORM
PLL DDR
PLL CORE GROUP
1V8
USB ANALOG (1V0)
3V3
USB
TRANSCEIVER
1V8
1V0
U1G
T2080NXN8PTB
AVDD_CGA2
G9
AVDD_PLAT
J10
AVDD_CGA1
H9
AVDD_D1
F22
AVDD_SD1_PLL1
AB17
AVDD_SD1_PLL2
AB20
AVDD_SD2_PLL1
AB11
SENSEVDD
J20
USB_SVDD2
G7
USB_OVDD2
J8
USB_HVDD1
A7
USB_HVDD2
C8
AVDD_SD2_PLL2
AB14
SENSEGND
K21
FA_ANALOG_PIN
G20
FA_ANALOG_G_V
H21
VDD1
L9
VDD2
L11
VDD3
L13
VDD4
L15
VDD5
L17
VDD6
L19
VDD7
L21
VDD8
M10
VDD9
M12
VDD10
M14
VDD11
M16
VDD12
M18
VDD13
M20
VDD14
N9
VDD15
N11
VDD16
N13
VDD17
N15
VDD18
N17
VDD19
N19
VDD20
N21
VDD21
P10
VDD22
P12
VDD23
P14
VDD24
P16
VDD25
P18
VDD26
P20
VDD27
R9
VDD28
R11
VDD29
R13
VDD30
R15
VDD31
R17
VDD32
R19
VDD33
R21
VDD34
T10
VDD35
T12
VDD36
T14
VDD37
T16
VDD38
T18
VDD39
T20
TH_TPA
F8
USB_SVDD1
F6
USB_OVDD1
J7
VDD40
U9
VDD41
U11
VDD42
U13
VDD43
U15
VDD44
U17
VDD45
U19
VDD46
U21
VDD47
V10
VDD48
V12
VDD49
V14
VDD50
V16
VDD51
V18
VDD52
V20
VDD53
W9
VDD54
W11
VDD55
W13
VDD56
W15
VDD57
W17
VDD58
W19
VDD59
W21
VDD60
Y10
C244
100NF
C253
100NF
C205
1UF
C292
100NF
L10
BLM18EG601SN1
C215
100nF
C288
100NF
C231
100nF
C296
100NF
C227
100nF
C276
100NF
C295
100NF
C218
100nF
C291
100NF
C217
100nF
C299
100NF
C279
100NF
C271
3,3NF
C195
22uF
C283
100NF
C289
100NF
C265
100NF
C224
47uF
C297
100NF
L8
BLM18EG601SN1
C197
22uF
C214
100nF
C261
100NF
C250
100NF
C200
22uF
C309
10uF
C280
10uF
C241
100NF
R370
0
C228
4,7uF
C212
100nF
C282
220NF
C223
100NF
C264
100NF
C251
100NF
R372
0
C287
220NF
C262
100NF
R367
330m
R369
5.1
C240
100NF
C192
22uF
C208
47uF
C234
47uF
C258
47uF
C281
1UF
C238
100NF
C268
2.2UF
C211
100nF
C194
22uF
C242
100NF
C310
1UF
C255
100NF
C198
22uF
C290
100NF
C196
22uF
C305
220NF
C245
2.2UF
C246
2.2UF
C256
100NF
C203
22uF
C225
4,7nF
L9
BLM18EG601SN1
C232
100nF
C207
1UF
C219
100NF
C293
100NF
C248
100nF
C233
100nF
C286
1UF
C301
100NF
C274
100NF
C206
1UF
C277
100NF
C249
100nF
C308
100NF
C201
22uF
C226
100nF
C294
100NF
C229
2.2UF
C285
10uF
C270
100NF
C193
22uF
C302
100NF
C213
100NF
C202
22uF
1V0_USB_SVDD
3V3_USB_HVDD
1V8_USB_OVDD
AVDD_SD1_PLL1
AVDD_SD1_PLL2
AVDD_SD2_PLL1
AVDD_SD2_PLL2
AVDD_CGA1
AVDD_CGA2
AVDD_PLAT
AVDD_DDR1
AVDD_CGA1
AVDD_CGA2
AVDD_PLAT
AVDD_DDR1
AVDD_SD1_PLL1
AVDD_SD1_PLL2
AVDD_SD2_PLL1
AVDD_SD2_PLL2
17. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
T2080 POWER SUPPLY (cont.)
LABEL = FA_VDD
LABEL = PROG_SFP
LABEL = PROG_MTR
ACB_0001_0
1V35
1V8
2V5
1V8
SVDD
XVDD
1V8
1V8
1V35
1V0S
1V35
1V0_LP
2V5
1V8
2V5
2V5
VCORE
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PROC PWR2
0 A317 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PROC PWR2
0 A317 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PROC PWR2
0 A317 45
Monday, August 10, 2020
<Variant Name>
C337
10NF
C384
100NF
C379
100NF
C362
10uF
C328
100NF
C345
2.2UF
C313
22uF
R376
330
R380
330
C329
100NF
R375 0
C312
22uF
C332
100NF
C381
100NF
C327
100NF
C380
100NF
C326
100NF C330
100NF
C373
100NF
C335
100NF
C354
100NF
R377 0
R378
330
C319
1UF
C355
100NF
FL1
NFM18PC105R0J3D
C365
100NF
C346
2.2UF
C323
100NF
C341
10NF
C375
100NF
C325
100NF
C363
100NF
C316
1UF
R379 0
C349
100NF
C322
100NF
C343
10NF
C366
2.2UF
C334
100NF
C376
100NF
C382
100NF
C348
100NF
C342
10NF
C320
10uF
C371
100NF
C340
10NF
C364
100NF
C357
100NF
C339
10NF
C350
100NF
C353
100NF
C336
100NF
C315
22uF
C372
100NF
C356
100NF
C317
1UF
C333
100NF C331
100NF
C368
3,3NF
C358
100NF
C378
100NF
C360
100NF
C314
22uF
C321
10uF
C344
10NF
C369
100NF
C374
100NF
C351
100NF
C377
100NF
C318
1UF
C324
100NF
C370
100NF
C352
100NF
FL2
NFM18PC105R0J3D
C359
100NF
C383
100NF
C338
10NF
C347
3,3NF
C367
2.2UF
C361
100NF
PS
GENERALI/O(1V8)
DDR(1V35/1V5)
SERDESCORELOGIC(1V0)SERDESTRANSCEIVER(1V35/1V5)
(GND/1V89)
(GND/1V0)
1V0
1V8
UART,I2C,DMA
(1V8/2V5)
eSPI(1V8/2V5)
ETH(2V5)
U1F
T2080NXN8PTB
DVDD1
N8
DVDD2
P8
LVDD1
T8
LVDD2
U8
LVDD3
V8
TH_VDD
K10
CVDD1
M6
FA_VL
H20
PROG_MTR
E8
PROG_SFP
E9
VDD_LP
R8
S1VDD1
Y16
S1VDD2
Y17
S1VDD3
Y18
S1VDD4
Y19
S1VDD5
Y20
S2VDD1
Y11
S2VDD2
Y12
S2VDD3
Y13
S2VDD4
Y14
S2VDD5
Y15
X1VDD1
AB22
X1VDD2
AD16
X1VDD3
AG17
X1VDD4
AG19
X1VDD5
AG20
X2VDD1
AE3
X2VDD2
AE11
X2VDD3
AG3
X2VDD4
AH4
X2VDD5
AH7
OVDD2
K12
OVDD3
K13
OVDD4
K14
OVDD5
K15
OVDD6
K16
OVDD7
K17
OVDD8
K18
OVDD9
K19
OVDD10
K20
G1VDD1
L22
G1VDD2
M22
G1VDD3
N22
G1VDD4
P22
G1VDD5
R22
G1VDD6
T22
G1VDD7
U22
G1VDD8
V22
G1VDD9
A29
G1VDD10
B30
G1VDD11
D29
G1VDD12
F29
G1VDD13
H29
G1VDD14
K29
G1VDD15
M29
G1VDD16
P29
G1VDD17
T29
G1VDD18
T30
G1VDD19
V29
G1VDD20
Y29
G1VDD21
AB29
G1VDD22
AD29
G1VDD23
AF29
G1VDD24
AJ30
G1VDD25
AK29
S1VDD6
Y21
S2VDD6
AA9
X1VDD6
AG22
X2VDD6
AH10
CVDD2
M8
OVDD11
L8
X1VDD7
AG24
OVDD1
K8
1V8_SFP
1V8_MTR
18. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
T2080 GROUND
ACB_0001_0
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
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Page title
PROC GND
0 A318 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PROC GND
0 A318 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PROC GND
0 A318 45
Monday, August 10, 2020
<Variant Name>
GND
PACKAGE_NC(AK1)
PACKAGE_NC(A30)
PACKAGE_NC(A1)
PACKAGE_NC(AK30)
U1H
T2080NXN8PTB
AGND_SD1_PLL1
AB16
AGND_SD1_PLL2
AB19
AGND_SD2_PLL1
AB10
AGND_SD2_PLL2
AB13
S2GND6
AA16
S1GND1
AA17
S1GND2
AA18
S1GND3
AA19
S1GND4
AA20
S1GND5
AA21
S1GND6
AB18
S1GND7
AC16
S1GND8
AC17
S1GND9
AC18
S1GND10
AC19
S1GND11
AC20
S2GND27
AD15
S1GND12
AH14
S1GND13
AH15
S1GND14
AH16
S2GND1
AA10
S2GND2
AA11
S2GND3
AA12
S2GND4
AA13
S2GND5
AA14
S2GND7
AB3
S2GND8
AB4
S2GND9
AB7
S2GND10
AB8
S2GND11
AB9
S2GND12
AB12
S2GND13
AC1
S2GND14
AC2
S2GND15
AC5
S2GND16
AC6
S2GND17
AC9
USB_AGND1
A9
USB_AGND2
B7
USB_AGND3
C5
USB_AGND4
D5
USB_AGND5
D6
USB_AGND6
D8
USB_AGND7
E6
USB_AGND8
G6
USB_AGND9
H7
S1GND15
AH19
S1GND16
AH22
S1GND17
AH25
S1GND18
AJ12
S1GND19
AJ14
S1GND20
AJ16
S1GND21
AJ18
S1GND22
AJ19
S1GND23
AJ21
S1GND24
AJ22
S1GND25
AJ24
S1GND26
AJ26
S1GND27
AK12
S1GND28
AK14
S1GND29
AK16
S1GND30
AK18
S1GND31
AK19
S2GND18
AC10
S2GND19
AC11
S2GND20
AC12
S2GND21
AC13
S2GND22
AC14
S2GND23
AD3
S2GND24
AD4
S2GND25
AD7
S2GND26
AD8
S2GND28
AE1
S2GND29
AE2
S2GND30
AE5
S2GND31
AE6
S2GND32
AH3
S2GND33
AH5
S2GND34
AH6
S2GND35
AH8
S2GND36
AH9
S2GND37
AH11
S2GND38
AJ4
S2GND39
AJ7
S2GND40
AJ10
S2GND41
AK2
S2GND42
AK4
S2GND44
AK10
X2GND1
Y3
X2GND2
Y4
X2GND3
AA1
X2GND4
AA2
X2GND5
AA5
X2GND6
AA6
X2GND7
AA7
X2GND8
AD10
X2GND9
AD11
X2GND10
AE4
X2GND11
AE7
X2GND12
AE8
X2GND13
AE9
X2GND14
AF3
X2GND15
AF4
X2GND16
AF7
X2GND17
AF10
X2GND18
AF12
X2GND19
AG1
X2GND20
AG2
X2GND21
AG4
X2GND22
AG7
X2GND23
AG10
X2GND24
AG12
X2GND25
AJ1
X2GND26
AJ2
X1GND1
AB21
X1GND2
AC21
X1GND3
AC23
X1GND4
AD17
X1GND5
AD22
X1GND6
AE17
X1GND7
AE19
X1GND8
AE20
X1GND9
AE22
X1GND10
AE24
X1GND11
AF14
X1GND12
AF15
X1GND13
AF17
X1GND14
AF19
X1GND15
AF20
X1GND16
AF22
X1GND17
AF24
X1GND18
AG13
X1GND19
AG16
X1GND20
AG18
X1GND21
AG21
X1GND22
AG23
S2GND43
AK7
S1GND32
AK21
S1GND33
AK22
S1GND34
AK24
S1GND35
AK26
USB_AGND10
H8
NC1
AB15
NC2
AC15
NC3
AD9
NC4
AD12
NC5
AD13
NC6
AD14
NC7
AE12
NC8
AE13
NC9
AF13
ORIENTATION_(GND)
Y2
GND
U1N
T2080NXN8PTB
GND001
A2
GND002
A4
GND003
A23
GND004
A27
GND005
B1
GND006
B4
GND007
B10
GND008
B13
GND009
B16
GND010
B19
GND011
B23
GND012
B26
GND013
C3
GND014
C22
GND015
C24
GND016
C28
GND017
D4
GND018
D9
GND019
D23
GND020
D26
GND021
E2
GND022
E12
GND023
E15
GND024
E18
GND025
E21
GND026
E22
GND027
E24
GND028
E28
GND029
F9
GND030
F20
GND031
F23
GND032
F26
GND033
G4
GND034
G8
GND035
G10
GND036
G21
GND037
G22
GND038
G24
GND039
G28
GND040
H2
GND041
H10
GND042
H13
GND043
H15
GND044
H17
GND045
H22
GND046
H26
GND047
J9
GND048
J11
GND049
J12
GND050
J14
GND051
J16
GND052
J18
GND053
J22
GND054
J24
GND055
J28
GND056
K4
GND057
K7
GND058
K9
GND059
K11
GND060
K23
GND061
K26
GND062
L2
GND063
L10
GND064
L12
GND065
L14
GND066
L16
GND067
L18
GND068
L20
GND069
L24
GND070
L28
GND071
M5
GND072
M7
GND073
M9
GND074
M11
GND075
M13
GND076
M15
GND077
M17
GND078
M19
GND079
M21
GND080
M23
GND081
M26
GND082
N4
GND083
N7
GND084
N10
GND085
N12
GND086
N14
GND087
N16
GND088
N18
GND089
N20
GND090
N24
GND091
N28
GND092
P2
GND093
P7
GND094
P9
GND095
P11
GND096
P13
GND097
P15
GND098
P17
GND099
P19
GND100
P21
GND101
P23
GND102
P26
GND103
R6
GND104
R10
GND105
R12
GND106
R14
GND107
R16
GND108
R18
GND109
R20
GND110
R24
GND111
R28
GND112
T4
GND113
T7
GND114
T9
GND115
T11
GND116
T13
GND117
T15
GND118
T17
GND119
T19
GND120
T21
GND121
T23
GND122
T26
GND123
U2
GND124
U7
GND125
U10
GND126
U12
GND127
U14
GND128
U16
GND129
U18
GND130
U20
GND131
U24
GND132
U28
GND133
V7
GND134
V9
GND135
V11
GND136
V13
GND137
V15
GND138
V17
GND139
V19
GND140
V21
GND141
V23
GND142
V26
GND143
W3
GND144
W4
GND145
W7
GND146
W8
GND147
W10
GND148
W12
GND149
W14
GND150
W16
GND151
W18
GND152
W20
GND153
W22
GND154
W24
GND155
W28
GND156
Y1
GND157
Y5
GND158
Y6
GND159
Y7
GND160
Y8
GND161
Y9
GND162
Y22
GND163
Y26
GND164
AA22
GND165
AA24
GND166
AA28
GND167
AB26
GND168
AC24
GND169
AC28
GND170
AD25
GND171
AD26
GND172
AE25
GND173
AE28
GND174
AF26
GND175
AG26
GND176
AG28
GND177
AH28
GND178
AK27
GND179
L7
19. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Single LED Mode
LED1
LED2
Blinking : Activity (RX, TX)
DescriptionPin
1 : Link off
0 : Link on (any speed), solid color
LED MODE
Single LED Mode
Strapping Pin
MODE2 MODE1 MODE0MODE3
Strapping Pins
0000
DescriptionMODE[3:0]
0001 reserved
0010 reserved
0011 reserved
0100 NAND Tree mode
0101 reserved
0110 reserved
0111 Chip Power Down
reserved
1001
Advertise all capabilites, except 1000BT half-duplex (RGMII)
1000
1101
Advertise 1000BT full-duplex only (RGMII)
reserved
1010
1100
1111 Advertise all capabilites (RGMII)
1110
1011
DescriptionMODE[3:0]
reserved
reserved
reserved
Advertise 1000BT full- and half-duplex only (RGMII)
CLK125_EN
0 = DISABLE
1 = ENABLE
Strapping Pins
PHYAD2 PHYAD1 PHYAD0
AVDDL_PMOSAVDDH
AVDDL
DVDDH
DVDDH DVDDHDVDDHDVDDH
DVDDL
AVDDL_PMOS
AVDDL_PLLAVDDH AVDDL DVDDL DVDDH
AVDDH
DVDDH DVDDH DVDDH DVDDH
DVDDH
AVDDL_PLL
AVDDL_PMOS
DVDDH
AVDDL_PMOS
DVDDH
DVDDH AVDDH
GND
GND
GND
GND
GND
AVDDH
3V3
3V3
EC1_GTXCLK 9
EC1_TXCTL 9
EC1_RST_N 15
EC1_RXCLK 9
EC1_RXCTL 9
EC1_REFCLK9
EC1_INT_N 8
EC1_PME_N 8
TXRXP_A20
TXRXM_A20
TXRXP_B20
TXRXM_B20
TXRXP_C20
TXRXM_C20
TXRXP_D20
TXRXM_D20
RGMII_LINK20
RGMII_LED_ACT20
EMI1_MDC 9
EMI1_MDIO 9
EC1_TXD[0..3] 9
EC1_RXD[0..3] 9
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
19 45
Monday, August 10, 2020Friday, August 17, 2018
A20
EC1 PHY
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
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Page title
ACB_0001_0
19 45
Monday, August 10, 2020Friday, August 17, 2018
A20
EC1 PHY
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
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Page title
ACB_0001_0
19 45
Monday, August 10, 2020Friday, August 17, 2018
A20
EC1 PHY
<Author> <Approved by><Cheked by>
<Variant Name>
R403
1K
C411
10uF
C414
10NFM11
FDV301N 1
23
C403
100NF
M10
FDV301N 1
23
R39322
C409
10NF
C415
10NF
L14
HF70ACB201209-T
R410
1K
C405
10NF
C396
10NF
R388 22
R385
10K
C408
10uF
R383 0
R39422
C389
100NF
C391
100NF
C395
10NF
L15
HF70ACB201209-T
R408
10K
Y3
25MHz
1
3
2
4
C398
100NF
R39222
R409
1K
C410
100NF
C416
10NF
R412
1K
R38922
R39022
L11
HF70ACB201209-T
C385
100NF
R411
1K
L12
HF70ACB201209-T
D6 BAT54
1 3
C404
10uF
R386
0
R384 0
R396
10K
R382
10K
R404
1K
U36
NLSV1T34AMX1TCG
VCCA
1
VCCB
6
A
2
GND
3
B
4
NC
5
C387 27PF
R387
12,1K
R407
10K
C390
10NF
C401
10NF
R39122
C412
10NF
C402
10NF
C406
10NF
D5
BAT54
13
R398
10K
C394
10uF
U37
IN
6
OUT
1
NC
2
EN
3
BIAS
4
GND
5
C393
100NF
R402
1K
C397
10NF
C407
100NF
C386
100NF
R406
10K
R397
10K
C417
10NF
C400
10NF
R39522
R381 22
C399
10uF
C413
10NF
R401
1K
L13
HF70ACB201209-T
R405
10K
KSZ9031RNX
48-pin QFN
Paddle Ground
(bottom of
chip)
U38
NC
13
LED2
15
DVDDH
16
LED1/PHYAD0/PME_N1
17
DVDDL
14
TXD0
19
TXD1
20
TXD2
21
TXD3
22
DVDDL
18
DVDDL
23
GTX_CLK
24
TX_EN
25DVDDL
26RXD3
27
VSS
29DVDDL
30RXD1
31RXD0
32RX_DV
33DVDDH
34RX_CLK
35MDC
36
MDIO
37INT_N/PME_N2
38DVDDL
39DVDDH
40CLK125_NDO
41RESET_N
42LDO_O
43
XO
45XI
46NC
47ISET
48
AVDDH
1
TXRXP_A
2
TXRXM_A
3
TXRXP_B
5
TXRXM_B
6
TXRXP_C
7
TXRXM_C
8
TXRXP_D
10
TXRXM_D
11
AVDDH
12
RXD2
28
AVDDL_PLL
44
EP
AVDDL
4
AVDDL
9
C388
10uF
R400
10K
R399
10K
C392 27PF
ETH_RESETn
XI
XO
CLK125_NDO
RXD0RXD2RXD3 RXD1
RXD2
RXD3
LED2
LED1
XI
CLK125_NDO
TXRXM_B
TXRXP_B
TXRXM_A
TXRXP_A
TXRXM_C
TXRXP_C
TXRXP_D
TXRXM_D
RX_CLK
RX_DV
RXD0
RXD1
RX_DV RX_CLK LED2 LED1
INT_N_3V3INT_N
RGMII_LINK
RGMII_LED_ACT
EC1_TXD0
EC1_TXD1
EC1_TXD2
EC1_TXD3
EC1_RXD0
EC1_RXD1
EC1_RXD2
EC1_RXD3
20. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Gigabit Ethernet
Led Ethernet Buffer
For Gigabit Ethernet protection, place close to magnetics
3V3
3V3
3V3
3V3
TXRXP_A19
TXRXM_A19
TXRXP_B19
TXRXM_B19
TXRXP_C19
TXRXM_C19
TXRXP_D19
TXRXM_D19
RGMII_LED_ACT19
RGMII_LINK19
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
20 45
Monday, August 10, 2020Friday, August 17, 2018
A40
ETHERNET CONN
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
20 45
Monday, August 10, 2020Friday, August 17, 2018
A40
ETHERNET CONN
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
20 45
Monday, August 10, 2020Friday, August 17, 2018
A40
ETHERNET CONN
<Author> <Approved by><Cheked by>
<Variant Name>
R415
10K
J11
STRIP_14
2
1
3
5
7
9
11
4
6
8
10
12
13
14
C418
100NF
R418
0
R417
0
R416
10K
R414
100
U39
SRV05-4
DNP
1
2
3 4
5
6
U40
SRV05-4
DNP
1
2
3 4
5
6
U41
SN74LVC2G07DBVR
1A
1
GND
2
2A
3
2Y
4
VCC
5
1Y
6
R413
100
C419
100NF
LINK_LED
ACT_LED
LINK_LED
ACT_LED
TXRXP_A
TXRXM_A
TXRXP_B
TXRXM_B
TXRXP_C
TXRXM_C
TXRXP_D
TXRXM_D
21. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
(Optional clk source: Oscillator)
MagniPlus -SATA Interface
MagniPlus
VAA2_3
1V8
1V8
3V3
VAA1
AVDD0 AVDD1
1V8
1V8
1V0
VAA2_0
3V3
1V8
1V8
VDD_10
VDDIO
VAA2_1
VAA2_2
SATA_PCIE_RX0P 9
SATA_PCIE_RX0N 9
SATA_PCIE_RX1P 9
SATA_PCIE_RX1N 9
SATA_PCIE_TX1P 9
SATA_PCIE_TX1N 9
SATA_PCIE_TX0P 9
SATA_PCIE_TX0N 9
S3_TXP22
S3_TXN22
S3_RXN22
S3_RXP22
S2_TXP22
S2_TXN22
S2_RXN22
S2_RXP22
S1_TXP22
S1_TXN22
S1_RXN22
S1_RXP22
S0_TXP22
S0_TXN22
S0_RXN22
S0_RXP22
SATA3_WAKE_N 15
SATA_PECLKP 36
SATA_PECLKN 36
SATA_RSTN 15
Project
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ACB_0001_0
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A30
SATA CONTROLLER
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
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ACB_0001_0
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A30
SATA CONTROLLER
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
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PCB Code BOM file
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ACB_0001_0
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Monday, August 10, 2020Tuesday, June 18, 2013
A30
SATA CONTROLLER
<Author> <Approved by><Cheked by>
<Variant Name>
C479
10NF
L18
BLM15GG471SN1D
C453
100NF
C426 100NF
TP38
C439 100NF
C432 100NF
TP43
C471
100NF
L20
BLM15GG471SN1D
C427 100NF
C491
100NF
C456
2,2UF
C433 100NF
C428 100NF
TP53
TP39
C476
100NF
TP44
C458
10NF
Y4
25MHz
1
3
2
4
C434 100NF
C421 100NF
C465
18PF
C429 100NF
C484
2,2UF
JPS1
12
C492
100NF
C459
1NF
C444
2,2UF
TP45
TP51
C464
18PF
C435 100NF
C430 100NF
C486
10NF
L17
BLM15GG471SN1D
TP48
L21
BLM15GG471SN1D
C457
100NF
C446
10NF
TP50
C431 100NF
C487
1NF
L23
BLM18EG601SN1
TP52
C480
2,2UF
TP46
C493
100NF
88SE9235
U42
Marvell Semiconductor
WAKE_N
60
CLKN
59
CLKP
58
N/C_3
57VSS_4
56PRXP0
55PRXN0
54AVDD0
53PTXP0
52PTXN0
51PRXP1
50PRXN1
49AVDD1
48PTXP1
47PTXN1
46VSS_3
45VDD_5
44N/C_4
43ISET
42XTLOUT
41
PERST_N
61VDD_6
62GPIO0
63TST0
64TST1
65TST2
66TST3
67VDDIO_2
68GPIO1
69GPIO2
70VDD_7
71TST4
72TST5
73TST6
74GPIO6
75GPIO7
76
VDD_1
1SPI_DO
2RXP_3
3RXN_3
4VAA2_3
5TXN_3
6TXP_3
7VSS_1
8RXP_2
9RXN_2
10VAA2_2
11TXN_2
12TXP_2
13SPI_CS
14SPI_DI
15VDDIO_1
16SPI_CLK
17GPIO3
18VDD_2
19
XTLIN_OSC
40VAA1
39
TP
38 N/C_2
37 VDD_4
36 N/C_1
35
GPIO5
21
TESTMODE
22
VDD_3
23
RXP_1
24
RXN_1
25
VAA2_1
26
TXN_1
27
TXP_1
28
VSS_2
29
RXP_0
30
RXN_0
31
VAA2_0
32
TXN_0
33
TXP_0
34
GPIO4
20
GND
77
TP49
L24
BLM15GG471SN1D
C447
1NF
C448
2,2UF
C485
100NF
R422
10K
C482
10NF
C460
2,2UF
C422 100NF
C445
100NF
C450
10NF
C483
1NF
R423 0
TP35
C462
10NF
C423 100NF
R425
0
C466
2,2UF
L19
7427927161
R419
4,7K
C451
1NF
C454
10NF
C440
100NF
L25
BLM15GG471SN1D
C481
100NF
R426
6,04K
C463
1NF
TP55
C468
10NF
C488
100uF
C443
100NF
C449
100NF
R421 0
TP40
L16
BLM15GG471SN1D
C472
10NF
C461
100NF
C469
1NF
C452
2,2UF
C442
100NF
L22
BLM15GG471SN1D
C473
10NF
TP54
TP36
C441
100NF
TP41
R420 0
C474
10NF
C489
100NF
C467
100NF
C436 100NF
C420 100NF
C424 100NF
C475
10NF
C455
1NF
TP47
R429
0
R424
100
C437 100NF
R427
0
C477
10NF
R428
0
TP37
C425 100NF
TP42
C478
10NF
C470
2,2UF
C490
100NF
C438 100NF
TST6
PRX_1N
PRX_1P
TST4
PTX_1N
PTX_0P
PTX_1P
S_TXP0
1V80
S0_TXP
S0_TXN
S0_RXP
S_TXN0
TST1
TST0
TST3
TST2
VDD_10
XTLOUT
S0_RXN
CLK25M
SATA_GPIO7
S1_TXP
S1_TXN
VDDIO
S1_RXP
S_TXN1
S_RXN1
S_RXP1
S1_RXN
ISET
S_TXP1
XTL_O
S2_TXP
S2_TXN
S2_RXP
S_TXN2
S_RXN2
S_RXP2
S2_RXN
S_TXP2
PTX_0N
TST5
VDD_10
PRX_1P
S_TXN0
TESTMODE
PTX_1P
PRX_1N
AVDD1
S_RXN0
S_RXP0
VDD_10
S_TXP1
VDD_10
VDD_10
VAA1
PRX_0P
PRX_0N
CLK25M
PTX_1N
VDD_10
AVDD0
S_TXN2
VAA2_2
S_RXN2
GNDPTX_0N
S_TXN3
S_RXN3
S_RXP3
VDD_10
S_TXP3
S_TXP2
VAA2_3
VDDIO
PTX_0P
S_TXP0
S_RXP1
GND
VAA2_0
S_TXN1
VAA2_1
GND
S_RXN1
TST6
TST5
TST4
WAKE_N
GND
VDDIO
PRX_0P
PCLKP
S3_TXP
S3_TXN
S3_RXP
S_TXN3
S_RXN3
S_RXP3
S3_RXN
S_TXP3 PRX_0N
PCLKN
TST1
TST0
TST3
TST2
S_RXP2
SATA_GPIO6
XTLOUT
S_RXP0
S_RXN0
PCLKN
PCLKP
22. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
HDD CONNECTOR
M2 SSD1 PCIEx4 CONNECTOR
NC = PCIe
GND= SATA
3V3
3V3
3V3
3V3
5V
S3_TXP21
S3_TXN21
S3_RXN21
S3_RXP21
S1_TXP21
S1_TXN21
S1_RXN21
S1_RXP21
S0_TXP21
S0_TXN21
S0_RXN21
S0_RXP21
PDETECT15
M2_REF_CLKN36
M2_REF_CLKP36
S2_TXP21
S2_TXN21
S2_RXN21
S2_RXP21
M2_PERP09
M2_PETP09
M2_PERN09
M2_PETN09
M2_PERN19
M2_PETP19
M2_PERP19
M2_PETN19
M2_PERP29
M2_PETP29
M2_PERN29
M2_PETN29
M2_PERP39
M2_PETP39
M2_PERN39
M2_PETN39
M2_CLK_REQ# 36
M2_RSTN 15
Project
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Designed by: Controlled by: approved by:
PCB Code BOM file
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Page title
ACB_0001_0
22 45
Monday, August 10, 2020Friday, November 30, 2018
A30
SATA CONNECTOR
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
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Page title
ACB_0001_0
22 45
Monday, August 10, 2020Friday, November 30, 2018
A30
SATA CONNECTOR
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
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Page title
ACB_0001_0
22 45
Monday, August 10, 2020Friday, November 30, 2018
A30
SATA CONNECTOR
<Author> <Approved by><Cheked by>
<Variant Name>
TP62
R4350
TP56
D7
LED VERDE
C501 100NF
TP57
C509 100NF
R431
10K
TP58
R430
510
TP63
TP59
C505 100NF
C510 100NF
R4360
C511 100NF
C494
1UF
C506 100NF
C499 100NF
C512 100NF R4370
C495
100NF
C507 100NF
C496
22uF
C498 100NF
C508 100NF
C517
22uF
C497
22uF
C513 100NF
C504
22uF
C514 100NF
C516
100NF
C503
100NF
TP60
J13
MDT180M01001
CONFIG_3
1
3.3 V
2GND
3
3.3 V
4PERn3
5
N/A
6PERp3
7
N/A
8GND
9
DAS/DSS
10PETn3
11
3.3 V
12PETp3
13
3.3 V
14GND
15
3.3V
16PERn2
17
3.3 V
18PERp2
19
N/A
20CONFIG_0
21
N/A
22PETn2
23
N/A
24PETp2
25
N/A
26GND
27
N/A
28PERn1
29
N/A
30PERp1
31
N/A
32GND
33
N/A
34PETn1
35
N/A
36
PETp1
37
DEVSLP
38GND
39
N/A
40SATAB+/PERn0
41
N/A
42SATAB-/PERp0
43
N/A
44GND
45
N/A
46SATAA-/PETn0
47
N/A
48SATAA+/PETp0
49
PERST#
50GND
51
CLKREQ#
52REFCLKN
53
PEWAKE#
54REFCLKP
55
MFG1
56GND
57
MFG2
58
N/A
67
SUSCLK
68CONFIG_1
69
3.3 V
70GND
71
3.3 V
72GND
73
3.3V
74CONFIG_2
75
C502
1UF
C515
1UF
TP61
R432 0
R434 0
J12
2
1
3
5
7
9
11
4
6
8
10
12
C500 100NF
R433 0
M2M_SSD1_LED
M2M_SSD1_LED
23. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
ACB_0001_0
PCI Express Gen.2
(90Ohm-differential)
Put close to U1
Do check with crystal vendor
if the value of C35, C36 and R22
are all appropriate.
Put close to CN3
Put close to CN1
USB SS (90Ohm-differential)
USB SS (90Ohm-differential)
USB SS (90Ohm-differential)
USB SS (90Ohm-differential)
USB HS (90Ohm-differential)
Put close to CN2
Put close to U1
Short and broad connection to GND
Don't split R33 into multiple resistors.
USB SS (90Ohm-differential)
USB SS (90Ohm-differential)
USB SS (90Ohm-differential)
Power on Reset
USB SS (90Ohm-differential)
USB HS (90Ohm-differential)
Note:
1. Every Power trace (3.3V_Dual, 1.05V, A3.3V, 3.3V, 3.3VAUX, 12V, 5V, VCCCH1-4) should be broad.
2. 2nd layer of this entire circuit should be grounded.
3. Every high speed signal trace (USB SS/HS, PCI Express) should be wired as shortly as possible.
4. Capacitors C100-116 should be located next to U1,
and connected to GND tightly -- by tracing shortly and broadly.
5. For signal traces, routing priority is as follows;
USB SS > PCI Express > (SATA) > USB HS > (DDR > Ether > PCI, PATA > Other legacy)
6. At any crossing for every trace except ground,
sufficient area of ground plane between each other should be put.
7. Follow the basic of transmission trace pair when routing any signal trace.
> Remove any impairment or discontinuity.
> Keep same length by each other.
> Keep same width and spacing.
8.The differential impedance of nominal value is as follows.
> USB 3.0 / 2.0 --- 90ohm
> PCI express Gen 1.(2.5GT/s) --- 100ohm PCI express Gen 2.(5GT/s) --- 85ohm
PCB trace impedance would be a non-continues value by its design rules.
The differential impedance adopt the nearest value that can be manufactured at PCB
For more information please refer to 'USB3.0 Board Design Guide' in design kit.
USB HS (90Ohm-differential)
Put close to CN4
Low ESR
Power Regulator
1.05V A3.3V A3.3VA3.3V 3V33V3
3V3
3V3
1.05V
3V3
OCI1B 24
PPON1 24
OCI2B 24
OCI4B
PPON4
PPON2 24
OCI3B
PPON3
USB3_PEWAKEB15
U2DM4 25
U2DP4 25
U2DM3 25
U2DP3 25
U3TXDP2 24
U3TXDN2 24
U2DM2 24
U2DP2 24
U3RXDP2 24
U3RDN2 24
U3TXDP1 24
U3TXDN1 24
U2DM1 24
U2DP1 24
U3RXDP1 24
U3RDN1 24
TXP026
TXN026
RXP026
RXN026
REFCLKN326
REFCLKP326
DWNRST3_L26
Project
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Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
USB3 CONTROLLER
0
A2
23 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
USB3 CONTROLLER
0
A2
23 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
USB3 CONTROLLER
0
A2
23 45
Monday, August 10, 2020
<Variant Name>
C541
10NF
Y5
24MHz
1
3
2
4
C551
100NF
C546
100NF
C529
100NF
C520
10uF
L27
BLM18EG601SN1
C533
10NF
C553
100NF
C554
1UF
R447
10K
R445 0
U43 RT8058GQW
PGND
1
PGND
2
PGND
3
FB
4
GND
5NC
6EN
7NC
8
VDD
9 PVDD
10 PVDD
11 PVDD
12
LX
13
LX
14
LX
15
NC
16
PGND
17
R444 0
C549
10NF
TP72
C547
100NF
C537
10NF
C538
10NF
C532
10NF
C539
10NF
R446
47K
C556
100NF
TP70
C543
10NF
C559
8pF
C545
10NF
R448
10K
R440
68K
TP69
uPD720201
U44
XT2
30 XT1
31
PONRSTB
14
PERSTB
2
PEWAKEB
3
PECREQB
13
AVDD33
32
AVDD33
6
PECLKP
4
PECLKN
5
PETXP
7
PETXN
8
PERXP
10
PERXN
11
IC(L)
34
SPISCK
18
SPICSB
17
SMIB
1
VDD33
66
VDD33
57
VDD33
40
VDD33
29
VDD33
49
VDD33
15
VDD10
63
VDD10
60
VDD10
43
VDD10
54
VDD10
46
VDD10
37
VDD10
28
VDD10
12
VDD10
9
EP
SPISI
19
SPISO
16
RREF
33
U3TXDP4
61
U3TXDN4
62
U3RXDP4
64
U3RXDN4
65
U2DP3
58
U2DM3
59
U3TXDP3
52
U3TXDN3
53
U3RXDP3
55
U3RXDN3
56
U2DP4
67
U2DM4
68
OCI4B
20
OCI3B
22
PPON4
21
PPON3
23
U3TXDP2
44
U3TXDN2
45
U2DM2
51
U3RXDP2
47
U3RXDN2
48
OCI2B
24
OCI1B
26
PPON2
25
PPON1
27
U3TXDP1
35
U3TXDN1
36
U2DM1
42
U2DP1
41
U3RXDP1
38
U3RXDN1
39
U2DP2
50
TP73
C519
22uF
C557
100NF
R449
1,65K
C544
10NF
C531
10NF
C558
8pF
C535
10NF
D8
BAS70LT1G
13
R439
51K
R450
680
C527
100NF
C540
10NF
R442 0
C534
10NF
C522
10uF
TP66
C524
100NF
C521
1UF
C552
100NF
C560
100NF
C536
10NF
R441 0
C555
100nF
C530
100NF
TP74
R443 0
C526
100NF
C518
22uF
C561
100NF
L26
3.3uH
L28
BLM18EG601SN1
C542
10NF
TP68
R438
0
TP65
C548
10NF
C525
100NF
TP71
U45
MX25L512EMI-10G
SCK
6
CS#
1
SI
5WP#
3 SO
2
HOLD#
7
GND
4
VCC
8
TP67
TP64
C528
100NF
C523
100NF
C550
100NF
SPISO
OCI4B
OCI3B
PPON4
PPON3
OCI2B
OCI1B
PPON2
PPON1
SPISCK
SPICSB
SPISI
SPISO
SPISCK
SPISI
SPICSB
24. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
ACB_0001_0
SS/CL
SS/CL
VCCCH2
VCCCH1
5V
VCCCH2
VCCCH1
3V3
PPON223
OCI2B23
PPON123
OCI1B23
U2DM123
U2DP123
U2DM223
U2DP223
U3TXDP223
U3TXDN223
U3RXDP223
U3RDN223
U3TXDP123
U3TXDN123
U3RXDP123
U3RDN123
Project
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PCB Code BOM file
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Page title
USB3 PORTS
0 A324 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
USB3 PORTS
0 A324 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
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Page title
USB3 PORTS
0 A324 45
Monday, August 10, 2020
<Variant Name>
U46
RCLAMP3346P.TNT
CH1
1
GND
2
CH2
3
CH3
4 CH4
5
CH5
6
CH6
7
FL5
DLP11SN161SL2
1 2
34
U48
AP2191SG-13
OC
5 GND
1
OUT
7EN
4 IN
3IN
2
OUT
6
NC
8
FL6
DLP11SN161SL2
1 2
34
L30
BLM18EG601SN1
FL3
DLP11SN161SL2
1 2
34
C562
1UF
R454
0
R455
0
FL8
DLP11SN161SL2
1 2
34
Standard-A
CN1
SS-52000-01
VBUS
1
D-
2
D+
3
GND_D
7
SSRX-
5
SSRX+
6
GND
4
SSTX-
8
SSTX+
9
SHIELDSHIELD
U47
AP2191SG-13
OC
5 GND
1
OUT
7EN
4 IN
3IN
2
OUT
6
NC
8
R452
10K
R451
0
C565
1UF
Standard-A
CN2
SS-52000-01
VBUS
1
D-
2
D+
3
GND_D
7
SSRX-
5
SSRX+
6
GND
4
SSTX-
8
SSTX+
9
SHIELDSHIELD
C564
22uF
U49
RCLAMP3346P.TNT
CH1
1
GND
2
CH2
3
CH3
4 CH4
5
CH5
6
CH6
7
R453
10K
C563
22uF
C567
22uF
C566
22uF
L29
BLM18EG601SN1
FL7
DLP11SN161SL2
1 2
34
FL4
DLP11SN161SL2
1 2
34
25. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
ACB_0001_0
3V3
5V
1V0
PCIE_LAN_RXP26
PCIE_LAN_RXN26
PCIE_LAN_TXP26
PCIE_LAN_TXN26
REFCLKN626
REFCLKP626
CLKREQ_L626
DWNRST1_L26
U2DM423
U2DP423
U2DM323
U2DP323
HUB_USB4_DN11
HUB_USB4_DP11
Project
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PCB Code BOM file
Sheet of REV.
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Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ETHERNET_CARD
0 A425 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ETHERNET_CARD
0 A425 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
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Page title
ETHERNET_CARD
0 A425 45
Monday, August 10, 2020
<Variant Name>
R456 0
FL10
DLP11SN161SL2
1 2
34
FL11
DLP11SN161SL2
1 2
34
J14
54132-3062
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TP75
FL9
DLP11SN161SL2
1 2
34
26. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
near to chipset
UPSTREAM X4
PORT
UPSTREAM PORT:
Port0: lane 0-3
DOWN_STREAM_PORT
Port1: lane4-7
Port2 : Lane 8
Port3: Lane 9
Port4: Lane 10
Port5: Lane 11
M2 WIFI
M2WWAN/3G/LTE
AUDIO
USB3 PCIEUSB3 PCIE
AUDIO
Port1: lane4-7
M2 WIFI
SMBUS ADDRESS
DEBUG MODE SELECT
STRAP PIN SETTING
3V3
3V3
3V3
3V3
3V3
3V3
RXP023
RXN023
RXN133
RXN227
L4_RXN28
RXP133
RXP227
L4_RXP28
DWNRST3_L 23
DWNRST2_L 28
DWNRST1_L 25
REFCLKIN_N 36
REFCLKIN_P 36
PCIE_SMBCLK32
PCIE_SMBDATA32
BRIDGE_RXP0 9BRIDGE_TXP09
BRIDGE_RXN0 9BRIDGE_TXN09
BRIDGE_RXP1 9BRIDGE_TXP19
BRIDGE_RXN1 9BRIDGE_TXN19
BRIDGE_RXP2 9BRIDGE_TXP29
BRIDGE_RXN2 9BRIDGE_TXN29
BRIDGE_RXP3 9BRIDGE_TXP39
BRIDGE_RXN3 9BRIDGE_TXN39
DWNRST4_L 33
REFCLKN226,28
REFCLKP226,28
REFCLKN323,26
REFCLKP323,26
REFCLKP426,33
REFCLKP526,27
REFCLKP625,26
REFCLKN426,33
REFCLKN526,27
REFCLKN625,26
REFCLKP2 26,28
REFCLKN2 26,28
REFCLKP3 23,26
REFCLKN3 23,26
REFCLKP4 26,33
REFCLKN4 26,33
REFCLKP5 26,27
REFCLKN5 26,27
REFCLKP6 25,26
REFCLKN6 25,26
PCIE_BRIDGE_RSTN15
CLKREQ_L2 28
TXP0 23
TXN0 23
L4_TXP 28
L4_TXN 28
TXP2 27
TXN2 27
TXP1 33
TXN1 33
PCIE_LAN_RXP 25
PCIE_LAN_RXN 25
PCIE_LAN_TXP25
PCIE_LAN_TXN25
L5_RXP28
L5_RXN28
L5_TXP 28
L5_TXN 28
DWNRST5_L 27
REFCLK2P36
REFCLK2N36
CLKREQ_L5 27
CLKREQ_L6 25
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
26 45
Monday, August 10, 2020Tuesday, June 25, 2013
A20
PCIE BRIDGE
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
26 45
Monday, August 10, 2020Tuesday, June 25, 2013
A20
PCIE BRIDGE
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
26 45
Monday, August 10, 2020Tuesday, June 25, 2013
A20
PCIE BRIDGE
<Author> <Approved by><Cheked by>
<Variant Name>
R47833
C573
100NF
R521
10K
R466
49,9
C585
100NF
R49133
C588
100nF
R512
10K
R503
10K
TP83
TP88
C587
100NF
C592
100NF
R510
10K
C591
100NF
C571
100NF
TP90
R458
1,43K
R48133
TP91
C575
100NF
R511
10K
R463
49,9
TP89
C584
100NF
R502
10K
R484
10K
C590
100NF
TP92
R48033
C586
100NF
TP84
U51
25AA256
VCC
8
HOLD
7
WP
3
GND
4
CS
1
SK
6
DI
5
DO
2
R464
49,9
R513
10K
C574
100NF
R505
10K
R474
1,43K
TP85
R518 10K
R486
10K
R47533
TP87
TP86
C577
100NF
R472
49,9
R514
0
TP76
C576
100NF
R520 10K
C568
100NF
R493
10K
R526
10K
R48533
TP93
C581
100NF
TP78
R504
10K
R471
49,9
R47333
R488
10K
C570
100NF
R524 10K
R517 10K
TP80
R497
10K
R48333
R523
10K
C583
100NF
R515
0
R470
49,9
R461
49,9
TP82
R495
475R
C578
100NF
C579
100NF
R506
10K
R499
10K
R490
10K
R482
10K
R469
49,9
R519 10K
R496
10K
R462
49,9
R47733
U50B
PI7C9X2G612GP
DBO4
N1 DBO3
M4
DBO2
M3
NC1
N2
NC2
P1
CLKBUF_PD
P2
DBO1
L3
CLKREQ_L4
D12
DBO0/PL_512B
K3
GPIO0
A2GPIO1
A1GPIO2
B2GPIO3
B1GPIO4
C5GPIO5
C4GPIO6
C3GPIO7
D3
CLKREQ_L5
C12
CLKREQ_L6
C11
CLKREQ_L1
C14
SCL_I2C
J11
SDA_I2C
K11
CLKREQ_L2
C13
CLKREQ_L3
B14
EECK
L12
EEDO
K12
EECS_L
M12 EEDI
M11
SHPCINT_L
B13
SHDA_I2C
A14
SHCL_I2C
A13
SWG_LVL
J12
R525
10K
R48933
R507
10K
R468
49,9
C580
100NF
R498
10K
R47633
TP77
C569
100NF
R522 10K
R48733
TP94
R467
49,9
C582
100NF
R509
10K
R459
49,9
TP79
R501
10K
R494
10K
TP95
R527
10K
U50C
PI7C9X2G612GP
PERST_L
M13
REFCLKN0
P7 REFCLKP0
N7
DWNRST_L1
P14
DWNRST_L2
P13
DWNRST_L3
N14
PERP08
C1
PERN08
C2 PETP08
D1
PETN08
D2
PERP11
M1
PERN11
M2 PETP11
L1
PETN11
L2
PERP10
K1
PERN10
K2 PETP10
J1
PETN10
J2
PERP09
E1
PERN09
E2 PETP09
F1
PETN09
F2
NC5
H3
REXT2
H1
REXTGND2
H2
REFCLKOP3
F13
REFCLKOP1
D13
REFCLKON3
F14
IREF
E12
REFCLKIN
G14REFCLKIP
G13
REFCLKON2
E14
REFCLKOP2
E13
REFCLKON1
D14
NC3
M8
NC4
C7
DWNRST_L4
N13
DWNRST_L5
M14
REXT1
A7
REXTGND1
B7
REXT0
P8
REXTGND0
N8
REFCLKP1
B8
REFCLKN1
A8
REFCLKP2
G2
REFCLKN2
G1
PETP07
A4
PETN07
B4
PETP06
A6
PETN06
B6
PETP05
A9
PETN05
B9
PETP04
A11
PETN04
B11
PETP03
P11
PETN03
N11
PETP02
P9
PETN02
N9
PETP01
P6
PETN01
N6
PETP00
P4
PETN00
N4
PERP07
A3
PERN07
B3
PERP06
A5
PERN06
B5
PERP05
A10
PERN05
B10
PERP04
A12
PERN04
B12
PERP03
P12
PERN03
N12
PERP02
P10
PERN02
N10
PERP01
P5
PERN01
N5
PERP00
P3
PERN00
N3
REFCLKON4
H14
REFCLKOP4
H13
REFCLKON5
J14
REFCLKOP5
J13
REFCLKON6
K14
REFCLKOP6
K13
REFCLKON7
L14
REFCLKOP7
L13
R516
10K
TP96
R460
49,9
TP81
C572
100NF
R457
1,43K
R47933
R465
49,9
R49233
R508
10K
R500
10K
C589
100nF
SMBDATA
SMBCLK
GPIO7
GPIO6
GPIO5
GPIO3
GPIO2
GPIO1
GPIO0
CLKQ1_N
CLKQ1_P
DWNRST1_L
DWNRST3_L
DWNRST2_L
REFCLKIN_N
REFCLKIN_P
RXP0
RXN0
L4_RXP
L4_RXN
RXP2
RXN2
RXP1
RXN1
REFCLK1N
REFCLK1P
GPIO4
EEDI
EECS_L
EECK
EEDO
EECS_L
EEDI
EEDO
EECK
DBO3
DBO4
DWNRST4_L
DWNRST5_L
CLKQ1_N_5
CLKQ1_P_4
CLKQ1_N_7
CLKQ1_P_6
CLKQ1_P_1
CLKQ1_N_2
CLKQ1_P_3
CLKQ1_N_4
CLKQ1_P_5
CLKQ1_N_6
CLKQ1_P_7
CLKQ1_N_1
CLKQ1_N_3
CLKQ1_P_2
CLKQ0_P
CLKQ0_N
REFCLK0P
REFCLK0N
CLKQ0_P
CLKQ0_N
CLKQ1_N
CLKQ1_P
REFCLK0P
REFCLK0N
REFCLK1P
REFCLK1N
DBO0/PL_512B
DBO1
DBO2
SWG_LV
CLKREQ_L1
CLKREQ_L2
CLKREQ_L3
CLKREQ_L4
CLKREQ_L5
CLKREQ_L6
SWG_LV
CLKREQ_L1
CLKREQ_L2
CLKREQ_L3
CLKREQ_L4
CLKREQ_L5
CLKREQ_L6
CLKBUF_PD
HPINT
HPSDA
HPSCL
TXP0
TXN0
L4_TXP
L4_TXN
TXP2
TXN2
TXP1
TXN1
L5_RXP
L5_RXN
L5_TXP
L5_TXN
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
DBO0/PL_512B
CLKBUF_PD
27. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
M2 WLAN+BT PCIEx1 CONNECTOR
5V
3V3
3V3
3V3
3V3
WLAN_EN 15
PE_WAKEN15 BT_EN 15
WLAN_PWR_EN15
TXP226
TXN226
RXP226
RXN226
UART2_RTSB 14
UART2_CTSB 14
UART2_TXD 14
UART2_RXD 14
WLAN_WAKEUP 15,27
WLAN_WAKEUP15,27
CLKREQ_L526
HUB_USB2_DN11
HUB_USB2_DP11
REFCLKN526
REFCLKP526 DWNRST5_L 26
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
27 45
Monday, August 10, 2020Friday, December 28, 2018
A30
M2.WLAN CONNECTOR
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
27 45
Monday, August 10, 2020Friday, December 28, 2018
A30
M2.WLAN CONNECTOR
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
27 45
Monday, August 10, 2020Friday, December 28, 2018
A30
M2.WLAN CONNECTOR
<Author> <Approved by><Cheked by>
<Variant Name>
C596
100NF
E KEY
J15
MDT180E01001
GND
1 +3.3V
2
USB_D+
3 +3.3V
4
USB_D-
5 LED1#
6
GND
7 PCM_CLK
8
WGR_D1N
9 PCM_SYNC/LCP_RSTN
10
WGR_D1P
11 PCM_IN
12
GND
13 PCM_OUT/CLKREQ0
14
WGR_D0N
15 LED2
16
WDR_D0P
17 GND
18
GND
19 UART_WAKE_N
20
WGR_CLKN
21 UART_RX/BRI_RSP
22
WGR_CLKP
23
GND
75
WT_CLKP
73
WT_CLKN
71
GND
69
WT_D0P
67
WT_D0N
65
GND
63
WT_D1P
61
WT_D1N
59
GND
57
PEWAKE0_N
55
CLKREQ0_N
53
GND
51
REFCLKN0
49
REFCLKP0
47
GND
45
PERN0
43
PERP0
41
GND
39
PETN0
37
PETP0
35
GND
33
3V3
74
3V3
72
PEWAKE1_N
70
CLKREQ1_N
68
PERST1_N
66
REFCLK0
64
IRQ_N(I)
62
I2CLK(IO)
60
I2C_DATA(IO)
58
W_DISABLE1_N(O)
56
W_DISABLE2_N(O)
54
PERST0_N(O)
52
SYSCLK(32KHZ)(O)
50
COEX1_TXD(IO)1.8V
48
COEX2_RXD(IO)1.8V
46
COEX3(IO)1.8V
44
CLKINK_CLK
42
CLKINK_DATA
40
CLINK_RESET
38
UART_RTS/BRI_DT
36
UART_CTS/RGI_RSP
34
UART_TX/RGI_DT
32
R535
10K
D9
LED VERDE
R537
10K
U52
TPS79633
VIN
2
EN
1
GND
3
VOUT
4
NR/FB
5
GND
6
R538
510
C597
150PF
M12
FDV301N1
23
R5320
D10
LED VERDE
R533
10K
R5310
R539
510
U53
32.768kHZ
ON
1
GND
2
OUT
3
VDD
4
C598
100NF
C593
1UF
M13
FDV301N1
23
R5340
C594
100NFR528
10K
R5360
R5300
R529
10K
C595
1UF
28. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
GPIO1_IO27
NOTE:
This design assumes a normal loading on the MPCIE_3V3 rail of up to 1A.
PF0100 SW2 can supply a maximum of 2A current. If more than 1A loading
is desired, the designer must consider other load on the GEN_3V3 rail
and depopulate other loads to allow additional loading on the MPCIE_3V3
rail. The MPCIE_1V5 rail is allowed a maximum of 100 mA.
M2_PCIe Load Switch
Componente lato bottom
SIM HOLDERSIM ON CHIP
3V3
GND
GND
3G_3V3
3G_3V3
3G_3V3
3G_3V3
PCIE_PWR_ON15
PWR_ON_OFF 15
3G_EN 15
HUB_USB3_DN11
HUB_USB3_DP11
L5_RXP26
L5_RXN26
L4_RXP26
L4_RXN26
L5_TXP26
L5_TXN26
L4_TXP26
L4_TXN26
REFCLKN226
REFCLKP226
CLKREQ_L2 26
DWNRST2_L 26
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
28 45
Monday, August 10, 2020Friday, December 28, 2018
A30
3G/LTE MODEM
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
28 45
Monday, August 10, 2020Friday, December 28, 2018
A30
3G/LTE MODEM
<Author> <Approved by><Cheked by>
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
ACB_0001_0
28 45
Monday, August 10, 2020Friday, December 28, 2018
A30
3G/LTE MODEM
<Author> <Approved by><Cheked by>
<Variant Name>
C611
33PF
R542
100K
C609
33PF
R552 0
R553 0
R543
10K
R540 0
C603
100NF
R550
0
R547 0
R545 0
R551 0
C601
100uF
C599
100uF
C614
33PF
R549 0
U55
m2m air
VSS
1
NC1
2
I/O
3
EP
9
NC
5
CLK
6
RST
7
NC2
4
VDD
8
FL12
DLP11SN161SL2
1 2
34
C612
1UF
B KEY
J16
MDT180B01001
CONFIG_3
1 +3.3V
2
GND
3 +3.3V
4
GND
5 CARD_POFF#
6
SUB_DP
7 W_DISABLE#
8
USB_DN
9 GPIO_9
10
GND
11
GPIO_5
20
CONFIG_0
21 GPIO_6
22
GPIO_11
23 GPIO_7
24
GPIO_12
25 GPIO_10
26
GND
27 GPIO_8
28
PERN1/USB3.0-RX-
29 UIM_RESET
30
PERP1/USB3.0-RX+
31
CONFIG_2
75
GND
73
GND
71
CONFIG_1
69
RESET#1.8V
67
ANTCTL3_1.8V
65
ANTCTL2_1.8V
63
ANTCTL1_1.8V
61
ANTCTL0_1.8V
59
GND
57
REFCLKP
55
REFCLKN
53
GND
51
PETP0/SATA-A+
49
PETN0/SATA-A-
47
GND
45
PERP0/SATA-B-
43
PERN0/SATA-B+
41
GND
39
PETP1/USB3.0-TX+
37
PETN1/USB3.0-TX-
35
GND
33
3V3
74
3V3
72
3V3
70
SUSCLK(32KHZ)
68
SIM_DETECT
66
COEX1_1V8
64
COEX2_1V8
62
COEX3_1V8
60
NC1
58
NC0
56
PEWAKE#
54
CLKREQ#
52
PERST#
50
GPIO_4
48
GPIO_3
46
GPIO_2
44
GPIO_1
42
GPIO_0
40
DEVSLP
38
UIM_PWR
36
UIM_DATA
34
UIM_CLK
32
C610
33PF
J17
SIM Holder 6p
C1/VCC
1 C2/RST
3 C3/CLK
5
C5/GND
2C6/VPP
4C7/IO
6
CD1
7
CD2
8
R554 0
C605
100NF
R546 0
R541
100K
C607
100NF
C606
100NF
TVS1
IP4221CZ6-S,115
1
2 5
43
6
C608
100NF
C604
100NF
C602
100uF
C600
100uF
C613
100NF
U54
FDC6331L
V_IN_R1
4
ON_OFF
5
R1_C1
6
R2
1
V_OUT_C1_2
2
V_OUT_C1_1
3
R544
1K
R548
10K
SIM_DET
PCIE_PWR_ON
PCIE_PWR_R1 PCIE_PWR_R2
SIM_VCC
SIM_RESET
SIM_DATA SIM_CLK
PCI3_UIM_CLK SIM_CLK
PCIe_UIM_DATA SIM_DATA
PCIe_UIM_RST SIM_RESET
SIM_VCCPCIe_UIM_PWR
SIM_RESET
SIM_VCC
SIM_DATA SIM_CLK
PCI3_UIM_CLK
PCIe_UIM_DATA
PCIe_UIM_RST
PCIe_UIM_PWR
SIM_DET
29. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
ACB_0001_0
1.0V Decoupling Capacitors
3.3V Decoupling Capacitors
POWER PAD TO GND
1.0V
1.0VAUX
1.0VAUX
1.0V
3V3
1.0V
1.0V 1.0V
1.0V 1.0V
1.0VAUX
3V33V3
3V3 3V3
3V3
3V3
3V3
3V3 BRIDGE_1V0
BRIDGE_1V0
3V3
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PCIE BRIDGE POWER
0 A329 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PCIE BRIDGE POWER
0 A329 45
Monday, August 10, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PCIE BRIDGE POWER
0 A329 45
Monday, August 10, 2020
<Variant Name>
C654
10uF
U56
TPS62067
PGD
6
FB
4
EN
5
PGND
1
Pvin
8
SW
2
EP
9
AGND
3
Avin
7
C642
1UF
C690
100NF
C658
100NF
C651
10NF
C667
1UF
C615
10uF
C681
100NF
C679
10uF
C659
10NF
C665
10NF
C645
1UF
C650
100NF
C669
10NF
U50A
PI7C9X2G612GP
AGND1
C6
AGND2
C9
AGND3
C10
AGND4
E3
AGND5
F3
AGND6
J3
AGND7
M5
AGND8
M6
AGND9
M9
AGND10
M10
VDDC1
D5
VDDC3
D9
VDDC4
D10
VDDC5
E4
VDDC6
E11
VDDC7
F4
VDDC8
F11
VDDC9
G11
AVDD1
D7
AVDD2
D8
AVDD5
L7
AVDD3
G4
AVDD4
H4
VDDR1
D4
VDDR2
D11
VDDC2
D6
VDDR3
L4
VDDR4
L11
AVDDH1
C8
VDDC10
H11
VDDC11
J4
VDDC12
K4
VDDC13
L5
VDDC14
L6
VDDC15
L9
VDDC16
L10
AVDD6
L8
AVDDH2
G3
AVDDH3
M7
CVDDR1
F12
CVDDR2
G12
CVDDR3
H12
DGND1
E5
DGND2
E6
DGND3
E7
DGND4
E8
DGND5
E9
DGND6
E10
DGND7
F5
DGND8
F6
DGND9
F7
DGND10
F8
DGND11
F9
DGND12
F10
DGND13
G5
DGND14
G6
DGND15
G7
DGND16
G8
DGND17
G9
DGND18
G10
DGND19
H5
DGND20
H6
DGND21
H7
DGND22
H8
DGND23
H9
DGND24
H10
DGND25
J5
DGND26
J6
DGND27
J7
DGND28
J8
DGND29
J9
DGND30
J10
DGND31
K5
DGND32
K6
DGND33
K7
DGND34
K8
DGND35
K9
DGND36
K10
R559
120K
C621
10NF
C629
1UF
C673
10NF
C624
10NF
C668
100NF
C627
10NF
C616
1UF
C639
100NF
L31
1uH
C662
100NF
C618
10NF
C660
10uF
C682
22uF
C649
1UF
C633
100NF
C680 22PF
C666
10uF
C626
100NF
C663
10NF
C617
100NF
C640
10NF
C631
10NF
C685
10uF
R5560
C623
100NF
C671
1UF
C683
22uF
C646
100NF
C638
10NF
C661
1UF
C634
10NF
C670
10uF
R558
47K
C641
10uF
C653
10NF
C664
100NF
C684
22uF
C622
1UF
C687
100NF
C625
1UF
C656
100NF
C676
100NF
C647
10NF
C672
100NF
C620
100NF
C657
10NF
C689
1UF
R560
180K
C628
10uF
C637
100NF
C675
1UF
R5570
C655
1UF
C632
1UF
C688
10NF
C619
1UF
C636
1UF
C677
10NF
C635
10uF
C643
100NF
C686
1UF
C648
10uF
C652
100NF
R5550
C630
100NF
C644
10NF
C674
10uF
C678
100NF