APB2SPI

1. Understanding the logic

2. Goal
Objective: Design and implementation of APB to SPI converter by using Verilog HDL.
Description: APB to SPI converter architecture shows the data transfer from APB protocol to SPI. The data gets
converted from parallel to serial and handled with
respective clock domains.
The main parts of the SPI are status, control, baud rate, control status and data
registers, shifter logic, baud rate generator, master control logic and asynchronous FIFO (Transmission FIFO and Receiver
FIFO). Depending on paddress the data is transferred from APB(parallel data) with respect to the main clock to SPI. SPI
shifter convert this data in serial manner to MOSI. At the same time the MISO also started shifting serial data to
shifter(SIPO), shifter started sending data to fifo. According to Paddr the Asynchronous FIFO data is sent to APB. Our
design acts as an interface between APB and SPI which are the popular serial protocols for communication between ICs.

3. APB to SPI

4. Introduction
• Advanced Peripheral Bus (APB) is the part of Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a
low-cost interface and it is optimized for minimal power consumption and reduced interface complexity. Unlike AHB, it is a
Non-Pipelined protocol, used to connect low-bandwidth peripherals. Mostly, used to connect the external peripheral to the
SOC. In APB, every transfer takes at least two clock cycles (SETUP Cycle and ACCESS Cycle) to complete. It can also
interface with AHB and AXI protocols using the bridges in between.
• The above diagram depicts a block diagram of a System. The High-performance ARM processor is the Core of the
system. The other components like High-bandwidth on-chip RAM, DMA bus master and High-bandwidth Memory Interface
are connected to the Core by System bus,which is AHB in this case. The other low bandwidth peripherals like UART,
Timer, Keypad and PIO are connected to the System bus through the Bridge by using Peripheral bus, here it is APB bus.
In this scenario, the Bridge acts as the AHB Slave corresponding to the Core Master. And it also acts as the APB Master
corresponding to remaining low-bandwidth external peripherals.

5. Timing Diagrams
• The components used in timing diagrams are explained in the
figure Key to timing diagram conventions. Variations have
clear labels, when they occur. Do not assume any timing
information that is not explicit in the diagrams.
• Shaded bus and signal areas are undefined, so the bus or
signal can assume any value within the shaded area at that
time. The actual level is unimportant and does not affect
normal operation.
• Timing diagrams sometimes show single-bit signals as HIGH
and LOW at the same time and they look similar to the bus
change shown in Key to timing diagram conventions. If a
timing diagram shows a single-bit signal in this way then its
value does not affect the accompanying description.
Caption

6. Signal Descriptions
PADDR[31:0] – Address bus from Master to Slave, can be up 32 to bit wide
PCLK – Generally System clock is directly connected to this
PENABLE – Indicates the second and subsequent cycles of transfer. When PENABLE is asserted, the ACCESS phase in
the transfer starts.
PRDATA[31:0] – Read data us from Slave to Master, can be up to 32 bit wide
PREADY – It is used by the slave to include wait states in the transfer. i.e. whenever slave is not ready to complete the
transaction, it will request the master for some time by de-asserting the PREADY.
PRESETn – Active Low Asynchronous Reset
PSELx – Slave select signal, there will be one PSEL signal for each slave connected to master. If master connected to ‘n’
number of slaves, PSELn is the maximum number of signals present in the system. (Eg: PSEL1,PSEL2,..,PSELn)
PSLVERR – Indicates the Success or failure of the transfer. HIGH indicates failure and LOW indicates Success
PWDATA[31:0] – Write data bus from Master to Slave, can be up to 32 bit wide
PWRITE – Indicates Write when HIGH, Read when LOW
System bus slave Interface – This is the System bus interface which transfers the AHB/AXI transactions to APB Bridge

7. Write Transfers
No wait States
This section describes the following types of write transfer:
• With no wait states
• With wait states
All signals shown in this section are sampled at the rising edge of PCLK.
With no wait states
he Setup phase of the write transfer occurs at T1. The select signal, PSEL, is
asserted, which means that PADDR, PWRITE and PWDATA must be valid.
The Access phase of the write transfer is shown at T2. where PENABLE is
asserted. PREADY is asserted by the Completer at the rising edge of PCLK
to indicate that the write data will be accepted at T3. PADDR, PWDATA, and
any other control signals, must be stable until the transfer completes.
At the end of the transfer, PENABLE is deasserted. PSEL is also deasserted,
unless there is another transfer to the same peripheral.

8. Write Transfers
With wait States
During an Access phase, when PENABLE is HIGH, the Completer
extends the transfer by driving PREADY LOW. The following signals
remain unchanged while PREADY remains LOW:
• Address signal, PADDR
• Direction signal, PWRITE
• Select signal, PSELx
• Enable signal, PENABLE
• Write data signal, PWDATA
• Write strobe signal, PSTRB
• Protection type signal, PPROT
• User request attribute, PAUSER
• User write data attribute, PWUSER
PREADY can take any value when PENABLE is LOW. This ensures
that peripherals that have a fixed two cycle access can tie PREADY
HIGH.

9. Read Transfers
No wait transfers
Two types of read transfer are described in this section:
• With no wait states
• With wait states
All signals shown in this section are sampled at the rising edge of PCLK.
The timing of the address, PADDR, write, PWRITE, select, PSEL, and
enable, PENABLE, signals are the same as described in Write transfers on
page 3-20. The Completer must provide the data before the end of the read
transfer.

10. Read Transfers
wait transfers
The transfer is extended if PREADY is driven LOW
during an Access phase. The following signals remain
unchanged while PREADY remains LOW:
• Address signal, PADDR
• Direction signal, PWRITE
• Select signal, PSEL
• Enable signal, PENABLE
• Protection signal, PPROT
• User signal, PAUSER
shows that two cycles are added using PREADY.
However, any number of additional cycles can be added,
from zero upwards.

11. Write Transfer
An example of a failing write transfer that completes with an error.

12. Read Transfer
A read transfer can also complete with an error response, indicating that there is no valid read data available.
A read transfer completing with an error response.

13. Operating States
The state machine operates through the following states:
IDLE SETUP
ACCESS
This is the default state of the APB interface.
When a transfer is required, the interface moves into the SETUP state, where the appropriate select signal,
PSELx, is asserted. The interface only remains in the SETUP state for one clock cycle and always moves
to the ACCESS state on the next rising edge of the clock.
The enable signal, PENABLE, is asserted in the ACCESS state. The following signals must not change in
the transition between SETUP and ACCESS and between cycles in the ACCESS state:
• PADDR
• PPROT
• PWRITE
• PWDATA, only for write transactions
• PSTRB
• PAUSER
• PWUSER
Exit from the ACCESS state is controlled by the PREADY signal from the Completer:
If PREADY is held LOW by the Completer, then the interface remains in the ACCESS state.
If PREADY is driven HIGH by the Completer then the ACCESS state is exited and the bus returns to the
IDLE state if no more transfers are required. Alternatively, the bus moves directly to the SETUP state if
another transfer follows.

14. FSM Code Snippet
always@(posedge pclk or negedge preset )begin
if(!preset)
begin
state <=IDLE;
prdata <=1'b0;
pready <=1'b0;
spi_data_reg<=1'b0;
end
else begin
case(state)
IDLE:
begin
if(psel==1'b1)
begin
if(pwrite==1'b1)begin
state<=WRITE_ENABLE;
if(!fifo_full && penable)begin
pready<=1'b1;
end
else
pready<=1'b0;
end
else begin
state<=READ_ENABLE;
if(psel && penable && !pwrite)
pready<=1'b1;
else if(rx_fifo_empty && penable )begin
pready<=1'b1;
end
else
pready<=1'b0;
end
end
end
WRITE_ENABLE:begin
if(psel && penable && pwrite)begin
case(paddr)
8'h00: spi_cntrl_reg1 <=pwdata;
8'h01: spi_cntrl_reg2 <=pwdata;
8'h02: spi_baudrate_reg <=pwdata;
8'h04: spi_data_reg <=pwdata;
default: spi_data_reg <=pwdata;
endcase
end
pready<=1'b0;
state<=IDLE;
end
READ_ENABLE:begin
if(psel && penable && !pwrite)begin
prdata <= prdata_from_spi;
pready <= 1'b0;
state <= IDLE;
end
end
default: begin
state <= IDLE ;
pready<=1'b0;
end
end
end

15. Calculation of Depth
Asynchronous FIFO
Lets assume the frequencies and Brust length as:
Read frequency= 100MHZ Write frequency= 200MHZ Burst length= 60
Calculation of depth:
Time required to write one data item= 1/200 =5ns
Time required to write all the data in the burst = 5ns*60 = 300ns
Time required to read one data item = 1/100 = 10ns
So, for every 10ns, the module is going to read one data in the burst
So, in period of 300ns, 60 number of data items can be written
Number of data items can be read in the duration of 300ns = 300ns/10ns = 30
So, the Asynchronous FIFO which must be in this scenario must be capable of storing 30bits So, the minimum Depth of the FIFO
should be 30
2^n=2^5 n=5
Address = (n-1) = 4
Pointer (rptr &wptr) = (n) = 5
We will take one bit extra for pointer to get full condition and empty condition.

16. SPI
SPI-Serial Peripheral Interface
• SPI is Serial Bus communication Protocol
• It was first developed by Motorola in late 1980 and it is most popular serial
synchronous bus protocol for short distance communication
• Sometimes SPI called as four-wired serial bus and each bus has a specific
role and importance.
• The SPI can be multi-slave but it cannot be multi master that means in SPI
there must be only one master which control the all communication event and
communication is always started by master

17. Features
The SPIV3 includes these distinctive features:
• Master mode and slave mode
• Bidirectional mode
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Double-buffered data register
• Serial clock with programmable polarity and phase
• Control of SPI operation during wait mode

18. • The SPI is four wire-based protocol, below are SPI pins used to interface to external
devices
• MOSI (Master OUT-Slave In)
• MISO (Master In- Slave Out )
• SCL (Serial clock which produces by the master)
• SS[n] (Slave select line which use to select specific slave during the communication)
SPI MASTER SPI SLAVE
SCLK
MOSI
MISO
SS
SS
MISO
MOSI
SCLK

19. Modes of operation
The SPI functions in three modes, run, wait, and stop.
• Run Mode
This is the basic mode of operation.
• Wait Mode
SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In
wait mode, if the SPISWAI bit is clear, the SPI operates like in Run Mode. If the SPISWAI bit is set, the SPI goes into a power
conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress
stops, but is resumed after CPU goes into Run Mode. If the SPI is configured as a slave, reception and transmission of a byte
continues, so that the slave stays synchronized to the master.
• Stop Mode
The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission in
progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a
byte continues, so that the slave stays synchronized to the master.

20. External Signal Description
External Signal Description
This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The SPIV3
module has a total of four external pins.
MOSI — Master Out/Slave In Pin
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as
slave.
MISO — Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as
master.
SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when
its configured as a master and its used as an input to receive the slave select signal when the SPI is configured as slave.
SCK — Serial Clock Pin
This pin is used to output the clock with respect to which the SPI transfers data or receive clock in case of slave.

21. Module Memory Map
1 Certain bits are non-writable.
2 Writes to this register are ignored.
3 Reading from this register returns all zeros.

22. Register Descriptions
Register descriptions in address order. Each
description includes a standard register
diagram with an associated figure number.
Details of register bit and field function
follow the register diagrams, in bit order.

23. SPI Control Register (SPICR1) and SS Input / Output Selection

24. Field Description
7 SPIE
SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
• 0 SPI interrupts disabled.
• 1 SPI interrupts enabled.
6 SPE
SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared,
SPI is disabled and forced into idle state, status bits in SPISR register are reset.
• 0 SPI disabled (lower power consumption).
• 1 SPI enabled, port pins are dedicated to SPI functions.
5 SPTIE
SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.
• 0 SPTEF interrupt disabled.
• 1 SPTEF interrupt enabled.
4 MSTR
SPI Master/Slave Mode Select Bit — This bit selects, if the SPI operates in master or slave mode. Switching the SPI from master to
slave or vice versa forces the SPI system into idle state.
• 0 SPI is in slave mode
• 1 SPI is in master mode
3 CPOL
SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules
must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into
idle state.
• 0 Active-high clocks selected. In idle state SCK is low.
• 1 Active-low clocks selected. In idle state SCK is high.
2 CPHA
SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a transmission in
progress and force the SPI system into idle state.
• 0 Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock
• 1 Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock
1 SSOE
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as
shown in Table 1-3. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.
0 LSBFE
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register
always have the MSB in bit 7. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle
state.
• 0 Data is transferred most significant bit first.
• 1 Data is transferred least significant bit first.

25. SPI Control Register 2 (SPICR2)
Bi-directional pin Configarations
Pin Mode SPC0 BIDIROE MISO MOSI
Master Mode of Operation
Normal 0 X Master In Master Out
Bidirectional 1
0 MISO not used by
SPI
Master In
1 Master I/O
Slave Mode of Operation
Normal 0 X Slave out Slave in
Pin Mode SPC0 BIDIROE MISO MOSI
Bidirectional 1
0 Slave In MOSI not used by
SPI
1 Slave I/O

26. SPICR2 Field Descriptions
Field Description
4 MODFEN
Mode Fault Enable Bit — This bit allows the MODF failure being detected. If the SPI is in master mode and
MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin
configuration refer to Table 1-3. In master mode, a change of this bit will abort a transmission in progress and
force the SPI system into idle state.
• 0 SS port pin is not used by the SPI
• 1 SS port pin with MODF feature
3 BIDIROE
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer of
the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode this bit controls the output buffer
of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a
change of this bit will abort a transmission in progress and force the SPI into idle state.
• 0 Output buffer disabled
• 1 Output buffer enabled
1 SPISWAI
SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
• 0 SPI clock operates normally in wait mode
• 1 Stop SPI clock generation when in wait mode
0 SPC0
Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 1-5. In master
mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state

27. SPI Baud Rate Register (SPIBR)
Field Description
6:4
SPPR[2:0]
SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 1-7. In
master mode, a change of these bits will abort a transmission in progress and force the SPI system into
idle state.
2:0
SPR[2:0}
SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 1-7. In master
mode, a change of these bits will abort a transmission in progress and force the SPI system into idle
state.
The baud rate divisor equation is as follows:
BaudRateDivisor = (SPPR + 12(SPR + 1The baud rate can be calculated with the following equation:
Baud Rate = BusClock BaudRateDivisor

28. SPI Status Register
Field Description
7 SPIF
SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI Data Register. This bit is
cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI Data Register.
• 0 Transfer not yet complete
• 1 New data copied to SPIDR
5 SPTEF
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear this bit and
place data into the transmit data register, SPISR has to be read with SPTEF = 1, followed by a write to SPIDR. Any write to
the SPI Data Register without reading SPTEF = 1, is effectively ignored.
• 0 SPI Data register not empty
• 1 SPI Data register empty
4 MODF
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode fault
detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 1.3.2.2, “SPI Control Register 2 (SPICR2).” The flag is cleared automatically by a read of the SPI Status Register
(with MODF set) followed by a write to the SPI Control Register 1.
• 0 Mode fault has not occurred.
• 1 Mode fault has occurred.

29. SPI Data Register
Read: anytime; normally read only after SPIF is set
Write: anytime
The SPI Data Register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and
transmitted. For a SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has
completed. The SPI Transmitter Empty Flag SPTEF in the SPISR register indicates when the SPI Data Register is ready to accept
new data.
Reading the data can occur anytime from after the SPIF is set to before the end of the next transfer. If the SPIF is not serviced by the
end of the successive transfers, those data bytes are lost and the data within the SPIDR retains the first byte until SPIF is serviced.

30. Baud Rate Code
always@(posedge clk,negedge reset)
begin
if(!reset)
begin
count <= 12'hfff;
baud_rate_no_delay <= 0;
end
else if(count == ((baud_rate_divisor/2)-1))
begin
count <= 12'h0;
baud_rate_no_delay <= ~baud_rate_no_delay;
end
else
count <= count + 12'h1;
end
assign baud_rate_clk = baud_rate_no_delay;
endmodule
module baud_rate_gen(clk,reset,baud_rate_register,baud_rate_clk);
input clk,reset;
input[7:0] baud_rate_register;
output baud_rate_clk;
wire baud_rate_clk;
wire [2:0] SPPR;
wire [2:0] SPR;
reg baud_rate_no_delay;
reg [12:0] baud_rate_divisor;
reg [11:0] count;
assign SPR[2:0] = baud_rate_register[2:0];
assign SPPR[2:0] = baud_rate_register[6:4];
always@(posedge clk,negedge reset)
begin
if(!reset)
baud_rate_divisor <= 13'h0;
else
baud_rate_divisor <= ((SPPR + 1) * (2**(SPR + 1)));
end

31. 8'h03:
begin
fifo_write_enable<=1'b0;
if(!pwrite_spi && penable_spi)begin
prdata_spi <= spi_sr;
end
else
prdata_spi <= 8'h00;
end
8'h04:
begin
if(pwrite_spi )
begin
if (!full && penable_spi)
begin
fifo_write_enable <= 1'b1;
spi_dr <= pwdata_spi;
end
end
else
begin
prdata_spi <= spi_dr;
fifo_write_enable <= 1'b0;
end
end
SPI
case(paddr_spi)
8'h00:
begin
fifo_write_enable<=1'b0;
if(spi_logic)begin
spi_cr_1 <= pwdata_spi;
end
else
prdata_spi <= spi_cr_1;
end
8'h01: // control register 2
begin
fifo_write_enable <=1'b0;
if(spi_logic)begin
MODFEN <= pwdata_spi[4];
BIDIROE <= pwdata_spi[3];
SPISWAI <= pwdata_spi[1];
SPC0 <= pwdata_spi[0];
end
else
prdata_spi <= {3'b0, MODFEN, BIDIROE, 1'b0, SPISWAI, SPC0};
end
8'h02:
begin
fifo_write_enable<=1'b0;
if(spi_logic)begin
spi_baud_reg <= pwdata_spi;
end
else
prdata_spi <= spi_baud_reg;
end

32. Contd..
8'h05:
begin
if(!pwrite_spi && penable_spi) begin
fifo_write_enable <= 1'b0;
prdata_spi <= rdata;
end
else
prdata_spi <= prdata_spi;
end
8'h06:
begin
if( spi_logic)begin
ctrl_status_reg <= pwdata_spi[4];
end
else
prdata_spi <= {1'b0,1'b0,1'b0,ctrl_status_reg,1'b0,1'b0,1'b0,1'b0};
end
default:
begin
fifo_write_enable <=1'b0;
end
endcase

33. Write

34. Read

35. Date: 1 June 2023