SlideShare une entreprise Scribd logo
1  sur  26
Guided By:-
G.L.Singh sir
Sri Chaitanya College Of Engineering
& Technology.
Contents:
• Aim
• Introduction
• Block Diagram
• Applications
• Advantages & Limitations
• Tools
• Conclusion
Aim:
To test the processing element in MECA & correct the
fault processing element.
To design a BIST circuit for processing elements.
Self detection and self correction.
Introduction:
• Joint Video Team (JVT).
• Motion Estimation Computing Arrays (MECA).
• Integrating MECA into a system-on-chip (SOC) design
has become increasingly important for video coding
applications.
• MECA performs up to 50% of computations in the entire
video-coding system
• For a commercial chip, a video coding system must
introduce Design For Testability (DFT), especially in an
MECA.
• These DFT approaches can be divided into three
categories.
1. Ad Hoc (Problems).
2. Structured.
3. BIST
• Among these techniques, BIST has an obvious advantage
in that expensive test equipment is not needed and tests
are low cost.
• The extended techniques of BIST are built-in self-
diagnosis(BISD) and built-in self-repair (BISR).
Introduction:
Block Diagram:
Current Pixel
Reference Pixel
Coder Processing
Elements
Detector
Selector
Corrector
Current and Reference Pixels:
• In a Video Sequence for 1Sec of time 64-images are
displayed.
• Current and Reference pixels are the two successive
images of the Video Sequence.
• Current Pixel is the present image displayed.
• Reference Pixel is the next image to be displayed.
• These two Pixels are Considered as the inputs.
Current and Reference Pixels:
Coder:
• The Current and Reference pixels are carried forward to
Coder.
• Here the Coder is used to convert the image into the Code
words.
• The codes are stored in the two different memory slots.
• In coder 2 coder modules are used to generate test code.
Coder:
Current frame:-
Reference frame:-
Processing Elements:
• Processing element calculates the sum of absolute
differences between current pixels and reference pixels.
• And then the two images are compressed into one image.
• Motion Estimation of the two pixels are done here.
Processing Elements:
Processing Elements:
Resulting image:-
Processing Elements:
Detector:
• The Output of Processing Elements is taken as the input for
the Detector.
• Detection of errors formed in the processing elements is
done.
• Syndrome Decoder is used to detect the error bit position.
Selector:
• Selector has two inputs.
1. Processing Elements
2. Detector
• Here the exact error bit position is found by comparing the
inputs.
Corrector:
• Input to the corrector module is the output of the selector
module that needs to be corrected.
• The corrector architecture consists of LUT(Look Up Table)
and 12 multiplexers.
Corrector:
Look Up Table:-
Applications:
• Aerospace/Defense, Automotive, Banking, Computer,
Healthcare, Networking, and Telecommunications.
• Motion Estimation used in MPEG-4 Multimedia
Applications and H.264/AVC video coding Standards.
• Motion Estimation in Space Science.
• Tracking of a person in a video sequence
Advantages:
• Better fault coverage, since special test structures can
be incorporated onto the chips
• Shorter test times if the BIST can be designed to test
more structures in parallel.
• Lower cost of test.
• Less no. of gate counts.
• More reliable.
• Easier customer support.
• Power Consumption is Low.
Limitations:
• Additional silicon area and fab processing requirements for
the BIST circuits.
• Additional pin requirements.
• Reduced access times.
• It uses more memory.
Future Scope:
 Timing required for Motion Estimation will be reduced.
 The input to the MECA is 8-bit data. It also can be
extended to higher volume of data.
 BIST can used in Flash memory type of Systems.
Tools:
 Software : Xilinx 12.3, Mat lab
 Language: Verilog
Conclusion:
Built-in Self-Detection/Correction Architecture for
Motion Estimation Computing Arrays is the project that is to
decrease the errors in the video sequence and make the video
more reliable to watch & Also estimates the tracking of a
person & object.
Built In Self Testing(BIST) Architecture for Motin Estimation and Computing Arrays(MECA)
Built In Self Testing(BIST) Architecture for Motin Estimation and Computing Arrays(MECA)

Contenu connexe

Tendances

Wavelet Based on the Finding of Hard and Soft Faults in Analog and Digital Si...
Wavelet Based on the Finding of Hard and Soft Faults in Analog and Digital Si...Wavelet Based on the Finding of Hard and Soft Faults in Analog and Digital Si...
Wavelet Based on the Finding of Hard and Soft Faults in Analog and Digital Si...ijcisjournal
 
faults in digital systems
faults in digital systemsfaults in digital systems
faults in digital systemsdennis gookyi
 
Design Verification and Test Vector Minimization Using Heuristic Method of a ...
Design Verification and Test Vector Minimization Using Heuristic Method of a ...Design Verification and Test Vector Minimization Using Heuristic Method of a ...
Design Verification and Test Vector Minimization Using Heuristic Method of a ...ijcisjournal
 
A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated ...
A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated ...A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated ...
A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated ...VLSICS Design
 
Reducing Area & Power Overhead In Design of Light Weight Sensor For Detection...
Reducing Area & Power Overhead In Design of Light Weight Sensor For Detection...Reducing Area & Power Overhead In Design of Light Weight Sensor For Detection...
Reducing Area & Power Overhead In Design of Light Weight Sensor For Detection...IJERA Editor
 
RESUME MANJEET (IC Design Engineer, Broadcom)(IIT Roorkee)
RESUME MANJEET (IC Design Engineer, Broadcom)(IIT Roorkee)RESUME MANJEET (IC Design Engineer, Broadcom)(IIT Roorkee)
RESUME MANJEET (IC Design Engineer, Broadcom)(IIT Roorkee)Manjeet Singh Lowanshi
 
Improvement in Error Resilience in BIST using hamming code
Improvement in Error Resilience in BIST using hamming codeImprovement in Error Resilience in BIST using hamming code
Improvement in Error Resilience in BIST using hamming codeIJMTST Journal
 
4 article azojete vol 8 37 45
4 article azojete vol 8 37 454 article azojete vol 8 37 45
4 article azojete vol 8 37 45Oyeniyi Samuel
 
Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Co...
Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Co...Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Co...
Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Co...iosrjce
 
Boundary Scan Basics - x1149 de Keysight
Boundary Scan Basics - x1149 de KeysightBoundary Scan Basics - x1149 de Keysight
Boundary Scan Basics - x1149 de KeysightInterlatin
 
Otdrpresentation 171203144201
Otdrpresentation 171203144201Otdrpresentation 171203144201
Otdrpresentation 171203144201ShahabKhalid6
 
implementation of area efficient high speed eddr architecture
implementation of area efficient high speed eddr architectureimplementation of area efficient high speed eddr architecture
implementation of area efficient high speed eddr architectureKumar Goud
 
A Unified Approach for Performance Degradation Analysis from Transistor to Gat...
A Unified Approach for Performance Degradation Analysis from Transistor to Gat...A Unified Approach for Performance Degradation Analysis from Transistor to Gat...
A Unified Approach for Performance Degradation Analysis from Transistor to Gat...IJECEIAES
 

Tendances (19)

Wavelet Based on the Finding of Hard and Soft Faults in Analog and Digital Si...
Wavelet Based on the Finding of Hard and Soft Faults in Analog and Digital Si...Wavelet Based on the Finding of Hard and Soft Faults in Analog and Digital Si...
Wavelet Based on the Finding of Hard and Soft Faults in Analog and Digital Si...
 
dft
dftdft
dft
 
faults in digital systems
faults in digital systemsfaults in digital systems
faults in digital systems
 
Design Verification and Test Vector Minimization Using Heuristic Method of a ...
Design Verification and Test Vector Minimization Using Heuristic Method of a ...Design Verification and Test Vector Minimization Using Heuristic Method of a ...
Design Verification and Test Vector Minimization Using Heuristic Method of a ...
 
A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated ...
A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated ...A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated ...
A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated ...
 
Reducing Area & Power Overhead In Design of Light Weight Sensor For Detection...
Reducing Area & Power Overhead In Design of Light Weight Sensor For Detection...Reducing Area & Power Overhead In Design of Light Weight Sensor For Detection...
Reducing Area & Power Overhead In Design of Light Weight Sensor For Detection...
 
RESUME MANJEET (IC Design Engineer, Broadcom)(IIT Roorkee)
RESUME MANJEET (IC Design Engineer, Broadcom)(IIT Roorkee)RESUME MANJEET (IC Design Engineer, Broadcom)(IIT Roorkee)
RESUME MANJEET (IC Design Engineer, Broadcom)(IIT Roorkee)
 
Improvement in Error Resilience in BIST using hamming code
Improvement in Error Resilience in BIST using hamming codeImprovement in Error Resilience in BIST using hamming code
Improvement in Error Resilience in BIST using hamming code
 
Y04507139147
Y04507139147Y04507139147
Y04507139147
 
4 article azojete vol 8 37 45
4 article azojete vol 8 37 454 article azojete vol 8 37 45
4 article azojete vol 8 37 45
 
Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Co...
Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Co...Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Co...
Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Co...
 
Boundary Scan Basics - x1149 de Keysight
Boundary Scan Basics - x1149 de KeysightBoundary Scan Basics - x1149 de Keysight
Boundary Scan Basics - x1149 de Keysight
 
The IEEE 1149.1 Boundary-scan test standard
The IEEE 1149.1 Boundary-scan test standardThe IEEE 1149.1 Boundary-scan test standard
The IEEE 1149.1 Boundary-scan test standard
 
Otdrpresentation 171203144201
Otdrpresentation 171203144201Otdrpresentation 171203144201
Otdrpresentation 171203144201
 
implementation of area efficient high speed eddr architecture
implementation of area efficient high speed eddr architectureimplementation of area efficient high speed eddr architecture
implementation of area efficient high speed eddr architecture
 
C010421720
C010421720C010421720
C010421720
 
A Unified Approach for Performance Degradation Analysis from Transistor to Gat...
A Unified Approach for Performance Degradation Analysis from Transistor to Gat...A Unified Approach for Performance Degradation Analysis from Transistor to Gat...
A Unified Approach for Performance Degradation Analysis from Transistor to Gat...
 
SNUG 2011 paper
SNUG 2011 paperSNUG 2011 paper
SNUG 2011 paper
 
pramod
pramodpramod
pramod
 

En vedette

Low power test pattern generation for bist applications
Low power test pattern generation for bist applicationsLow power test pattern generation for bist applications
Low power test pattern generation for bist applicationseSAT Journals
 
Pseudo Random Bit Sequence Generator
Pseudo Random Bit Sequence Generator Pseudo Random Bit Sequence Generator
Pseudo Random Bit Sequence Generator ajay singh
 
SYNERGY THRISLINGTON (EMERGING COMPANY IN PUF MARKET)
SYNERGY THRISLINGTON (EMERGING COMPANY IN PUF MARKET)SYNERGY THRISLINGTON (EMERGING COMPANY IN PUF MARKET)
SYNERGY THRISLINGTON (EMERGING COMPANY IN PUF MARKET)surabhi04
 
Mobile communication – the milestone in wireless communication
Mobile communication – the milestone in wireless communicationMobile communication – the milestone in wireless communication
Mobile communication – the milestone in wireless communicationsree navya
 
Paper Presentation
Paper PresentationPaper Presentation
Paper Presentationjohirbuet
 
cellular automata as a test pattern generator and output response compactor f...
cellular automata as a test pattern generator and output response compactor f...cellular automata as a test pattern generator and output response compactor f...
cellular automata as a test pattern generator and output response compactor f...Shiva Narayan Reddy
 
Design and Implementation of FPGA Based Low Power Pipelined 64 Bit Risc Proce...
Design and Implementation of FPGA Based Low Power Pipelined 64 Bit Risc Proce...Design and Implementation of FPGA Based Low Power Pipelined 64 Bit Risc Proce...
Design and Implementation of FPGA Based Low Power Pipelined 64 Bit Risc Proce...IJEEE
 
VLSI Projects, IC Design, Low Power VLSI, Power Management, BIST, FPGA Projec...
VLSI Projects, IC Design, Low Power VLSI, Power Management, BIST, FPGA Projec...VLSI Projects, IC Design, Low Power VLSI, Power Management, BIST, FPGA Projec...
VLSI Projects, IC Design, Low Power VLSI, Power Management, BIST, FPGA Projec...Manoj Subramanian
 
Optimal and Power Aware BIST for Delay Testing of System-On-Chip
Optimal and Power Aware BIST for Delay Testing of System-On-ChipOptimal and Power Aware BIST for Delay Testing of System-On-Chip
Optimal and Power Aware BIST for Delay Testing of System-On-ChipIDES Editor
 
Zigbee technology
Zigbee technologyZigbee technology
Zigbee technologySerma Pavi
 
Sandwichpanel pptSandwich Puf Panels Manufacturers
Sandwichpanel pptSandwich Puf Panels ManufacturersSandwichpanel pptSandwich Puf Panels Manufacturers
Sandwichpanel pptSandwich Puf Panels Manufacturerssandwichpanels
 
Ieee 2015 project list_vlsi
Ieee 2015 project list_vlsiIeee 2015 project list_vlsi
Ieee 2015 project list_vlsiigeeks1234
 
Power generation through solar trains
Power generation through solar trainsPower generation through solar trains
Power generation through solar trainschakri218
 
KUSURSUZ SUNUM YAPMANIN 7 TAKTİĞİ
KUSURSUZ SUNUM YAPMANIN 7 TAKTİĞİ KUSURSUZ SUNUM YAPMANIN 7 TAKTİĞİ
KUSURSUZ SUNUM YAPMANIN 7 TAKTİĞİ Sunumo
 
ETKİLİ BİR SUNUM İÇİN OLMAZSA OLMAZLAR(PÜF NOKTALARI)
ETKİLİ BİR SUNUM İÇİN OLMAZSA OLMAZLAR(PÜF NOKTALARI)ETKİLİ BİR SUNUM İÇİN OLMAZSA OLMAZLAR(PÜF NOKTALARI)
ETKİLİ BİR SUNUM İÇİN OLMAZSA OLMAZLAR(PÜF NOKTALARI)Barış ŞENER
 
Seminar on Digital Multiplier(Booth Multiplier) Using VHDL
Seminar on Digital Multiplier(Booth Multiplier) Using VHDLSeminar on Digital Multiplier(Booth Multiplier) Using VHDL
Seminar on Digital Multiplier(Booth Multiplier) Using VHDLNaseer LoneRider
 

En vedette (20)

Low power test pattern generation for bist applications
Low power test pattern generation for bist applicationsLow power test pattern generation for bist applications
Low power test pattern generation for bist applications
 
Implementation of Low Power Test Pattern Generator Using LFSR
Implementation of Low Power Test Pattern Generator Using LFSRImplementation of Low Power Test Pattern Generator Using LFSR
Implementation of Low Power Test Pattern Generator Using LFSR
 
Pseudo Random Bit Sequence Generator
Pseudo Random Bit Sequence Generator Pseudo Random Bit Sequence Generator
Pseudo Random Bit Sequence Generator
 
SYNERGY THRISLINGTON (EMERGING COMPANY IN PUF MARKET)
SYNERGY THRISLINGTON (EMERGING COMPANY IN PUF MARKET)SYNERGY THRISLINGTON (EMERGING COMPANY IN PUF MARKET)
SYNERGY THRISLINGTON (EMERGING COMPANY IN PUF MARKET)
 
testing
testingtesting
testing
 
Mobile communication – the milestone in wireless communication
Mobile communication – the milestone in wireless communicationMobile communication – the milestone in wireless communication
Mobile communication – the milestone in wireless communication
 
Paper Presentation
Paper PresentationPaper Presentation
Paper Presentation
 
cellular automata as a test pattern generator and output response compactor f...
cellular automata as a test pattern generator and output response compactor f...cellular automata as a test pattern generator and output response compactor f...
cellular automata as a test pattern generator and output response compactor f...
 
Design and Implementation of FPGA Based Low Power Pipelined 64 Bit Risc Proce...
Design and Implementation of FPGA Based Low Power Pipelined 64 Bit Risc Proce...Design and Implementation of FPGA Based Low Power Pipelined 64 Bit Risc Proce...
Design and Implementation of FPGA Based Low Power Pipelined 64 Bit Risc Proce...
 
VLSI Projects, IC Design, Low Power VLSI, Power Management, BIST, FPGA Projec...
VLSI Projects, IC Design, Low Power VLSI, Power Management, BIST, FPGA Projec...VLSI Projects, IC Design, Low Power VLSI, Power Management, BIST, FPGA Projec...
VLSI Projects, IC Design, Low Power VLSI, Power Management, BIST, FPGA Projec...
 
Optimal and Power Aware BIST for Delay Testing of System-On-Chip
Optimal and Power Aware BIST for Delay Testing of System-On-ChipOptimal and Power Aware BIST for Delay Testing of System-On-Chip
Optimal and Power Aware BIST for Delay Testing of System-On-Chip
 
Zigbee technology
Zigbee technologyZigbee technology
Zigbee technology
 
Sandwichpanel pptSandwich Puf Panels Manufacturers
Sandwichpanel pptSandwich Puf Panels ManufacturersSandwichpanel pptSandwich Puf Panels Manufacturers
Sandwichpanel pptSandwich Puf Panels Manufacturers
 
Cellular Automata
Cellular AutomataCellular Automata
Cellular Automata
 
Ieee 2015 project list_vlsi
Ieee 2015 project list_vlsiIeee 2015 project list_vlsi
Ieee 2015 project list_vlsi
 
Power generation through solar trains
Power generation through solar trainsPower generation through solar trains
Power generation through solar trains
 
LFSR
LFSRLFSR
LFSR
 
KUSURSUZ SUNUM YAPMANIN 7 TAKTİĞİ
KUSURSUZ SUNUM YAPMANIN 7 TAKTİĞİ KUSURSUZ SUNUM YAPMANIN 7 TAKTİĞİ
KUSURSUZ SUNUM YAPMANIN 7 TAKTİĞİ
 
ETKİLİ BİR SUNUM İÇİN OLMAZSA OLMAZLAR(PÜF NOKTALARI)
ETKİLİ BİR SUNUM İÇİN OLMAZSA OLMAZLAR(PÜF NOKTALARI)ETKİLİ BİR SUNUM İÇİN OLMAZSA OLMAZLAR(PÜF NOKTALARI)
ETKİLİ BİR SUNUM İÇİN OLMAZSA OLMAZLAR(PÜF NOKTALARI)
 
Seminar on Digital Multiplier(Booth Multiplier) Using VHDL
Seminar on Digital Multiplier(Booth Multiplier) Using VHDLSeminar on Digital Multiplier(Booth Multiplier) Using VHDL
Seminar on Digital Multiplier(Booth Multiplier) Using VHDL
 

Similaire à Built In Self Testing(BIST) Architecture for Motin Estimation and Computing Arrays(MECA)

FYP-Final-External
FYP-Final-ExternalFYP-Final-External
FYP-Final-ExternalAhmed Rik
 
Ip cctv design full course by eng nader elmansi
Ip cctv design full course by eng nader elmansiIp cctv design full course by eng nader elmansi
Ip cctv design full course by eng nader elmansiNader Elmansi
 
1.0 2.0 IP CCTV system
1.0 2.0 IP CCTV system 1.0 2.0 IP CCTV system
1.0 2.0 IP CCTV system Nader Elmansi
 
1. An Introduction to Embed Systems_DRKG.pptx
1. An Introduction to Embed Systems_DRKG.pptx1. An Introduction to Embed Systems_DRKG.pptx
1. An Introduction to Embed Systems_DRKG.pptxKesavanGopal1
 
VIP - Wheelchair Project Final Presentation
VIP - Wheelchair Project Final PresentationVIP - Wheelchair Project Final Presentation
VIP - Wheelchair Project Final PresentationKarvin Dassanayake
 
System On Chip (SOC)
System On Chip (SOC)System On Chip (SOC)
System On Chip (SOC)Shivam Gupta
 
SCADA ( Supervisory Control and Data Acquisition system) Software Solutions
SCADA ( Supervisory Control and Data Acquisition system) Software SolutionsSCADA ( Supervisory Control and Data Acquisition system) Software Solutions
SCADA ( Supervisory Control and Data Acquisition system) Software SolutionsEmbitel Technologies (I) PVT LTD
 
High Efficiency Video Codec
High Efficiency Video CodecHigh Efficiency Video Codec
High Efficiency Video CodecTejus Adiga M
 
System On Chip
System On ChipSystem On Chip
System On ChipA B Shinde
 
IOT Unit 3 for engineering second year .pptx
IOT Unit 3 for engineering second year .pptxIOT Unit 3 for engineering second year .pptx
IOT Unit 3 for engineering second year .pptxneelamsanjeevkumar
 
SOC Application Studies: Image Compression
SOC Application Studies: Image CompressionSOC Application Studies: Image Compression
SOC Application Studies: Image CompressionA B Shinde
 
IRJET- A Review: To Design Efficient 32 Bits Carry Select Adder by using ...
IRJET-  	  A Review: To Design Efficient 32 Bits Carry Select Adder by using ...IRJET-  	  A Review: To Design Efficient 32 Bits Carry Select Adder by using ...
IRJET- A Review: To Design Efficient 32 Bits Carry Select Adder by using ...IRJET Journal
 
Paper id 2120148
Paper id 2120148Paper id 2120148
Paper id 2120148IJRAT
 
CAD theory presentation.pptx .
CAD theory presentation.pptx                .CAD theory presentation.pptx                .
CAD theory presentation.pptx .Athar739197
 
Delphi Integrated Radar and Camera System (RACam) 2016 teardown reverse costi...
Delphi Integrated Radar and Camera System (RACam) 2016 teardown reverse costi...Delphi Integrated Radar and Camera System (RACam) 2016 teardown reverse costi...
Delphi Integrated Radar and Camera System (RACam) 2016 teardown reverse costi...Yole Developpement
 
OBD2 Software Development and Testing for an ECU Application
OBD2 Software Development and Testing for an ECU ApplicationOBD2 Software Development and Testing for an ECU Application
OBD2 Software Development and Testing for an ECU ApplicationEmbitel Technologies (I) PVT LTD
 
fingerprint based electronic voting machine
fingerprint based electronic voting machinefingerprint based electronic voting machine
fingerprint based electronic voting machinesanthu652
 

Similaire à Built In Self Testing(BIST) Architecture for Motin Estimation and Computing Arrays(MECA) (20)

FYP-Final-External
FYP-Final-ExternalFYP-Final-External
FYP-Final-External
 
Ip cctv design full course by eng nader elmansi
Ip cctv design full course by eng nader elmansiIp cctv design full course by eng nader elmansi
Ip cctv design full course by eng nader elmansi
 
1.0 2.0 IP CCTV system
1.0 2.0 IP CCTV system 1.0 2.0 IP CCTV system
1.0 2.0 IP CCTV system
 
1. An Introduction to Embed Systems_DRKG.pptx
1. An Introduction to Embed Systems_DRKG.pptx1. An Introduction to Embed Systems_DRKG.pptx
1. An Introduction to Embed Systems_DRKG.pptx
 
VIP - Wheelchair Project Final Presentation
VIP - Wheelchair Project Final PresentationVIP - Wheelchair Project Final Presentation
VIP - Wheelchair Project Final Presentation
 
Real Time Video Processing in FPGA
Real Time Video Processing in FPGA Real Time Video Processing in FPGA
Real Time Video Processing in FPGA
 
System On Chip (SOC)
System On Chip (SOC)System On Chip (SOC)
System On Chip (SOC)
 
SCADA ( Supervisory Control and Data Acquisition system) Software Solutions
SCADA ( Supervisory Control and Data Acquisition system) Software SolutionsSCADA ( Supervisory Control and Data Acquisition system) Software Solutions
SCADA ( Supervisory Control and Data Acquisition system) Software Solutions
 
Intro to building mvs
Intro to building  mvsIntro to building  mvs
Intro to building mvs
 
High Efficiency Video Codec
High Efficiency Video CodecHigh Efficiency Video Codec
High Efficiency Video Codec
 
System On Chip
System On ChipSystem On Chip
System On Chip
 
IOT Unit 3 for engineering second year .pptx
IOT Unit 3 for engineering second year .pptxIOT Unit 3 for engineering second year .pptx
IOT Unit 3 for engineering second year .pptx
 
Core of the ES
Core of the ESCore of the ES
Core of the ES
 
SOC Application Studies: Image Compression
SOC Application Studies: Image CompressionSOC Application Studies: Image Compression
SOC Application Studies: Image Compression
 
IRJET- A Review: To Design Efficient 32 Bits Carry Select Adder by using ...
IRJET-  	  A Review: To Design Efficient 32 Bits Carry Select Adder by using ...IRJET-  	  A Review: To Design Efficient 32 Bits Carry Select Adder by using ...
IRJET- A Review: To Design Efficient 32 Bits Carry Select Adder by using ...
 
Paper id 2120148
Paper id 2120148Paper id 2120148
Paper id 2120148
 
CAD theory presentation.pptx .
CAD theory presentation.pptx                .CAD theory presentation.pptx                .
CAD theory presentation.pptx .
 
Delphi Integrated Radar and Camera System (RACam) 2016 teardown reverse costi...
Delphi Integrated Radar and Camera System (RACam) 2016 teardown reverse costi...Delphi Integrated Radar and Camera System (RACam) 2016 teardown reverse costi...
Delphi Integrated Radar and Camera System (RACam) 2016 teardown reverse costi...
 
OBD2 Software Development and Testing for an ECU Application
OBD2 Software Development and Testing for an ECU ApplicationOBD2 Software Development and Testing for an ECU Application
OBD2 Software Development and Testing for an ECU Application
 
fingerprint based electronic voting machine
fingerprint based electronic voting machinefingerprint based electronic voting machine
fingerprint based electronic voting machine
 

Dernier

Scanning the Internet for External Cloud Exposures via SSL Certs
Scanning the Internet for External Cloud Exposures via SSL CertsScanning the Internet for External Cloud Exposures via SSL Certs
Scanning the Internet for External Cloud Exposures via SSL CertsRizwan Syed
 
Anypoint Exchange: It’s Not Just a Repo!
Anypoint Exchange: It’s Not Just a Repo!Anypoint Exchange: It’s Not Just a Repo!
Anypoint Exchange: It’s Not Just a Repo!Manik S Magar
 
Nell’iperspazio con Rocket: il Framework Web di Rust!
Nell’iperspazio con Rocket: il Framework Web di Rust!Nell’iperspazio con Rocket: il Framework Web di Rust!
Nell’iperspazio con Rocket: il Framework Web di Rust!Commit University
 
Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024BookNet Canada
 
SIP trunking in Janus @ Kamailio World 2024
SIP trunking in Janus @ Kamailio World 2024SIP trunking in Janus @ Kamailio World 2024
SIP trunking in Janus @ Kamailio World 2024Lorenzo Miniero
 
Advanced Test Driven-Development @ php[tek] 2024
Advanced Test Driven-Development @ php[tek] 2024Advanced Test Driven-Development @ php[tek] 2024
Advanced Test Driven-Development @ php[tek] 2024Scott Keck-Warren
 
"Subclassing and Composition – A Pythonic Tour of Trade-Offs", Hynek Schlawack
"Subclassing and Composition – A Pythonic Tour of Trade-Offs", Hynek Schlawack"Subclassing and Composition – A Pythonic Tour of Trade-Offs", Hynek Schlawack
"Subclassing and Composition – A Pythonic Tour of Trade-Offs", Hynek SchlawackFwdays
 
Take control of your SAP testing with UiPath Test Suite
Take control of your SAP testing with UiPath Test SuiteTake control of your SAP testing with UiPath Test Suite
Take control of your SAP testing with UiPath Test SuiteDianaGray10
 
The Ultimate Guide to Choosing WordPress Pros and Cons
The Ultimate Guide to Choosing WordPress Pros and ConsThe Ultimate Guide to Choosing WordPress Pros and Cons
The Ultimate Guide to Choosing WordPress Pros and ConsPixlogix Infotech
 
Merck Moving Beyond Passwords: FIDO Paris Seminar.pptx
Merck Moving Beyond Passwords: FIDO Paris Seminar.pptxMerck Moving Beyond Passwords: FIDO Paris Seminar.pptx
Merck Moving Beyond Passwords: FIDO Paris Seminar.pptxLoriGlavin3
 
Leverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage Cost
Leverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage CostLeverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage Cost
Leverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage CostZilliz
 
"LLMs for Python Engineers: Advanced Data Analysis and Semantic Kernel",Oleks...
"LLMs for Python Engineers: Advanced Data Analysis and Semantic Kernel",Oleks..."LLMs for Python Engineers: Advanced Data Analysis and Semantic Kernel",Oleks...
"LLMs for Python Engineers: Advanced Data Analysis and Semantic Kernel",Oleks...Fwdays
 
Connect Wave/ connectwave Pitch Deck Presentation
Connect Wave/ connectwave Pitch Deck PresentationConnect Wave/ connectwave Pitch Deck Presentation
Connect Wave/ connectwave Pitch Deck PresentationSlibray Presentation
 
Ensuring Technical Readiness For Copilot in Microsoft 365
Ensuring Technical Readiness For Copilot in Microsoft 365Ensuring Technical Readiness For Copilot in Microsoft 365
Ensuring Technical Readiness For Copilot in Microsoft 3652toLead Limited
 
Dev Dives: Streamline document processing with UiPath Studio Web
Dev Dives: Streamline document processing with UiPath Studio WebDev Dives: Streamline document processing with UiPath Studio Web
Dev Dives: Streamline document processing with UiPath Studio WebUiPathCommunity
 
Commit 2024 - Secret Management made easy
Commit 2024 - Secret Management made easyCommit 2024 - Secret Management made easy
Commit 2024 - Secret Management made easyAlfredo García Lavilla
 
Designing IA for AI - Information Architecture Conference 2024
Designing IA for AI - Information Architecture Conference 2024Designing IA for AI - Information Architecture Conference 2024
Designing IA for AI - Information Architecture Conference 2024Enterprise Knowledge
 
Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)
Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)
Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)Mark Simos
 
Unleash Your Potential - Namagunga Girls Coding Club
Unleash Your Potential - Namagunga Girls Coding ClubUnleash Your Potential - Namagunga Girls Coding Club
Unleash Your Potential - Namagunga Girls Coding ClubKalema Edgar
 
What's New in Teams Calling, Meetings and Devices March 2024
What's New in Teams Calling, Meetings and Devices March 2024What's New in Teams Calling, Meetings and Devices March 2024
What's New in Teams Calling, Meetings and Devices March 2024Stephanie Beckett
 

Dernier (20)

Scanning the Internet for External Cloud Exposures via SSL Certs
Scanning the Internet for External Cloud Exposures via SSL CertsScanning the Internet for External Cloud Exposures via SSL Certs
Scanning the Internet for External Cloud Exposures via SSL Certs
 
Anypoint Exchange: It’s Not Just a Repo!
Anypoint Exchange: It’s Not Just a Repo!Anypoint Exchange: It’s Not Just a Repo!
Anypoint Exchange: It’s Not Just a Repo!
 
Nell’iperspazio con Rocket: il Framework Web di Rust!
Nell’iperspazio con Rocket: il Framework Web di Rust!Nell’iperspazio con Rocket: il Framework Web di Rust!
Nell’iperspazio con Rocket: il Framework Web di Rust!
 
Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
Transcript: New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
 
SIP trunking in Janus @ Kamailio World 2024
SIP trunking in Janus @ Kamailio World 2024SIP trunking in Janus @ Kamailio World 2024
SIP trunking in Janus @ Kamailio World 2024
 
Advanced Test Driven-Development @ php[tek] 2024
Advanced Test Driven-Development @ php[tek] 2024Advanced Test Driven-Development @ php[tek] 2024
Advanced Test Driven-Development @ php[tek] 2024
 
"Subclassing and Composition – A Pythonic Tour of Trade-Offs", Hynek Schlawack
"Subclassing and Composition – A Pythonic Tour of Trade-Offs", Hynek Schlawack"Subclassing and Composition – A Pythonic Tour of Trade-Offs", Hynek Schlawack
"Subclassing and Composition – A Pythonic Tour of Trade-Offs", Hynek Schlawack
 
Take control of your SAP testing with UiPath Test Suite
Take control of your SAP testing with UiPath Test SuiteTake control of your SAP testing with UiPath Test Suite
Take control of your SAP testing with UiPath Test Suite
 
The Ultimate Guide to Choosing WordPress Pros and Cons
The Ultimate Guide to Choosing WordPress Pros and ConsThe Ultimate Guide to Choosing WordPress Pros and Cons
The Ultimate Guide to Choosing WordPress Pros and Cons
 
Merck Moving Beyond Passwords: FIDO Paris Seminar.pptx
Merck Moving Beyond Passwords: FIDO Paris Seminar.pptxMerck Moving Beyond Passwords: FIDO Paris Seminar.pptx
Merck Moving Beyond Passwords: FIDO Paris Seminar.pptx
 
Leverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage Cost
Leverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage CostLeverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage Cost
Leverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage Cost
 
"LLMs for Python Engineers: Advanced Data Analysis and Semantic Kernel",Oleks...
"LLMs for Python Engineers: Advanced Data Analysis and Semantic Kernel",Oleks..."LLMs for Python Engineers: Advanced Data Analysis and Semantic Kernel",Oleks...
"LLMs for Python Engineers: Advanced Data Analysis and Semantic Kernel",Oleks...
 
Connect Wave/ connectwave Pitch Deck Presentation
Connect Wave/ connectwave Pitch Deck PresentationConnect Wave/ connectwave Pitch Deck Presentation
Connect Wave/ connectwave Pitch Deck Presentation
 
Ensuring Technical Readiness For Copilot in Microsoft 365
Ensuring Technical Readiness For Copilot in Microsoft 365Ensuring Technical Readiness For Copilot in Microsoft 365
Ensuring Technical Readiness For Copilot in Microsoft 365
 
Dev Dives: Streamline document processing with UiPath Studio Web
Dev Dives: Streamline document processing with UiPath Studio WebDev Dives: Streamline document processing with UiPath Studio Web
Dev Dives: Streamline document processing with UiPath Studio Web
 
Commit 2024 - Secret Management made easy
Commit 2024 - Secret Management made easyCommit 2024 - Secret Management made easy
Commit 2024 - Secret Management made easy
 
Designing IA for AI - Information Architecture Conference 2024
Designing IA for AI - Information Architecture Conference 2024Designing IA for AI - Information Architecture Conference 2024
Designing IA for AI - Information Architecture Conference 2024
 
Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)
Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)
Tampa BSides - Chef's Tour of Microsoft Security Adoption Framework (SAF)
 
Unleash Your Potential - Namagunga Girls Coding Club
Unleash Your Potential - Namagunga Girls Coding ClubUnleash Your Potential - Namagunga Girls Coding Club
Unleash Your Potential - Namagunga Girls Coding Club
 
What's New in Teams Calling, Meetings and Devices March 2024
What's New in Teams Calling, Meetings and Devices March 2024What's New in Teams Calling, Meetings and Devices March 2024
What's New in Teams Calling, Meetings and Devices March 2024
 

Built In Self Testing(BIST) Architecture for Motin Estimation and Computing Arrays(MECA)

  • 1. Guided By:- G.L.Singh sir Sri Chaitanya College Of Engineering & Technology.
  • 2. Contents: • Aim • Introduction • Block Diagram • Applications • Advantages & Limitations • Tools • Conclusion
  • 3. Aim: To test the processing element in MECA & correct the fault processing element. To design a BIST circuit for processing elements. Self detection and self correction.
  • 4. Introduction: • Joint Video Team (JVT). • Motion Estimation Computing Arrays (MECA). • Integrating MECA into a system-on-chip (SOC) design has become increasingly important for video coding applications. • MECA performs up to 50% of computations in the entire video-coding system • For a commercial chip, a video coding system must introduce Design For Testability (DFT), especially in an MECA.
  • 5. • These DFT approaches can be divided into three categories. 1. Ad Hoc (Problems). 2. Structured. 3. BIST • Among these techniques, BIST has an obvious advantage in that expensive test equipment is not needed and tests are low cost. • The extended techniques of BIST are built-in self- diagnosis(BISD) and built-in self-repair (BISR). Introduction:
  • 6. Block Diagram: Current Pixel Reference Pixel Coder Processing Elements Detector Selector Corrector
  • 7. Current and Reference Pixels: • In a Video Sequence for 1Sec of time 64-images are displayed. • Current and Reference pixels are the two successive images of the Video Sequence. • Current Pixel is the present image displayed. • Reference Pixel is the next image to be displayed. • These two Pixels are Considered as the inputs.
  • 9. Coder: • The Current and Reference pixels are carried forward to Coder. • Here the Coder is used to convert the image into the Code words. • The codes are stored in the two different memory slots. • In coder 2 coder modules are used to generate test code.
  • 11. Processing Elements: • Processing element calculates the sum of absolute differences between current pixels and reference pixels. • And then the two images are compressed into one image. • Motion Estimation of the two pixels are done here.
  • 15. Detector: • The Output of Processing Elements is taken as the input for the Detector. • Detection of errors formed in the processing elements is done. • Syndrome Decoder is used to detect the error bit position.
  • 16. Selector: • Selector has two inputs. 1. Processing Elements 2. Detector • Here the exact error bit position is found by comparing the inputs.
  • 17. Corrector: • Input to the corrector module is the output of the selector module that needs to be corrected. • The corrector architecture consists of LUT(Look Up Table) and 12 multiplexers.
  • 19. Applications: • Aerospace/Defense, Automotive, Banking, Computer, Healthcare, Networking, and Telecommunications. • Motion Estimation used in MPEG-4 Multimedia Applications and H.264/AVC video coding Standards. • Motion Estimation in Space Science. • Tracking of a person in a video sequence
  • 20. Advantages: • Better fault coverage, since special test structures can be incorporated onto the chips • Shorter test times if the BIST can be designed to test more structures in parallel. • Lower cost of test. • Less no. of gate counts. • More reliable. • Easier customer support. • Power Consumption is Low.
  • 21. Limitations: • Additional silicon area and fab processing requirements for the BIST circuits. • Additional pin requirements. • Reduced access times. • It uses more memory.
  • 22. Future Scope:  Timing required for Motion Estimation will be reduced.  The input to the MECA is 8-bit data. It also can be extended to higher volume of data.  BIST can used in Flash memory type of Systems.
  • 23. Tools:  Software : Xilinx 12.3, Mat lab  Language: Verilog
  • 24. Conclusion: Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays is the project that is to decrease the errors in the video sequence and make the video more reliable to watch & Also estimates the tracking of a person & object.