1. Shikhar Jain
M. Tech (Microelectronics & VLSI), IIT Hyderabad
email: EE14MTECH11022@iith.ac.in, sigmashikhar@gmail.com
Ph : (Cell) +91 - 9603739476
Web : https://in.linkedin.com/pub/shikhar-jain/a2/800/ab4
Objective:
To excel in the field of Microelectronics & VLSI and make a steady progress by constantly updating my
knowledge and enhancing my practical skills so that I become a better engineer everyday and hence my
knowledge comes to use of the society.
Areas of Interest:
Digital and Analog system design, ASIC/FPGA Implementation, Semiconductor Devices
Education:
• M.Tech (Microelectronics & VLSI) 2014–2016
(Teaching Assistance Program with GATE Scholarship)
Indian Institute of Technology, Hyderabad.
CGPA: 7.7/10
• B.E (Electronics and Telecommunication Engineering) 2008-2012
Bhilai Institute of Technology, Durg
CGPA: 8.19/10
Technical Skills:
• Programming: Verilog,C, MATLAB, 8051 Assembly language, basics of DSP Assembly language.
• VLSI EDA tools: Xilinx ISE, Modelsim, Cadence Virtuoso.
• Physics CAD: Silvaco TCAD.
• Hardware: Hands on experience with Lithography, Oxidation.
Relevant Course Works:
Digital IC Design, Analog IC Design, Digital Signal Processing, Embedded Systems, VLSI Technology,
Semiconductor Device Modeling, VLSI Design lab, Microelectronics lab, DSP lab, Device Simulation Lab.
Academic Projects:
M.Tech (EE), IIT Hyderabad
1. Analysis of cavity introduced aperture coupled feed micro-strip patch antenna. In this project
the effect of cavity is analyzed in aperture coupled antenna. Return loss, VSWR and Radiation pattern
of antenna is observed using HFSS simulation software.
2. Cu-Cu bonding with Nickel passivation (In Progress): The project involves thermo-compressive
bonding of silicon wafers and to examine the effect of Nickel passivation on bond strength,
conductivity, and stability.
3. CORDIC Algorithm Implementation: The aim of project was to calculate angle of given vector and
rotate existing vector by that angle that can be used for object trace. CORDIC algorithm was used in
the implementation to reduce the hardware complexity. Synthesis, Floor planning and place & route
were performed using Synopsys DC Compiler and IC complier tools respectively.

2. 4. RTL implementation of 32 point fft: The aim of the project was implementing 32 point fft using
verilog HDL and netlist generation using DC compiler (Synopsis EDA tool).
5. SILVACO/TCAD Simulation of silicon on insulator (SOI): The aim of the project was simulation
and characterization of Fully Depleted SOI as SiO2 as dielectric and comparison of the same with
different oxide HfO2 and SiGe instead of Si thin film. Silvaco(TCAD tool) was used for the process.
OTHER PROJECTS
• FPGA implementation of floating point multiplier
• ECG signal comparison to monitor health of patient using ARM NXP LPC1768.
• BGR and two stage amplifier design in cadence.
Hobbies:
• Singing
• Play Chess
Personal Details:
Date of Birth : 27 July 1989
Present Address : Room No: 640, Boys Hostel, IIT Hyderabad,
ODF Campus, Yeddumailaram, Medak-502205
Permanent Address : Varsha Kirana Stores, Nirmal Chowk, Rasmara
Durg, Chhattisgarh (491001)
Languages Known : English, Hindi and Telugu
Declaration:
I hereby declare that the above mentioned information is true to the best of my knowledge and belief.
Shikhar Jain