Design of 32 Bit Processor Using 8051 and Leon3 (Progress Report)

1. Title: Design and Development
of a General Purpose Processor
PERIOD: 13 FEB 2017 – 12 FEB 2018
TALAL KHALIQ
MSEE-7 (DSSP)
SUPERVISOR: DR. AWAIS M. KAMBOH

2. Background
 Commercial companies like Intel, AMD, ARM that design/produce
general purpose processors have following resources at their disposal
 Large teams of hundred of engineers
 3-5 years for design of a processor
 Access to state-of-the-art design & verification tools
 Access to fast IC technologies, e.g. 22nm, 32nm, 45nm…
 Access to IP cores such as cache, SRAM and memory controllers
 Several hundred man-years of experience
 Software design support for instruction-set, assembler, compiler
design

3. Purpose & Objective
 Purpose: To explore the design of a single core 32-bit general purpose
processor which is synthesizable on an FPGA
 Objective: To obtain a processor architecture on which further
components could be added for improved and increased functionality.
 Plan: Start with an open source processor, add new peripherals to suite
our needs.

4. Deliverables
 Report: Basic architecture of a 32-bit general purpose processor
 Code: Synthesizable processor core in Verilog / VHDL
 Final report and source code

5. Milestones
1. 8-bit Processor: 8051
 Obtain, Simulate, and Synthesize Open Source code for 8-bit 8051
 Implementation on FPGA
 Compile and Test custom program on FPGA
 Understand architecture
 Add custom peripheral and testing its functionality
2. 32-bit Processor: LEON-3
1. Setup software tool chain for Leon-3
2. Understand advanced components e.g. Memory Management Unit
Timeline
 Feb 2017
 Mar 2017
 Apr 2017
 May 2017
 July 2017
1. Sep 2017
2. Nov 2017

6. Selection of 8 bit Processor (8051 uC)
An Open Source IP Core for 8051 Microcontroller written in VHDL from Oregano
Systems was chosen. Its main features due to which it was chosen are as under:
Instruction set compatible to the industry standard 8051 microcontroller
Active timer/counter and serial interface units selectable via additional special
function register
Parameterizeable via VHDL constants
256 bytes internal RAM
Up to 64 Kbytes ROM and up to 64 Kbytes External RAM
Source code freely available

7. 8051 Core Top Module

8. Synthesis on FPGA (8051 uC)
Hardware
FPGA :Xilinx Virtex-5 ML507 Student Evaluation Board
Software
Xilinx ISE Design Suite 14.5
Keil C51
Hex to COE Conversion Tools

9. Synthesis on FPGA (8051 uC)
Top module for 8051 was written in VHDL which used:
8051 Core
Memory Cores using Core Generator:
128 x 8 RAM
64k x 8 ROM
64k x 8 External RAM
PLL Core (100MHz board clock to 11.675MHz)

10. RTL Schematic (8051 uC)

11. Implementation on FPGA (8051 uC)
~One Constraint of min clock period 10 ns not met (Setup Violation)

12. Adding Peripherals (8051 uC)
 Original design uses 74 I/Os with:
 2x Timers
 1x Serial Port
 2x External Interrupt Units
 Modified peripherals
 4x Timers
 2x Serial Port
 3x External Interrupt Units

13. 32-bit Processor: Leon3 Introduction
 Leon 3 is 32 bit processor based on SPARC V8 Architecture
 Support for Multiprocessing Configurations
 7 Stage Pipeline
 Can achieve 125 MHz on FPGA and 400 MHz on 0.13um ASICs
 Optional high performance IEEE-754 Floating Point Unit
 Optional SPARC Reference Memory Management Unit

14. Leon3 Advantages
 Open Source in VHDL and netlist
 Multiprocessor Support
 Configuration through GRLIB
 Support for FPGAs and ASICs
 Uniform Method for Hardware & Software debug
 Hardware (excluding EDA Tools) & Software tools are downloadable

15. Leon3 SoC Architecture

16. Software Required (Leon3)
EDA Tools
Xilinx ISE Design Suite
Xilinx Vivado HLS
Modelsim
GRTools
Leon IDE including Eclipse
GRMON2 eval
TSIM2 eval
For Linux:
Ubuntu 14 and above
For Windows:
Cygwin
Bash for Ubuntu (Windows 10)

17. GRLIB Configuration (Leon3)

18. GRLIB Synthesis and Simulation (Leon3)

19. What we want to achieve (Leon3)
 We will use same design process as in 8051 uC
 It will involve:
 Simulation
 Synthesis,
 Compilation of program
 Test of pre-configured peripherals on an FPGA
 New peripherals to enhance the processor's capabilities, and to adapt them for
better performance in a given domain of applications
 Compiler customization as per requirements

20. THANK YOU