This presentation has given a brief introduction and working of CMOS Logic Structures which includes MOS logic, CMOS logic, CMOS logic structure, CMOS complementary logic, pass transistor logic, bi CMOS logic, pseudo –nMOS logic, CMOS domino logic, Cascode Voltage Switch Logic(CVSL), clocked CMOS logic(c²mos), dynamic CMOS logic
3. CMOS stands for "Complementary Metal Oxide Semiconductor." It is a
technology used to produce integrated circuits.
CMOS circuits are found in several types of electronic components,
including microprocessors, batteries, and digital camera image sensors.
The "MOS" in CMOS refers to the transistors in a CMOS component,
called MOSFETs (metal oxide semiconductor field-effect transistors).
The "complimentary" part of CMOS refers to the two different types of
semiconductors each transistor contains N-type and P-type.
N-type semiconductors have a greater concentration of electrons than
holes, or places where an electron could exist. P-type semiconductors
have a greater concentration of holes than electrons.
4. Metal Oxide Semiconductor(MOS) structure is
created by superimposing several layers of
conducting and insulating materials to form a
sandwich like structure.
These structure are manufactured using a series of
chemical processing steps involving oxidation of the
silicon, selective introduction of dopant, and
deposition and etching of metal wires and contacts.
CMOS technology provides two types of transistor
an n-type transistor (nMOS) and p-type transistor
(pMOS).
Transistor operation is controlled by electric fields
so the devices are also called Metal Oxide
Semiconductor Field Effect Transistor (MOSFETs).
5. A complementary metal-oxide semiconductor (CMOS) consists of a
pair of semiconductors connected to a common secondary voltage
such that they operate in opposite (complementary) fashion.
CMOS is a combination of both NMOS and PMOS technology.
Thus, when one transistor is turned on, the other is turned off, and
vice versa.
CMOS can be used a invertor, but NMOS and PMOS alone used a
inverter. They are not enough to produce full output swing.
NMOS is not good enough to produce logic one strongly.
At the same time PMOS is not good enough to produce strong logic
zero. Some value may be degradated in the output value.
So to get full output swing for logic zero and logic one, we go for
CMOS.
6. In general, a static CMOS gate has
An NMOS pull-down network
to connect the output to 0 (GND)
and
PMOS pull-up network to
connect the output to 1 (VDD)
In general, when we join a pull-up
network to a pull-down network to
form a logic gate, they both will
attempt to exert a logic level at the
output.
7. VDD is connected to the source terminal of
pMOS and GND is connected to the source
terminal of nMOS.
When the input Vin is logic 0, the NMOS
transistor is OFF and the PMOS transistor is
ON.
The output is pulled up to logic 1 because
PMOS is connected to VDD. So PMOS is
called pull up transistor/ network.
When the input Vin is logic 1, the NMOS is
ON and PMOS is OFF.
Then Vout is pulled down to logic ‘0’, because
NMOS is connected to GND. So NMOS is
known as Pull down transistor/ network.
8. P1 and P2 are the PMOS of pull up network
connected in parallel.
N1 and N2 are the NMOS of pull down network
connected in series.
The PMOS transistor will allow strong 0 so if
anyone of the input is zero (since they are
connected in parallel) the output will become
logic 1.
The NMOS transistor will allow strong 1 so if
both the input are one (since they are connected
in series) the output will become logic 0.
9. P1 and P2 are the PMOS of pull up network
connected in series.
N1 and N2 are the NMOS of pull down network
connected in parallel.
The PMOS transistor will allow strong o so if
both the input are zero (since they are
connected in series) the output will become
logic 1.
The NMOS transistor will allow strong 1 so if
anyone of the input is one (since they are
connected in parallel) the output will become
logic 0.
10. In electronic, pass transistor logic(PTL) describes several logic families
used in the design of integrated circuits.
It reduces the count of transistor used to make different logic gates, by
eliminating redundant transistor.
In conventional logic families input is applied to gate terminal of
transistor but in PTL it is also applied to source/ drain terminal.
These circuits act as switches use either NMOS transistor or parallel
pair of NMOS and PMOS transistor called Transmission gate.
The width of the PMOS is taken equal to the NMOS so that both
transistor can pass the signal simultaneously in parallel.
Disadvantages is that output level are always lower than the input level.
11. A simple BiCMOS inverter can be constructed
from a pair of MOS transistor and NPN
transistors.
Each of the MOS transistors are cascaded with
an NPN transistor.
When the input is HIGH, the NMOS
transistor is conducting becoming the base
current for the Q2 NPN transistor causing the
discharge current to drop.
Conversely when the input is LOW, the PMOS
transistor is conducting becoming the base
current for the Q1 NPN transistor, causing the
output the increase.
12. In pseudo NMOS, we have one PMOS which is
connected to power supply VDD and to GND in the
input terminal.
There is an pull down network where NMOS are been
used depending on the required NMOS the input
varies.
When compared to static CMOS(2n transistor) the
number of input terminal in pseudo NMOS will be N+1
(i.e n NMOS and one PMOS).
PMOS transistor is always ON, because it is connected
to GND.
When input is 0, NMOS is OFF and o/p voltage will be
1 , because PMOS is always conducting.
When input is 1, NMOS is ON and PMOS is always
ON. So there will a direct path between VDD and
GND. Since both are conducting we will not get the
output as exact zero.
13. The basic difference between static CMOS and
dynamic CMOS is that, the total no. of transistor is way
greater in static CMOS when compared to dynamic
CMOS.
In dynamic CMOS, we avoid PMOS fabrication in its
structure and only less no. of NMOS are used.
So the total size as well as the capacitance loading will
be less when compared to static CMOS.
Switching characteristics is faster in dynamic CMOS
when compared to static CMOS.
It generally consists of a PDN that is constructed
identically to a CMOS PDN, but instead of a PUN, it
has a pair of complementary transistors that connected
to the clock. These divide the operation of the dynamic
gate into Precharge and Evaluation phases.
14. • When the clock is low (“Precharge”), the PDN is off
(regardless of it’s logic state) and the Precharge
transistor is open, providing a high value to the
output. When the clock toggles, the Evaluation
transistor (nMOS) opens, providing a conditional
discharge path, depending on the logic state of the
PDN. Thus, either the output is discharged to a low
value, or stays at its high output from the Precharge
stage.
15. In domino logic CMOS, we connect static
CMOS inverter at the output. This make the
difference between dynamic and domino
CMOS.
The total number of NMOS in domino logic
CMOS will be K no. of NMOS, one gated
NMOS and one NMOS in static inverter (i.e
NMOS = K+2).
The total number of PMOS in domino logic
CMOS will be one gated PMOS and one
PMOS in static inverter (i.e PMOS = 2).
16. When clk is 0 and i/p is 1, the clk terminal will be VDD based logic 1 and
by inverter the out 1 it will be logic 0, it will passed as i/p to the
cascading circuit, the clk terminal will be 1 and then the out 2 will be 0.
When clk is 1 and i/p is 1, the clk terminal will be VDD will start to
discharge (logic 0) and by inverter the out 1 it will be logic 1, it will
passed as i/p to the cascading circuit, the clk terminal will be 0 and then
the out 2 will be 1.
In dynamic we have false logic condition, but here there will be delayed
output. When there is more cascaded circuit the delay will be increasing.
17. It is also called as Differential Cascode
Voltage Switch Logic (DCVSL).
CVSL seeks the performance of pseudo
NMOS without the static power
consumption.
It is a differential type of logic circuits
where both true and complement inputs are
required.
N pull down tree are the dual of each other.
P pull up devices are cross coupled to latch
output.
Both true and complement outputs are
obtained.
18. Clocked-CMOS (C2MOS)(C2MOS) is a logic
family that combines static logic design with
the synchronization achieved by using clock
signals.
The inputs A, B, and C are connected to
complementary nFET/pFET pairs as in
ordinary static design where they act like
open or closed switches.
When the clock is at a level of ϕ=1 both Mn
and Mp are biased active.
the circuit when ϕ=0 and both Mn and Mp
are in cutoff.
This isolates the output node from both logic
arrays and the value of Vout=VResult is held
on Cout.
19. This presentation has given a brief introduction and working of CMOS
Logic Structures which includes MOS logic, CMOS logic, CMOS logic
structure, CMOS complementary logic, pass transistor logic, bi CMOS
logic, pseudo –nMOS logic, CMOS domino logic, Cascode Voltage
Switch Logic(CVSL), clocked CMOS logic(c²mos), dynamic CMOS
logic
