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Round-Robin Arbiter Tutorial

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dennis gookyi

The document describes a round-robin arbiter module that determines which master can use a shared bus. It uses a rotating priority scheme to grant access to each master in turn. The arbiter logic includes request detection, priority encoding, state tracking to grant the next master, and arbitration logic to assert the appropriate grant lines. Verification is done through testing and simulation of sample waveforms.

Engineering
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CCoonntteenntt  Round-Robin Arbiter Module 2
RRoouunndd--RRoobbiinn AArrbbiitteerr  In a shared bus, the arbiter determines which master can use the bus  The bus is granted on a rotary basis much like the four position rotary switch shown below:  When a master relinquishes the bus, the switch is turned to the next position and the bus is granted to the master on the level  In this way all masters are granted the bus on an equal basis 3 MASTER #0 MASTER #3 MASTER #2 MASTER #1
RRoouunndd--RRoobbiinn AArrbbiitteerr  Arbiter general topology: 4 LASMAS STATE MACHINE REGISTER COMCYC LOGIC ENCODER LOGIC ARBITRATION LOGIC GNT3 GNT3 GNT2 GNT1 GNT0 GNT2 GNT1 GNT0 GNT(1..0) CLK CLK CLK LMAS1 LMAS0 RST CYC3 CYC2 CYC1 CYC0 RST_I COMCYC LASMAS CE
RRoouunndd--RRoobbiinn AArrbbiitteerr  Bus requests arrive at inputs [ CYC0] to [CYC3]  If bus is free, one of the 4 grant lines ([GNT0] to [GNT1]) is asserted which corresponds to the request signals 5
Round-RRoobbiinn AArrbbiitteerr:: CCOOMMCCYYCC  The [COMCYC] indicates whether the bus is free or busy  It is asserted whenever a master has both requested the bus and has been granted the bus by the arbiter 6
Round-RRoobbiinn AArrbbiitteerr:: CCOOMMCCYYCC  Inputs and outputs:  COMCYC logic diagram: GNT_3 COMCYC = (CYC3 & GNT3)||(CYC2 & GNT2)|| (CYC1 & GNT1)||(CYC0 & GNT0); 7 Inputs Output CYC_3, CYC_2, CYC_1, CYC_0 GNT_3, GNT_2, GNT_1, GNT_0 COMCYC CYC_3 CYC_2 GNT_2 CYC_1 GNT_1 CYC_0 GNT_0 COMCYC
Round-Robin AArrbbiitteerr:: EEnnccooddeerr LLooggiicc  Grant line [GNT0] to [GNT3] are encoded as [GNT(1..0)]  This is used with the [COMCYC] signal to indicate which master has been granted the bus  When [COMCYC] is asserted, the master located on [GNT(1..0)] is granted the bus 8
Round-Robin AArrbbiitteerr:: EEnnccooddeerr LLooggiicc  Inputs and outputs:  Encoder logic diagram: 9 Inputs Outputs GNT_3, GNT_2, GNT_1, GNT_0 GNT[1], GNT[0] GNT_3 GNT_1 GNT[1] = GNT_2 || GNT_3 GNT[0] = GNT3 || GNT1 GNT_2 0 0 0 0 0 GNT_3 GNT_2 GNT_1 GNT_0 GNT[1] GNT[0] 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1
Round-RRoobbiinn AArrbbiitteerr:: LLAASSMMAASS  Round-robin arbiters keep track of the level of the previous master  The level is saved in a register that latches the state of grant signals [GNT(1..0)]  The register latches the grant signal when indicated by the LASMAS state machine 10 CE
Round-RRoobbiinn AArrbbiitteerr:: LLAASSMMAASS  LASMAS state machine: state diagram State = {EDG,LASMAS}  Input logic: Input = BEG BEG= (CYC0 || CYC1 || CYC2 || CYC3) & (~COMCYC);  From the state diagram: EDG= ( BEG & ~EDG & LASMAS) || ( BEG & EDG & ~LASMAS ); LASMAS = ( BEG & ~EDG & ~LASMAS ); 11 CYC0 CYC1 CYC2 CYC3 COMCYC BEG
Round-Robin AArrbbiitteerr:: BBuuss TTooppoollooggyy  The arbitration logic is as below: 12 MASTER #0 MASTER #3 MASTER #2 MASTER #1
Round-Robin AArrbbiitteerr:: BBuuss TTooppoollooggyy  The arbitration logic is as below: GNT0 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & ~CYC3 & ~CYC2 & ~CYC1 & CYC0 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC0 ) || ( ~RST & COMCYC & GNT0 ); GNT1 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC1 ~CYC0 ) || ( ~RST & COMCYC & GNT1 ); GNT2 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 CYC2 & ~CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 CYC2 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC2 & ~CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 CYC2 & ~CYC1 & ~CYC0 ) || ( ~RST & COMCYC & GNT2 ); GNT3 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC3 & ~CYC2 & ~CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & CYC3 & ~CYC2 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & CYC3 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC3 & ~CYC2 & ~CYC1 & ~CYC0 ) 13 MASTER #0 MASTER #3 MASTER #2 MASTER #1
Round-Robin AArrbbiitteerr:: BBuuss TTooppoollooggyy  The arbitration logic is as below: GNT0 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & ~CYC3 & ~CYC2 & ~CYC1 & CYC0 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC0 ) || ( ~RST & COMCYC & GNT0 ); GNT1 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC1 ~CYC0 ) || ( ~RST & COMCYC & GNT1 ); GNT2 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 CYC2 & ~CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 CYC2 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC2 & ~CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 CYC2 & ~CYC1 & ~CYC0 ) || ( ~RST & COMCYC & GNT2 ); GNT3 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC3 & ~CYC2 & ~CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & CYC3 & ~CYC2 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & CYC3 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC3 & ~CYC2 & ~CYC1 & ~CYC0 ) 14 MASTER #0 MASTER #3 MASTER #2 MASTER #1
Round-Robin AArrbbiitteerr:: BBuuss TTooppoollooggyy  The arbitration logic is as below: GNT0 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & ~CYC3 & ~CYC2 & ~CYC1 & CYC0 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC0 ) || ( ~RST & COMCYC & GNT0 ); GNT1 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC1 ~CYC0 ) || ( ~RST & COMCYC & GNT1 ); GNT2 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 CYC2 & ~CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 CYC2 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC2 & ~CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 CYC2 & ~CYC1 & ~CYC0 ) || ( ~RST & COMCYC & GNT2 ); GNT3 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC3 & ~CYC2 & ~CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & CYC3 & ~CYC2 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & CYC3 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC3 & ~CYC2 & ~CYC1 & ~CYC0 ) 15 MASTER #0 MASTER #3 MASTER #2 MASTER #1
RRoouunndd--RRoobbiinn AArrbbiitteerr  Code 16
RRoouunndd--RRoobbiinn AArrbbiitteerr  Code: 17
RRoouunndd--RRoobbiinn AArrbbiitteerr  RTL schematic 18
RRoouunndd--RRoobbiinn AArrbbiitteerr  Testbench 19
Round-RRoobbiinn AArrbbiitteerr:: wwaavveeffoorrmm  Cyc0 request and is granted the bus 20 cyc0 is granted the bus
Round-RRoobbiinn AArrbbiitteerr:: wwaavveeffoorrmm  Cyc1 and cyc2 both request the bus at the same time 21 comcyc is negated to indicate that the bus is free
Round-RRoobbiinn AArrbbiitteerr:: wwaavveeffoorrmm  Bus granted to cyc1 22 Bus granted to cyc1 because it is next in line
Round-RRoobbiinn AArrbbiitteerr:: wwaavveeffoorrmm  Cyc3 request for bus and is granted 23 Bus granted to cyc3

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Round-Robin Arbiter Tutorial

  • 1. WWiisshhbboonnee TTuuttoorriiaallss GGooookkyyii DDeennnniiss AA.. NN.. SSooCC DDeessiiggnn LLaabb.. October.17.2014
  • 3. RRoouunndd--RRoobbiinn AArrbbiitteerr  In a shared bus, the arbiter determines which master can use the bus  The bus is granted on a rotary basis much like the four position rotary switch shown below:  When a master relinquishes the bus, the switch is turned to the next position and the bus is granted to the master on the level  In this way all masters are granted the bus on an equal basis 3 MASTER #0 MASTER #3 MASTER #2 MASTER #1
  • 4. RRoouunndd--RRoobbiinn AArrbbiitteerr  Arbiter general topology: 4 LASMAS STATE MACHINE REGISTER COMCYC LOGIC ENCODER LOGIC ARBITRATION LOGIC GNT3 GNT3 GNT2 GNT1 GNT0 GNT2 GNT1 GNT0 GNT(1..0) CLK CLK CLK LMAS1 LMAS0 RST CYC3 CYC2 CYC1 CYC0 RST_I COMCYC LASMAS CE
  • 5. RRoouunndd--RRoobbiinn AArrbbiitteerr  Bus requests arrive at inputs [ CYC0] to [CYC3]  If bus is free, one of the 4 grant lines ([GNT0] to [GNT1]) is asserted which corresponds to the request signals 5
  • 6. Round-RRoobbiinn AArrbbiitteerr:: CCOOMMCCYYCC  The [COMCYC] indicates whether the bus is free or busy  It is asserted whenever a master has both requested the bus and has been granted the bus by the arbiter 6
  • 7. Round-RRoobbiinn AArrbbiitteerr:: CCOOMMCCYYCC  Inputs and outputs:  COMCYC logic diagram: GNT_3 COMCYC = (CYC3 & GNT3)||(CYC2 & GNT2)|| (CYC1 & GNT1)||(CYC0 & GNT0); 7 Inputs Output CYC_3, CYC_2, CYC_1, CYC_0 GNT_3, GNT_2, GNT_1, GNT_0 COMCYC CYC_3 CYC_2 GNT_2 CYC_1 GNT_1 CYC_0 GNT_0 COMCYC
  • 8. Round-Robin AArrbbiitteerr:: EEnnccooddeerr LLooggiicc  Grant line [GNT0] to [GNT3] are encoded as [GNT(1..0)]  This is used with the [COMCYC] signal to indicate which master has been granted the bus  When [COMCYC] is asserted, the master located on [GNT(1..0)] is granted the bus 8
  • 9. Round-Robin AArrbbiitteerr:: EEnnccooddeerr LLooggiicc  Inputs and outputs:  Encoder logic diagram: 9 Inputs Outputs GNT_3, GNT_2, GNT_1, GNT_0 GNT[1], GNT[0] GNT_3 GNT_1 GNT[1] = GNT_2 || GNT_3 GNT[0] = GNT3 || GNT1 GNT_2 0 0 0 0 0 GNT_3 GNT_2 GNT_1 GNT_0 GNT[1] GNT[0] 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1
  • 10. Round-RRoobbiinn AArrbbiitteerr:: LLAASSMMAASS  Round-robin arbiters keep track of the level of the previous master  The level is saved in a register that latches the state of grant signals [GNT(1..0)]  The register latches the grant signal when indicated by the LASMAS state machine 10 CE
  • 11. Round-RRoobbiinn AArrbbiitteerr:: LLAASSMMAASS  LASMAS state machine: state diagram State = {EDG,LASMAS}  Input logic: Input = BEG BEG= (CYC0 || CYC1 || CYC2 || CYC3) & (~COMCYC);  From the state diagram: EDG= ( BEG & ~EDG & LASMAS) || ( BEG & EDG & ~LASMAS ); LASMAS = ( BEG & ~EDG & ~LASMAS ); 11 CYC0 CYC1 CYC2 CYC3 COMCYC BEG
  • 12. Round-Robin AArrbbiitteerr:: BBuuss TTooppoollooggyy  The arbitration logic is as below: 12 MASTER #0 MASTER #3 MASTER #2 MASTER #1
  • 13. Round-Robin AArrbbiitteerr:: BBuuss TTooppoollooggyy  The arbitration logic is as below: GNT0 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & ~CYC3 & ~CYC2 & ~CYC1 & CYC0 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC0 ) || ( ~RST & COMCYC & GNT0 ); GNT1 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC1 ~CYC0 ) || ( ~RST & COMCYC & GNT1 ); GNT2 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 CYC2 & ~CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 CYC2 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC2 & ~CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 CYC2 & ~CYC1 & ~CYC0 ) || ( ~RST & COMCYC & GNT2 ); GNT3 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC3 & ~CYC2 & ~CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & CYC3 & ~CYC2 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & CYC3 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC3 & ~CYC2 & ~CYC1 & ~CYC0 ) 13 MASTER #0 MASTER #3 MASTER #2 MASTER #1
  • 14. Round-Robin AArrbbiitteerr:: BBuuss TTooppoollooggyy  The arbitration logic is as below: GNT0 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & ~CYC3 & ~CYC2 & ~CYC1 & CYC0 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC0 ) || ( ~RST & COMCYC & GNT0 ); GNT1 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC1 ~CYC0 ) || ( ~RST & COMCYC & GNT1 ); GNT2 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 CYC2 & ~CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 CYC2 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC2 & ~CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 CYC2 & ~CYC1 & ~CYC0 ) || ( ~RST & COMCYC & GNT2 ); GNT3 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC3 & ~CYC2 & ~CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & CYC3 & ~CYC2 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & CYC3 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC3 & ~CYC2 & ~CYC1 & ~CYC0 ) 14 MASTER #0 MASTER #3 MASTER #2 MASTER #1
  • 15. Round-Robin AArrbbiitteerr:: BBuuss TTooppoollooggyy  The arbitration logic is as below: GNT0 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & ~CYC3 & ~CYC2 & ~CYC1 & CYC0 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC0 ) || ( ~RST & COMCYC & GNT0 ); GNT1 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC1 ~CYC0 ) || ( ~RST & COMCYC & GNT1 ); GNT2 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 CYC2 & ~CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 CYC2 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC2 & ~CYC1 & ~CYC0 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 CYC2 & ~CYC1 & ~CYC0 ) || ( ~RST & COMCYC & GNT2 ); GNT3 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC3 & ~CYC2 & ~CYC1 ) || ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & CYC3 & ~CYC2 ) || ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & CYC3 ) || ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC3 & ~CYC2 & ~CYC1 & ~CYC0 ) 15 MASTER #0 MASTER #3 MASTER #2 MASTER #1
  • 20. Round-RRoobbiinn AArrbbiitteerr:: wwaavveeffoorrmm  Cyc0 request and is granted the bus 20 cyc0 is granted the bus
  • 21. Round-RRoobbiinn AArrbbiitteerr:: wwaavveeffoorrmm  Cyc1 and cyc2 both request the bus at the same time 21 comcyc is negated to indicate that the bus is free
  • 22. Round-RRoobbiinn AArrbbiitteerr:: wwaavveeffoorrmm  Bus granted to cyc1 22 Bus granted to cyc1 because it is next in line
  • 23. Round-RRoobbiinn AArrbbiitteerr:: wwaavveeffoorrmm  Cyc3 request for bus and is granted 23 Bus granted to cyc3