AUDIENCE THEORY -CULTIVATION THEORY - GERBNER.pptx
Apache track d updated
1. Comprehensive Low Power Design Analysis and Optimization An RTL to GDSII Approach Aveek Sarkar and Ronen Stilkol Apache Design Solutions
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5. Power in the RTL GDS II Flow Target power reduction early in the design flow Ensure design verification to predict voltage drop noise from low power techniques Power reduction Usage Curve Power Integrity Usage Curve Physical Implementation & Signoff RTL Design & reduction Floor-planning & Synthesis Chip-Package-System Convergence
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7. Operational Power Reduction Clock Tree Optimization RTL: Add and Improve Clock Enables Non-enabled Enabled sel sel_1d 1 R2 D RTL reductions make clock gating more effective EN CLK CG GCLK D EN CLK D Synthesis: Clock Gating RTL Gates